CYBLE-014008-00_技术文档

CYBLE-014008-00

EZ-BLE™ PSoC^®Module

■ Low power mode support

❐ Deep Sleep: 1.3 µA with watch crystal oscillator (WCO) on

❐ Hibernate: 150 nA with SRAM retention

General Description

The Cypress CYBLE-014008-00 is a fully certified and qualified

module supporting Bluetooth^Low Energy (BLE) wireless

communication. The CYBLE-014008-00 is a turnkey solution

and includes onboard crystal oscillators, trace antenna, passive

components, and the Cypress PSoC^®4 BLE. Refer to the

PSoC^®4 BLE datasheet for additional details on the capabilities

of the PSoC 4 BLE device used on this module.

❐ Stop: 60 nA with GPIO (P2.2) or XRES wakeup

Programmable Analog

■ Four opamps with reconfigurable high-drive external and

high-bandwidth internal drive, comparator modes, and ADC

input buffering capability; can operate in Deep-Sleep mode

^{The EZ-BLE} PSoC^®module is a scalable and reconfigurable

platform architecture. It combines programmable and

reconfigurable analog and digital blocks with flexible automatic

routing. The CYBLE-014008-00 also includes digital

programmable logic, high-performance analog-to-digital

conversion (ADC), opamps with comparator mode, and standard

communication and timing peripherals.

■ 12-bit, 1-Msps SAR ADC with differential and single-ended

modes; channel sequencer with signal averaging

■ Two current DACs (IDACs) for general-purpose or capacitive

sensing applications on any pin

■ One low-power comparator that operate in Deep-Sleep mode

Programmable Digital

The CYBLE-014008-00 includes a royalty-free BLE stack

compatible with Bluetooth 4.1 and provides up to 25 GPIOs in a

small 11 × 11 × 1.80 mm package.

■ Four programmable logic blocks called universal digital blocks,

(UDBs), each with eight macrocells and datapath

■ Cypress-provided peripheral Component library, user-defined

state machines, and Verilog input

The CYBLE-014008-00 is a complete solution and an ideal fit for

applications seeking a highly integrated BLE wireless solution.

Capacitive Sensing

Module Description

■ Cypress CapSense Sigma-Delta (CSD) provides best-in-class

SNR (> 5:1) and liquid tolerance

■ Module size: 11.0 mm × 11.0 mm × 1.80 mm (with shield)

■ 128-KB flash memory, 16-KB SRAM memory

■ Cypress-supplied software component makes

capacitive-sensing design easy

■ Up to 25 GPIOs configurable as open drain high/low,

pull-up/pull-down, HI-Z analog, HI-Z digital, or strong output

■ Automatic hardware-tuning algorithm (SmartSense™)

■ Bluetooth 4.1 qualified single-mode module

❐ QDID: 79697

❐ Declaration ID: D029647

Segment LCD Drive

■ LCD drive supported on all GPIOs (common or segment)

■ Operates in Deep-Sleep mode with four bits per pin memory

■ Certified to FCC, CE, MIC, KC, and IC regulations

■ Industrial temperature range: –40 °C to +85 °C

Serial Communication

■ Two independent runtime reconfigurable serial communication

■ 32-bit processor (0.9 DMIPS/MHz) with single-cycle 32-bit

blocks (SCBs) with I²C, SPI, or UART functionality

multiply, operating at up to 48 MHz

Timing and Pulse-Width Modulation

■ Watchdog timer with dedicated internal low-speed oscillator

(ILO)

■ Four 16-bit timer, counter, pulse-width modulator (TCPWM)

blocks

■ Two-pin SWD for programming

■ Center-aligned, Edge, and Pseudo-random modes

■ Comparator-based triggering of Kill signals for motor drive and

other high-reliability digital logic applications

Power Consumption

■ TX output power: –18 dbm to +3 dbm

Up to 25 Programmable GPIOs

■ Received signal strength indicator (RSSI) with 1-dB resolution

■ TX current consumption of 15.6 mA (radio only, 0 dbm)

■ RX current consumption of 16.4 mA (radio only)

■ Any GPIO pin can be CapSense, LCD, analog, or digital

Cypress Semiconductor Corporation

Document Number: 002-00023 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 22, 2017

CYBLE-014008-00

More Information

Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to

quickly and effectively integrate the module into your design.

■ Overview: EZ-BLE Module Portfolio, Module Roadmap

■ EZ-BLE PSoC Product Overview

■ Knowledge Base Articles

❐ KBA97279 - Pin Mapping Differences Between the

EZ-BLE™ PRoC™ Evaluation Board

(CYBLE-014008-EVAL) and the BLE Pioneer Kit

(CY8CKIT-042-BLE)

❐ KBA210574 - RF Regulatory Certifications for CY-

BLE-014008-00 and CYBLE-214009-00 EZ-BLE™ PSoC^®

Modules - KBA210574

■ PSoC 4 BLE Silicon Datasheet

■ Application notes: Cypress offers a number of BLE application

notes covering a broad range of topics, from basic to advanced

level. Recommended application notes for getting started with

EZ-BLE modules are:

❐ KBA97095 - EZ-BLE™ Module Placement

❐ KBA213976 -FAQ for BLE and Regulatory Certifications with

EZ-BLE modules

❐ KBA210802 - Queries on BLE Qualification and Declaration

Processes

❐ AN96841 - Getting Started with EZ-BLE Module

❐ AN94020 - Getting Started with PSoC^®4 BLE

❐ AN97060 - PSoC^®4 BLE and PRoC™ BLE - Over-The-Air

(OTA) Device Firmware Upgrade (DFU) Guide

❐ AN91162 - Creating a BLE Custom Profile

❐ AN91184 - PSoC 4 BLE - Designing BLE Applications

■ Development Kits:

❐ AN92584 - Designing for Low Power and Estimating Battery

❐ CYBLE-014008-EVAL, CYBLE-014008-00EvaluationBoard

❐ CY8CKIT-042-BLE, Bluetooth^®Low Energy (BLE) Pioneer

Life for BLE Applications

❐ AN85951 - PSoC^®4 CapSense^®Design Guide

Kit

❐ AN95089 - PSoC^®4/PRoC™ BLE Crystal Oscillator Selec-

❐ CY8CKIT-002, PSoC^®MiniProg3 Program and Debug Kit

tion and Tuning Techniques

■ Test and Debug Tools:

❐ AN91445 - Antenna Design and RF Layout Guidelines

❐ CYSmart, Bluetooth^®LE Test and Debug Tool (Windows)

■ Technical Reference Manual (TRM):

❐ CYSmart Mobile, Bluetooth^®LE Test and Debug Tool

❐ PSoC^®4 BLE Technical Reference Manual

(Android/iOS Mobile App)

❐ PSOC^®4 BLE Registers Technical Reference Manual (TRM)

Two Easy-To-Use Design Environments to Get You Started Quickly

®

PSoC Creator™ Integrated Design Environment (IDE)

PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and

debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, PRoC BLE and EZ-BLE module systems with no code size limitations. PSoC

peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified,

production-ready PSoC Components™.

PSoC Components are analog and digital “virtual chips,” represented by an icon that users can drag-and-drop into a design and

configure to suit a broad array of application requirements.

Blutooth Low Energy Component

The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you

quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.1 compliant BLE protocol stack and

provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS)

hardware via the stack.

EZ-Serial™ BLE Firmware Platform

The EZ-Serial Firmware Platform provides a simple way to access the most common hardware and communication features needed

in BLE applications. EZ-Serial implements an intuitive API protocol over the UART interface and exposes various status and control

signals through the module’s GPIOs, making it easy to add BLE functionality quickly to existing designs.

Use a simple serial terminal and evaluation kit to begin development without requiring an IDE. Refer to the EZ-Serial webpage for

User Manuals and instructions for getting started as well as detailed reference materials.

EZ-BLE modules are pre-flashed with the EZ-Serial Firmware Platform. If you do not have EZ-Serial pre-loaded on your module, you

can download each EZ-BLE module’s firmware images on the EZ-Serial webpage.

Technical Support

■ Frequently Asked Questions (FAQs): Learn more about our BLE ECO System.

■ Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE and PRoC BLE forums.

■ Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,

you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.

Document Number: 002-00023 Rev. *K

Page 2 of 43

CYBLE-014008-00

Contents

Overview............................................................................ 4

Module Description...................................................... 4

Pad Connection Interface ................................................ 6

Recommended Host PCB Layout ................................... 7

Digital and Analog Capabilities and Connections......... 9

Power Supply Connections and Recommended External

Components.................................................................... 11

Connection Options................................................... 11

External Component Recommendation .................... 11

Critical Components List ........................................... 14

Antenna Design......................................................... 14

Electrical Specification .................................................. 15

GPIO ......................................................................... 17

XRES......................................................................... 18

Analog Peripherals.................................................... 19

Digital Peripherals ..................................................... 22

Serial Communication ............................................... 24

Memory ..................................................................... 25

System Resources .................................................... 26

Environmental Specifications ....................................... 31

Environmental Compliance ....................................... 31

RF Certification.......................................................... 31

Environmental Conditions ......................................... 31

ESD and EMI Protection ........................................... 31

Regulatory Information.................................................. 32

FCC........................................................................... 32

Industry Canada (IC) Certification............................. 33

European R&TTE Declaration of Conformity ............ 33

MIC Japan................................................................. 34

KC Korea................................................................... 34

Packaging........................................................................ 35

Ordering Information...................................................... 37

Part Numbering Convention...................................... 37

Acronyms........................................................................ 38

Document Conventions ................................................. 40

Units of Measure ....................................................... 40

Document History Page................................................. 41

Sales, Solutions, and Legal Information ...................... 43

Worldwide Sales and Design Support....................... 43

Products.................................................................... 43

PSoC® Solutions ...................................................... 43

Cypress Developer Community................................. 43

Technical Support ..................................................... 43

Document Number: 002-00023 Rev. *K

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CYBLE-014008-00

Overview

Module Description

The CYBLE-014008-00 module is a complete module designed to be soldered to the main host board.

Module Dimensions and Drawing

Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE

module functionality. Such selections will guarantee that all height restrictions of the component area are maintained. Designs should

be completed with the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm).

Table 1. Module Design Dimensions

Dimension Item

Specification

Length (X) 11.00 ± 0.15 mm

Width (Y) 11.00 ± 0.15 mm

Length (X) 11.00 ± 0.15 mm

Width (Y) 4.62 ± 0.15 mm

Module dimensions

Antenna location dimensions

PCB thickness

Height (H) 0.80 ± 0.10 mm

Height (H) 1.00 ± 0.10 mm

Shield height

Maximum component height

Height (H) 1.00-mm typical (shield)

Total module thickness (bottom of module to highest component) Height (H) 1.80-mm typical

See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-014008-00.

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CYBLE-014008-00

Figure 1. Module Mechanical Drawing

Top View

Side View

Bottom View (Seen from Bottom)

Note

1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on

recommended host PCB layout, see Figure 3 on page 6, Figure 4 and Figure 5 on page 7, and Figure 6 and Table 3 on page 8.

Document Number: 002-00023 Rev. *K

Page 5 of 43

CYBLE-014008-00

Pad Connection Interface

As shown in the bottom view of Figure 1 on page 5, the CYBLE-014008-00 connects to the host board via solder pads on the back

of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-014008-00 module.

Table 2. Solder Pad Connection Description

Name Connections Connection Type

SP 32 Solder Pads

Pad Length Dimension

Pad Width Dimension

Pad Pitch

Pad9/Pad24: 0.74 mm

All Others: 0.79 mm

0.41 mm

0.66 mm

Figure 2. Solder Pad Dimensions (Seen from Bottom)

To maximize RF performance, the host layout should follow these recommendations:

1. The ideal placement of the Cypress BLE module is in a corner of the host board with the antenna located on the edge of the host

board. This placement minimizes the additional recommended keep-out area stated in item 2. Refer to AN96841 for module

placement best practices.

2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional

keep-out area, where no grounding or signal traces are contained. The keep-out area applies to all layers of the host board. The

recommended dimensions of the host PCB keep-out area are shown in Figure 3 (dimensions are in mm).

Figure 3. Recommended Host PCB Keep-Out Area Around the CYBLE-014008-00 Trace Antenna

Document Number: 002-00023 Rev. *K

Page 6 of 43

CYBLE-014008-00

Recommended Host PCB Layout

Figure 4 through Figure 6 and Table 3 provide details that can be used for the recommended host PCB layout pattern for the

CYBLE-014008-00. Dimensions are in millimeters unless otherwise noted. Pad length of 0.99 mm (0.494 mm from center of the pad

on either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed using

either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern.

Figure 4. Host Layout Pattern for CYBLE-014008-00

Figure 5. Module Pad Location from Origin

Top View (Seen on Host PCB)

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Page 7 of 43

CYBLE-014008-00

Table 3 provides the center location for each solder pad on the CYBLE-014008-00. All dimensions are referenced to the center of the

solder pad. Refer to Figure 6 for the location of each module solder pad.

Table 3. Module Solder Pad Location

Figure 6. Solder Pad Reference Location

Solder Pad

(Center of Pad)

Location (X,Y) from

Orign (mm)

Dimension from

Orign (mils)

1

(0.30, 4.83)

(0.30, 5.49)

(0.30, 6.15)

(0.30, 6.81)

(0.30, 7.47)

(0.30, 8.13)

(0.30, 8.79)

(0.30, 9.45)

(0.27, 10.11)

(1.21, 10.70)

(1.87, 10.70)

(2.53, 10.70)

(3.19, 10.70)

(3.85, 10.70)

(4.51, 10.70)

(5.17, 10.70)

(5.84, 10.70)

(6.50, 10.70)

(7.16, 10.70)

(7.82, 10.70)

(8.48, 10.70)

(9.14, 10.70)

(9.80, 10.70)

(10.73, 10.11)

(10.70, 9.45)

(10.70, 8.79)

(10.70, 8.13)

(10.70, 7.47)

(10.70, 6.81)

(10.70, 6.15)

(10.70, 5.49)

(10.70, 4.83)

(11.81, 190.16)

(11.81, 216.14)

(11.81, 242.13)

(11.81, 268.11)

(11.81, 294.09)

(11.81, 320.08)

(11.81, 346.06)

(11.81, 372.05)

(10.63, 398.03)

(47.64, 421.26)

(73.62, 421.26)

(99.61, 421.26)

(125.59, 421.26)

(151.57, 421.26)

(177.56, 421.26)

(203.54, 421.26)

(229.92, 421.26)

(255.91, 421.26)

(281.89, 421.26)

(307.87, 421.26)

(333.86, 421.26)

(359.84, 421.26)

(385.83, 421.26)

(422.44, 398.03)

(421.26, 372.05)

(421.26, 346.06)

(421.26, 320.08)

(421.26, 294.09)

(421.26, 268.11)

(421.26, 242.13)

(421.26, 216.14)

(421.26, 190.16)

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Top View (Seen on Host PCB)

Document Number: 002-00023 Rev. *K

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CYBLE-014008-00

Digital and Analog Capabilities and Connections

Table 4 and Table 5 detail the solder pad connection definitions and available functions for each connection pad. Table 4 lists the

solder pads on CYBLE-014008-00, the BLE device port-pin, and denotes whether the digital function shown is available for each

solder pad. Table 5 denotes whether the analog function shown is available for each solder pad. Each connection is configurable for

a single option shown with a ✓.

Table 4. Digital Peripheral Capabilities

Pad

Device

Cap

WCO ECO

UART

SPI

I²C

TCPWM^[2,3]

LCD

SWD

GPIO

Number Port Pin

Sense Out OUT

1

2

3

4

5

6

GND^[4]

P1.1

P1.0

P1.5

P0.1

P0.7

Ground Connection

✓(TCPWM)

✓(SCB1_SS1)

✓

✓(SCB0_TX) ✓(SCB0_MISO) ✓(SCB0_SCL)

✓(SCB1_TX) ✓(SCB1_MISO) ✓(SCB1_SCL)

✓(SCB0_CTS) ✓(SCB0_SCLK)

✓

(SWDCLK)

7

8

VDD

P1.4

P0.4

P0.5

P0.6

Digital Power Supply Input (1.71 to 5.5V)

✓(SCB0_RX) ✓(SCB0_MOSI) ✓(SCB0_SDA)

✓(SCB0_TX) ✓(SCB0_MISO) ✓(SCB0_SCL)

✓(SCB0_RTS) ✓(SCB0_SS0)

✓(TCPWM)

✓

9

✓

10

11

✓(TCPWM)

✓

(SWDIO)

✓

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

P1.2

V_DDR

P2.6

P1.3

P3.0

P2.1

P2.2

P2.3

VDDA

P3.4

P3.1

P3.7

P3.5

P3.3

VREF

P3.2

P3.6

XRES

P2.4

P2.5

GND

✓(SCB1_SS2)

✓(TCPWM)

Radio Power Supply (1.9V to 5.5V)

✓

✓(TCPWM)

✓

✓(SCB1_SS3)

✓(SCB0_RX)

✓(SCB0_SDA)

✓(SCB0_SS2)

✓(SCB0_SS3)

✓

Analog Power Supply Input (1.71 to 5.5V)

✓(SCB1_RX)

✓(SCB0_TX)

✓(SCB1_CTS)

✓(SCB1_TX)

✓(SCB0_CTS)

✓(SCB1_SDA)

✓(SCB0_SCL)

✓(TCPWM)

✓

✓(SCB1_SCL)

Reference Voltage Input

✓(SCB0_RTS)

✓(SCB1_RTS)

✓(TCPWM)

✓

External Reset Hardware Connection Input

✓(TCPWM)

✓

Ground Connection

Notes

2. TCPWM stands for timer, counter, and PWM. If supported, the pad can be configured to any of these peripheral functions.

3. TCPWM connections on ports 0, 1, 2, and 3 can be routed through the Digital Signal Interconnect (DSI) to any of the TCPWM blocks and can be either positive

or negative polarity.

4. The main board needs to connect both GND connections (Pad 1 and Pad 32) on the module to the common ground of the system.

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Page 9 of 43

CYBLE-014008-00

Table 5. Analog Peripheral Capabilities

Pad Number

Device Port Pin

GND^[4]

P1.1

SARMUX

OPAMP

LPCOMP

1

Ground Connection

2

✓(CTBm1_OA0_INN)

3

P1.0

✓(CTBm1_OA0_INP)

✓(CTBm1_OA1_INP)

4

P1.5

5

P0.1

6

P0.7

7

VDD

P1.4

Digital Power Supply Input (1.71 to 5.5V)

8

✓(CTBm1_OA1_INN)

9

P0.4

✓(COMP1_INP)

✓(COMP1_INN)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

P0.5

P0.6

P1.2

✓(CTBm1_OA0_OUT)

Radio Power Supply (1.9V to 5.5V)

V_DDR

P2.6

✓(CTBm0_OA0_INP)

✓(CTBm1_OA1_OUT)

P1.3

P3.0

✓

P2.1

✓(CTBm0_OA0_INN)

✓(CTBm0_OA0_OUT)

✓(CTBm0_OA1_OUT)

Analog Power Supply Input (1.71 to 5.5V)

P2.2

P2.3

VDDA

P3.4

✓

P3.1

P3.7

P3.5

P3.3

VREF

P3.2

Reference Voltage Input (Optional)

✓

P3.6

XRES

P2.4

External Reset Hardware Connection Input

✓(CTBm0_OA1_INN)

P2.5

✓(CTBm0_OA1_INP)

GND

Ground Connection

Document Number: 002-00023 Rev. *K

Page 10 of 43

CYBLE-014008-00

Power Supply Connections and Recommended External Components

Power Connections

External Component Recommendation

The CYBLE-014008-00 contains three power supply connec-

tions, VDD, VDDA, and VDDR. The VDD and VDDA connections

supply power for the digital and analog device operation respec-

tively. VDDR supplies power for the device radio.

In either connection scenario, it is recommended to place an

external ferrite bead between the supply and the module

connection. The ferrite bead should be positioned as close as

possible to the module pin connection.

VDD and VDDA accept a supply range of 1.71 V to 5.5 V. VDDR

accepts a supply range of 1.9 V to 5.5 V. These specifications

can be found in Table 10. The maximum power supply ripple for

both power connections on the module is 100 mV, as shown in

Table 8.

Figure 7 details the recommended host schematic options for a

single supply scenario. The use of one or three ferrite beads will

depend on the specific application and configuration of the

CYBLE-014008-00.

Figure 8 details the recommended host schematic for an

independent supply scenario.

The power supply ramp rate of VDD and VDDA must be equal

to or greater than that of VDDR when the radio is used.

The recommended ferrite bead value is 330 , 100 MHz (Murata

BLM21PG331SN1D).

Connection Options

Two connection options are available for any application:

1. Single supply: Connect VDD, VDDA, and VDDR to the same

supply.

2. Independent supply: Power VDD, VDDA, and VDDR

separately.

Figure 7. Recommended Host Schematic Options for Single Supply Option

Single Ferrite Bead Option (Seen from Bottom)

Three Ferrite Bead Option (Seen from Bottom)

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CYBLE-014008-00

Figure 8. Recommended Host Schematic for Independent Supply Option

Independent Power Supply Option (Seen from Bottom)

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CYBLE-014008-00

The CYBLE-014008-00 schematic is shown in Figure 9.

Figure 9. CYBLE-014008-00 Schematic Diagram

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CYBLE-014008-00

Critical Components List

Table 6 details the critical components used in the CYBLE-014008-00 module.

Table 6. Critical Component List

Component

Reference Designator

Description

Silicon

Crystal

U1

Y1

Y2

68-pin WLCSP Programmable System-on-Chip (PSoC) with BLE

24.000 MHz, 10PF

32.768 kHz, 12.5PF

Antenna Design

Table 7 details antenna used on the CYBLE-014008-00 module. The Cypress module performance improves many of these charac-

teristics. For more information, see Table 9 on page 15.

Table 7. Trace Antenna Specifications

Item

Description

Frequency Range

Peak Gain

2400 MHz–2500 MHz

0.5-dBi typical

Average Gain

Return Loss

–0.5-dBi typical

10-dB minimum

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Page 14 of 43

CYBLE-014008-00

Electrical Specification

Table 8 details the absolute maximum electrical characteristics for the Cypress BLE module.

Table 8. CYBLE-014008-00 Absolute Maximum Ratings

Parameter

V_{DDD_ABS}

Description

Min

–0.5

Typ

–

Max

6

Unit

V

Details/Conditions

V_DD, V_DDAor V_DDRsupply relative to V_SS

Absolute maximum

(V_SSD= V_SSA

)

V_{CCD_ABS}

Direct digital core voltage input relative to V_SSD

–

1.95

V

Absolute maximum

3.0-V supply

Maximum power supply ripple for V_DD, V_DDAand

_DDRinput voltage

V_{DDD_RIPPLE}

–

100

mV Ripple frequency of 100 kHz

to 750 kHz

V

V_{GPIO_ABS}

I_{GPIO_ABS}

GPIO voltage

–0.5

–25

–

VDD +0.5

25

V

Absolute maximum

Maximum current per GPIO

mA Absolute maximum

GPIO injection current: Maximum for V_IH> V_DD

and minimum for V_IL< V_SS

Absolute maximum current

injected per pin

I_{GPIO_injection}

LU

–0.5

–

0.5

mA

Pin current for latch up

–200

200

mA

–

Table 9 details the RF characteristics for the Cypress BLE module.

Table 9. CYBLE-014008-00 RF Performance Characteristics

Parameter

RF_O

Description

RF output power on ANT

Min

Typ

Max

Unit

Details/Conditions

Configurable via register

settings

–18

0

3

dBm

Guaranteed by design

simulation

RX_S

RF receive sensitivity on ANT

–

–87

–

dBm

F_R

Module frequency range

Peak gain

2400

–

2480

MHz

dBi

dB

–

G_P

–

0.5

–

G_Avg

RL

Average gain

–0.5

–10

Return loss

Table 10 through Table 51 list the module-level electrical characteristics for the CYBLE-014008-00. All specifications are valid for

–40 °C  TA  85 °C and TJ  100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.

Table 10. CYBLE-014008-00 DC Specifications

Parameter

V_DD1

Description

Min

1.71

Typ

–

Max

5.5

Unit

V

Details/Conditions

Power supply input voltage (V_{DD =}V_{DDA =}V_DDR

)

With regulator enabled

V_DD2

Power supply input voltage unregulated

1.8

1.89

V

Internally unregulated

supply

(V_DD= V_DDA= V_DDR

)

V_DDR1

V_DDR2

Radio supply voltage (radio on)

Radio supply voltage (radio off)

1.9

–

5.5

V

–

1.71

Active Mode, V_DD= 1.71 V to 5.5 V

I_DD3

Execute from flash; CPU at 3 MHz

–

1.7

–

mA T = 25 °C,

_DD= 3.3 V

V

I_DD4

I_DD5

Execute from flash; CPU at 3 MHz

Execute from flash; CPU at 6 MHz

–

mA T = –40 °C to 85 °C

2.5

mA T = 25 °C,

V_DD= 3.3 V

I_DD6

I_DD7

Execute from flash; CPU at 6 MHz

Execute from flash; CPU at 12 MHz

–

4

–

mA T = –40 °C to 85 °C

mA T = 25 °C,

V_DD= 3.3 V

Document Number: 002-00023 Rev. *K

Page 15 of 43

CYBLE-014008-00

Table 10. CYBLE-014008-00 DC Specifications (continued)

Parameter

I_DD8

Description

Min

–

Typ

–

Max

–

Unit

Details/Conditions

Execute from flash; CPU at 12 MHz

Execute from flash; CPU at 24 MHz

mA T = –40 °C to 85 °C

mA T = 25 °C,

I_DD9

–

7.1

–

V_DD= 3.3 V

I_DD10

I_DD11

Execute from flash; CPU at 24 MHz

Execute from flash; CPU at 48 MHz

–

mA T = –40 °C to 85 °C

13.4

mA T = 25 °C,

V_DD= 3.3 V

I_DD12

Execute from flash; CPU at 48 MHz

–

mA T = –40 °C to 85 °C

Sleep Mode, V_DD= 1.71 V to 5.5 V

I_DD13IMO on

mA T = 25 °C, V_DD= 3.3 V,

SYSCLK = 3 MHz

Sleep Mode, V_DDand V_DDR= 1.9 V to 5.5 V

I_DD14ECO on

–

mA T = 25 °C, V_DD= 3.3 V,

SYSCLK = 3 MHz

Deep-Sleep Mode, V_DD= 1.71 V to 3.6 V

I_DD15

WDT with WCO on

1.3

µA T = 25 °C,

V_DD= 3.3 V

I_DD16

I_DD17

WDT with WCO on

–

µA T = –40 °C to 85 °C

µA T = 25 °C,

V_DD= 5 V

I_DD18

WDT with WCO on

–

µA T = –40 °C to 85 °C

Deep-Sleep Mode, V_DD= 1.71 V to 1.89 V (Regulator Bypassed)

I_DD19

I_DD20

WDT with WCO on

–

µA T = 25 °C

µA T = –40 °C to 85 °C

Hibernate Mode, V_DD= 1.71 V to 3.6 V

I_DD27

GPIO and reset active

–

150

–

nA T = 25 °C,

V_DD= 3.3 V

I_DD28

GPIO and reset active

nA T = –40 °C to 85 °C

Hibernate Mode, V_DD= 3.6 V to 5.5 V

I_DD29

GPIO and reset active

–

nA T = 25 °C,

V_DD= 5 V

I_DD30

GPIO and reset active

nA T = –40 °C to 85 °C

Stop Mode, V_DD= 1.71 V to 3.6 V

I_DD33Stop-mode current (V_DD

)

–

20

40

–

nA T = 25 °C,

V_DD= 3.3 V

I_DD34

Stop-mode current (V_DDR

)

–-

nA T = 25 °C,

V_DDR= 3.3 V

I_DD35

I_DD36

Stop-mode current (V_DD

)

–

nA T = –40 °C to 85 °C

Stop-mode current (V_DDR

nA T = –40 °C to 85 °C,

V_DDR= 1.9 V to 3.6 V

Stop Mode, V_DD= 3.6 V to 5.5 V

I_DD37Stop-mode current (V_DD

)

–

nA T = 25 °C,

V

_DD= 5 V

nA T = 25 °C,

_DDR= 5 V

I_DD38

Stop-mode current (V_DDR

)

V

I_DD39

I_DD40

Stop-mode current (V_DD

)

–

nA T = –40 °C to 85 °C

Stop-mode current (V_DDR

Document Number: 002-00023 Rev. *K

Page 16 of 43

CYBLE-014008-00

Table 11. AC Specifications

Parameter

Description

Min

DC

–

Typ

–

Max

48

–

Unit

Details/Conditions

F_CPU

CPU frequency

MHz 1.71 V V_DD5.5 V

T_SLEEP

Wakeup from Sleep mode

0

µs

Guaranteed by characterization

24-MHz IMO. Guaranteed by

characterization

T_DEEPSLEEP

Wakeup from Deep-Sleep mode

–

25

µs

T_HIBERNATE

T_STOP

Wakeup from Hibernate mode

Wakeup from Stop mode

–

800

2

µs

Guaranteed by characterization

XRES wakeup

ms

GPIO

Table 12. GPIO DC Specifications

Parameter

Description

Min

Typ

–

Max

Unit

V

Details/Conditions

Input voltage HIGH threshold

LVTTL input, V_DD< 2.7 V

LVTTL input, V_DD 2.7 V

Input voltage LOW threshold

LVTTL input, V_DD< 2.7 V

LVTTL input, V_DD 2.7 V

Output voltage HIGH level

Output voltage LOW level

Pull-up resistor

0.7 × V_DD

–

CMOS input

[5]

V_IH

0.7 × V_DD

–

V

–

2.0

–

V

–

0.3 × V_DD

V

CMOS input

V_IL

–

0.3 × V_DD

V

–

0.8

–

V

–

V_DD– 0.6

–

V

I_OH= 4 mA at 3.3-V V_DD

V_OH

V_DD– 0.5

–

V

I_OH= 1 mA at 1.8-V V_DD

–

0.6

0.4

8.5

2

V

I_OL= 8 mA at 3.3-V V_DD

V_OL

–

V

I_OL= 4 mA at 1.8-V V_DD

–

V

I_OL= 3 mA at 3.3-V V_DD

R_PULLUP

R_PULLDOWN

I_IL

3.5

5.6

–

k

nA

pF

mV

1

–

Pull-down resistor

3.5

–

Input leakage current (absolute value)

Input leakage on CTBm input pins

Input capacitance

–

25 °C, V_DD= 3.3 V

I_{IL_CTBM}

C_IN

V_HYSTTL

V_HYSCMOS

–

4

–

25

–

7

–

Input hysteresis LVTTL

40

–

V_DD> 2.7 V

–

Input hysteresis CMOS

0.05 × V_DD

–

Current through protection diode to

I_DIODE

–

100

200

µA

–

V_DD/V_SS

Maximum total source or sink chip

current

I_{TOT_GPIO}

mA

Note

5.

V

must not exceed V + 0.2 V.

IH DD

Document Number: 002-00023 Rev. *K

Page 17 of 43

CYBLE-014008-00

Table 13. GPIO AC Specifications

Parameter Description

T_RISEF

Min

2

Typ

–

Max

12

Unit

ns

Details/Conditions

3.3-V V_DDD, C_LOAD= 25 pF

Rise time in Fast-Strong mode

Fall time in Fast-Strong mode

Rise time in Slow-Strong mode

Fall time in Slow-Strong mode

T_FALLF

T_RISES

T_FALLS

2

–

12

ns

10

–

60

ns

–

60

ns

GPIO Fout; 3.3 V  V_DD5.5 V

90/10%, 25-pF load, 60/40 duty

cycle

F_GPIOUT1

F_GPIOUT2

F_GPIOUT3

F_GPIOUT4

F_GPIOIN

–

33

16.7

7

MHz

Fast-Strong mode

GPIO Fout; 1.7 V V_DD3.3 V

Fast-Strong mode

90/10%, 25-pF load, 60/40 duty

cycle

GPIO Fout; 3.3 V V_DD5.5 V

Slow-Strong mode

90/10%, 25-pF load, 60/40 duty

cycle

GPIO Fout; 1.7 V V_DD3.3 V

Slow-Strong mode

90/10%, 25-pF load, 60/40 duty

cycle

3.5

48

GPIO input operating frequency

1.71 V V_DD5.5 V

MHz 90/10% V_IO

XRES

Table 14. XRES DC Specifications

Parameter Description

V_IH

Min

Typ

–

Max

Unit

V

Details/Conditions

Input voltage HIGH threshold

Input voltage LOW threshold

Pull-up resistor

0.7 × V_DDD

–

CMOS input

V_IL

–

3.5

–

0.3 × V_DDD

V

R_PULLUP

C_IN

5.6

3

8.5

–

k

pF

mV

–

Input capacitance

V_HYSXRES

Input voltage hysteresis

Current through protection diode to

–

100

–

I_DIODE

–

100

µA

–

V_DD/V_SS

Table 15. XRES AC Specifications

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

T_RESETWIDTHReset pulse width

1

–

µs

–

Document Number: 002-00023 Rev. *K

Page 18 of 43

CYBLE-014008-00

Analog Peripherals

Opamp

Table 16. Opamp Specifications

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

I_DD(Opamp Block Current. V_DD= 1.8 V. No Load)

I_{DD_HI}

Power = high

Power = medium

Power = low

–

1000

500

1300

–

µA

–

I_{DD_MED}

I_{DD_LOW}

250

350

GBW (Load = 20 pF, 0.1 mA. V_DDA= 2.7 V)

GBW_HI

Power = high

Power = medium

Power = low

6

4

–

1

–

MHz

–

GBW_MED

GBW_LO

I_{OUT_MAX}(V_DDA 2.7 V, 500 mV from Rail)

I_{OUT_MAX_HI}

I_{OUT_MAX_MID}

I_{OUT_MAX_LO}

Power = high

Power = medium

Power = low

10

–

5

–

mA

–

I_OUT(V_DDA= 1.71 V, 500 mV from Rail)

I_{OUT_MAX_HI}

I_{OUT_MAX_MID}

I_{OUT_MAX_LO}

V_IN

Power = high

4

–

2

–

mA

V

–

Power = medium

–

Power = low

–

Charge pump on, V_DDA 2.7 V

–0.05

V_DDA– 0.2

V_CM

V

V_OUT(V_DDA 2.7 V)

V_{OUT_1}

V_{OUT_2}

V_{OUT_3}

V_{OUT_4}

V_{OS_TR}

V_{OS_DR_TR}

Power = high, I_LOAD= 10 mA

Power = high, I_LOAD= 1 mA

Power = medium, I_LOAD= 1 mA

Power = low, I_LOAD=0.1 mA

Offset voltage, trimmed

0.5

0.2

1

–

V_DDA– 0.5

V

–

V_DDA– 0.2

–

V_DDA– 0.2

V

–

V_DDA– 0.2

V

–

±0.5

±1

±2

±3

±10

1

–

mV

µV/C

High mode

Medium mode

Low mode

High mode

Medium mode

Low mode

Offset voltage, trimmed

–

Offset voltage, trimmed

–

Offset voltage drift, trimmed

–10

–

10

–

V

_DDD= 3.6 V,

CMRR

DC

65

70

85

–

dB

High-power mode

PSRR

Noise

V_N1

At 1 kHz, 100-mV ripple

V_DDD= 3.6 V

Input referred, 1 Hz–1 GHz, power = high

Input referred, 1 kHz, power = high

Input referred, 10 kHz, power = high

Input referred, 100 kHz, power = high

–

94

72

28

15

–

µVrms

nV/rtHz

–

V_N2

V_N3

V_N4

Stable up to maximum load. Performance specs

at 50 pF.

C_LOAD

–

6

–

125

–

pF

Cload = 50 pF, Power = High,

V_DDA 2.7 V

–

Slew_rate

V/µs

Document Number: 002-00023 Rev. *K

Page 19 of 43

CYBLE-014008-00

Table 16. Opamp Specifications (continued)

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

From disable to enable, no external RC

dominating

–

T_op_wake

–

300

–

µs

Comp_mode (Comparator Mode; 50-mV Drive, T_RISE= T_FALL(Approx.)

T_PD1

Response time; power = high

Response time; power = medium

Response time; power = low

Hysteresis

–

150

400

2000

10

–

ns

–

T_PD2

T_PD3

ns

Vhyst_op

mV

Deep-Sleep Mode (Deep-Sleep mode operation is only guaranteed for V_DDA> 2.5 V)

GBW_DS

IDD_DS

Gain bandwidth product

Current

–

50

15

5

–

kHz

µA

–

Vos_DS

Offset voltage

–

mV

µV/°C

V

Vos_dr_DS

Vout_DS

Vcm_DS

Offset voltage drift

Output voltage

–

20

–

0.2

V

_DD–0.2

Common mode voltage

–

V_DD–1.8

V

Table 17. Comparator DC Specifications

Parameter Description

V_OFFSET1

Min

–

Typ

Max

Unit

mV

V

Details/Conditions

Input offset voltage, Factory trim

–

±10

–

V_OFFSET2

V_OFFSET3

V_HYST

Input offset voltage, Custom trim

–

±6

–

Input offset voltage, ultra-low-power mode

Hysteresis when enabled

–

±12

10

–

35

–

Modes 1 and 2

–

V_ICM1

Input common mode voltage in normal mode

Input common mode voltage in low-power mode

0

V_DDD– 0.1

V_DDD

V_ICM2

0

–

V

Input common mode voltage in ultra low-power

mode

V_ICM3

0

–

V_DDD– 1.15

V

–

CMRR

I_CMP1

I_CMP2

I_CMP3

Z_CMP

Common mode rejection ratio

Block current, normal mode

50

42

–

6

–

dB

µA

M

V_DDD 2.7 V

V_DDD 2.7 V

400

100

–

Block current, low-power mode

Block current in ultra-low-power mode

DC input impedance of comparator

–

35

–

Table 18. Comparator AC Specifications

Parameter Description

T_RESP1

T_RESP2

Min

Typ

Max

Unit

Details/Conditions

Response time, normal mode, 50-mV overdrive

–

38

–

ns

50-mV overdrive

Response time, low-power mode, 50-mV

overdrive

–

70

–

ns

µs

50-mV overdrive

200-mV overdrive

Response time, ultra-low-power mode, 50-mV

overdrive

T_RESP3

2.3

Temperature Sensor

Table 19. Temperature Sensor Specifications

Parameter

T_SENSACC

Description

Min

Typ

Max

Unit

Details/Conditions

Temperature-sensor accuracy

–5

±1

5

°C

–40 to +85 °C

Document Number: 002-00023 Rev. *K

Page 20 of 43

CYBLE-014008-00

SAR ADC

Table 20. SAR ADC DC Specifications

Parameter

A_RES

Description

Min

–

Typ

–

Max

12

8

Unit

Details/Conditions

Resolution

bits

–

A_CHNIS_S

A-CHNKS_D

A-MONO

Number of channels - single-ended

–

8 full-speed

Diff inputs use

neighboring I/O

Number of channels - differential

Monotonicity

–

4

–

Yes

With external

reference

A_GAINERR

Gain error

±0.1

%

Measured with 1-V

V_REF

A_OFFSET

Input offset voltage

–

2

mV

A_ISAR

A_VINS

A_VIND

A_INRES

A_INCAP

Current consumption

–

V_SS

–

1

mA

V

–

Input voltage range - single-ended

Input voltage range - differential

Input resistance

V_DDA

2.2

V

k

pF

Input capacitance

–

10

Percentage of Vbg

(1.024 V)

VREFSAR

Trimmed internal reference to SAR

–1

–

1

%

Table 21. SAR ADC AC Specifications

Parameter Description

A_PSRR

Min

Typ

Max

Unit

Details/Conditions

Measured at 1-V

reference

Power-supply rejection ratio

70

–

dB

A_CMRR

A_SAMP

Common-mode rejection ratio

Sample rate

66

–

1

dB

–

Msps

SAR operating speed without external ref.

bypass

Fsarintref

–

100

ksps 12-bit resolution

A_SNR

A_BW

Signal-to-noise ratio (SNR)

65

–

dB

F_IN= 10 kHz

–

Input bandwidth without aliasing

A_SAMP/2

kHz

Integral nonlinearity. V_DD= 1.71 V to 5.5 V,

1 Msps.

A_INL

A_dnl

–1.7

–1.5

–1

–

2

LSB

V

_REF= 1 V to V_DD

_REF= 1.71 V to V_DD

_REF= 1 V to V_DD

_REF= 1.71 V to V_DD

_REF= 1 V to V_DD

Integral nonlinearity. V_DDD= 1.71 V to 3.6 V,

1 Msps.

1.7

2.2

2

Integral nonlinearity. V_DD= 1.71 V to 5.5 V,

500 Ksps.

Differential nonlinearity. V_DD= 1.71 V to

5.5 V, 1 Msps.

Differential nonlinearity. V_DD= 1.71 V to

3.6 V, 1 Msps.

A_DNL

–1

Differential nonlinearity. V_DD= 1.71 V to

5.5 V, 500 Ksps.

A_DNL

A_THD

–1

–

2.2

LSB

dB

Total harmonic distortion

–65

F_IN= 10 kHz

Document Number: 002-00023 Rev. *K

Page 21 of 43

CYBLE-014008-00

CSD

Table 22. CSD Block Specifications

Parameter

V_CSD

Description

Min

1.71

–1

Typ

–

Max

5.5

1

Unit

V

Details/Conditions

Voltage range of operation

DNL for 8-bit resolution

INL for 8-bit resolution

–

IDAC1

IDAC2

SNR

–

LSB

–3

–

3

DNL for 7-bit resolution

INL for 7-bit resolution

–1

–

1

–3

–

3

Ratio of counts of finger to noise

5

–

Ratio Capacitancerangeof9 pF

to35 pF,0.1-pFsensitivity.

Radio is not operating

during the scan.

I_{DAC1_CRT1}

I_{DAC1_CRT2}

I_{DAC2_CRT1}

I_{DAC2_CRT2}

Output current of IDAC1 (8 bits) in High range

Output current of IDAC1 (8 bits) in Low range

Output current of IDAC2 (7 bits) in High range

Output current of IDAC2 (7 bits) in Low range

–

612

306

305

153

–

µA

–

Digital Peripherals

Timer

Table 23. Timer DC Specifications

Parameter

I_TIM1

I_TIM2

I_TIM3

Description

Min

–

Typ

–

Max

42

Unit

µA

Details/Conditions

Block current consumption at 3 MHz

Block current consumption at 12 MHz

Block current consumption at 48 MHz

16-bit timer

–

130

535

µA

16-bit timer

–

µA

Table 24. Timer AC Specifications

Parameter Description

T_TIMFREQ

Min

Typ

–

Max

48

–

Unit

MHz

ns

Details/Conditions

Operating frequency

F_CLK

–

T_CAPWINT

Capture pulse width (internal)

Capture pulse width (external)

Timer resolution

2 × T_CLK

T_CLK

–

T_CAPWEXT

T_TIMRES

–

ns

–

ns

T_TENWIDINT

T_TENWIDEXT

T_TIMRESWINT

T_TIMRESEXT

Enable pulse width (internal)

Enable pulse width (external)

Reset pulse width (internal)

Reset pulse width (external)

2 × T_CLK

–

ns

–

ns

–

ns

–

ns

Document Number: 002-00023 Rev. *K

Page 22 of 43

CYBLE-014008-00

Counter

Table 25. Counter DC Specifications

Parameter

I_CTR1

I_CTR2

I_CTR3

Description

Min

–

Typ

–

Max

42

Unit

µA

Details/Conditions

16-bit counter

Block current consumption at 3 MHz

Block current consumption at 12 MHz

Block current consumption at 48 MHz

–

130

535

µA

16-bit counter

µA

Table 26. Counter AC Specifications

Parameter

T_CTRFREQ

Description

Min

Typ

–

Max

48

–

Unit

MHz

ns

Details/Conditions

Operating frequency

F_CLK

–

T_CTRPWINT

T_CTRPWEXT

T_CTRES

Capture pulse width (internal)

Capture pulse width (external)

Counter Resolution

2 × T_CLK

T_CLK

–

ns

–

ns

T_CENWIDINT

T_CENWIDEXT

T_CTRRESWINT

Enable pulse width (internal)

Enable pulse width (external)

Reset pulse width (internal)

2 × T_CLK

–

ns

–

ns

–

ns

T_CTRRESWEXTReset pulse width (external)

–

ns

Pulse Width Modulation (PWM)

Table 27. PWM DC Specifications

Parameter

I_PWM1

I_PWM2

I_PWM3

Description

Min

–

Typ

–

Max

42

Unit

µA

Details/Conditions

16-bit PWM

Block current consumption at 3 MHz

Block current consumption at 12 MHz

Block current consumption at 48 MHz

–

130

535

µA

16-bit PWM

–

µA

16-bit PWM

Table 28. PWM AC Specifications

Parameter Description

T_PWMFREQ

T_PWMPWINT

T_PWMEXT

Min

Typ

–

Max

48

–

Unit

MHz

ns

Details/Conditions

Operating frequency

F_CLK

–

Pulse width (internal)

2 × T_CLK

–

Pulse width (external)

–

ns

T_PWMKILLINT

T_PWMKILLEXT

T_PWMEINT

Kill pulse width (internal)

Kill pulse width (external)

Enable pulse width (internal)

Enable pulse width (external)

Reset pulse width (internal)

Reset pulse width (external)

–

ns

–

ns

–

ns

T_PWMENEXT

T_PWMRESWINT

T_PWMRESWEXT

–

ns

–

ns

–

ns

Document Number: 002-00023 Rev. *K

Page 23 of 43

CYBLE-014008-00

LCD Direct Drive

Table 29. LCD Direct Drive DC Specifications

Spec ID

SID228

Parameter

Description

Min

Typ

Max Unit

Details/Conditions

16 × 4 small segment

display at 50 Hz

I_LCDLOW

Operating current in low-power mode

–

17.5

–

µA

SID229

SID230

C_LCDCAP

LCD capacitance per segment/common driver

Long-term segment offset

–

500 5000

pF

–

LCD_OFFSET

20

–

mV

LCD system operating current

32 × 4 segments.

50 Hz at 25 °C

SID231

SID232

I_LCDOP1

I_LCDOP2

–

2

–

mA

V

_BIAS= 5 V

LCD system operating current

_BIAS= 3.3 V

32 × 4 segments

50 Hz at 25 °C

2

–

V

Table 30. LCD Direct Drive AC Specifications

Spec ID Parameter Description

SID233 F_LCD

Min

Typ

Max

Unit

Details/Conditions

LCD frame rate

10

50

150

Hz

–

Serial Communication

Table 31. Fixed I²C DC Specifications

Parameter

I_I2C1

Description

Min

–

Typ

–

Max

50

Unit

Details/Conditions

Block current consumption at 100 kHz

Block current consumption at 400 kHz

Block current consumption at 1 Mbps

I²C enabled in Deep-Sleep mode

µA

–

I_I2C2

–

155

390

1.4

I_I2C3

–

I_I2C4

–

Table 32. Fixed I²C AC Specifications

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

F_I2C1

Bit rate

–

400

kHz

–

Table 33. Fixed UART DC Specifications

Parameter

I_UART1

Description

Min

–

Typ

–

Max

55

Unit

µA

Details/Conditions

Block current consumption at 100 kbps

Block current consumption at 1000 kbps

–

I_UART2

–

312

µA

Table 34. Fixed UART AC Specifications

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

F_UART

Bit rate

–

1

Mbps

–

Table 35. Fixed SPI DC Specifications

Parameter

I_SPI1

I_SPI2

I_SPI3

Description

Min

–

Typ

–

Max

360

560

600

Unit

µA

Details/Conditions

Block current consumption at 1 Mbps

Block current consumption at 4 Mbps

Block current consumption at 8 Mbps

–

µA

–

µA

Document Number: 002-00023 Rev. *K

Page 24 of 43

CYBLE-014008-00

Table 36. Fixed SPI AC Specifications

Parameter

Description

SPI operating frequency (master; 6x over sampling)

Min

Typ

Max

Unit

Details/Conditions

F_SPI

–

8

MHz

–

Table 37. Fixed SPI Master Mode AC Specifications

Parameter

T_DMO

Description

Min

Typ Max Unit

Details/Conditions

MOSI valid after SCLK driving edge

–

18

ns

–

MISO valid before SCLK capturing edge

Full clock, late MISO sampling used

T_DSI

20

0

–

Full clock, late MISO sampling

Referred to Slave capturing edge

T_HMO

Previous MOSI data hold time

–

Table 38. Fixed SPI Slave Mode AC Specifications

Parameter Description

T_DMI

Min

40

–

Typ

–

Max

–

Unit

ns

MOSI valid before SCLK capturing edge

MISO valid after SCLK driving edge

T_DSO

–

42 + 3 × T_CPU

ns

MISO Valid after SCLK driving edge in external clock mode.

_DD< 3.0 V

T_{DSO_ext}

–

50

ns

V

T_HSO

Previous MISO data hold time

0

–

ns

T_SSELSCK

SSEL valid to first SCK valid edge

100

Memory

Table 39. Flash DC Specifications

Parameter Description

V_PE

Min

1.71

2

Typ

–

Max

5.5

–

Unit

V

Details/Conditions

Erase and program voltage

–

T_WS48

T_WS32

T_WS16

Number of Wait states at 32–48 MHz

Number of Wait states at 16–32 MHz

Number of Wait states for 0–16 MHz

–

CPU execution from flash

1

–

0

–

Table 40. Flash AC Specifications

Parameter

Description

Min

–

Typ

–

Max

20

13

7

Unit

ms

Details/Conditions

[6]

T_ROWWRITE

Row (block) write time (erase and program)

Row erase time

Row (block) = 128 bytes

[6]

T_ROWERASE

–

[6]

T_ROWPROGRAM

Row program time after erase

Bulk erase time (128 KB)

–

[6]

T_BULKERASE

–

35

second

s

[6]

T_DEVPROG

Total device program time

–

25

–

F_END

F_RET

F_RET2

Flash endurance

100 K

20

–

cycles

years

–

Flash retention. T_A 55 °C, 100 K P/E cycles.

Flash retention. T_A 85 °C, 10 K P/E cycles.

10

Note

6. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have

completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make

certain that these are not inadvertently activated.

Document Number: 002-00023 Rev. *K

Page 25 of 43

CYBLE-014008-00

System Resources

Power-on-Reset (POR)

Table 41. POR DC Specifications

Parameter

Description

Min

0.80

0.75

15

Typ

–

Max

1.45

1.40

200

Unit

V

Details/Conditions

V_RISEIPOR

V_FALLIPOR

V_IPORHYST

Rising trip voltage

–

Falling trip voltage

Hysteresis

–

V

–

mV

Table 42. POR AC Specifications

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

Precision power-on reset (PPOR) response

time in Active and Sleep modes

T_{PPOR_TR}

–

1

µs

–

Table 43. Brown-Out Detect

Parameter

Description

Min

1.64

1.4

Typ

–

Max

–

Unit

V

Details/Conditions

V_FALLPPOR

V_FALLDPSLP

BOD trip voltage in Active and Sleep modes

BOD trip voltage in Deep Sleep

–

V

Table 44. Hibernate Reset

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

V_HBRTRIP

BOD trip voltage in Hibernate

1.1

–

V

–

Voltage Monitors (LVD)

Table 45. Voltage Monitor DC Specifications

Parameter

V_LVI1

Description

LVI_A/D_SEL[3:0] = 0000b

LVI_A/D_SEL[3:0] = 0001b

LVI_A/D_SEL[3:0] = 0010b

LVI_A/D_SEL[3:0] = 0011b

LVI_A/D_SEL[3:0] = 0100b

LVI_A/D_SEL[3:0] = 0101b

LVI_A/D_SEL[3:0] = 0110b

LVI_A/D_SEL[3:0] = 0111b

LVI_A/D_SEL[3:0] = 1000b

LVI_A/D_SEL[3:0] = 1001b

LVI_A/D_SEL[3:0] = 1010b

LVI_A/D_SEL[3:0] = 1011b

LVI_A/D_SEL[3:0] = 1100b

LVI_A/D_SEL[3:0] = 1101b

LVI_A/D_SEL[3:0] = 1110b

LVI_A/D_SEL[3:0] = 1111b

Block current

Min

1.71

1.76

1.85

1.95

2.05

2.15

2.24

2.34

2.44

2.54

2.63

2.73

2.83

2.93

3.12

4.39

–

Typ

1.75

1.80

1.90

2.00

2.10

2.20

2.30

2.40

2.50

2.60

2.70

2.80

2.90

3.00

3.20

4.50

–

Max

1.79

1.85

1.95

2.05

2.15

2.26

2.36

2.46

2.56

2.67

2.77

2.87

2.97

3.08

3.28

4.61

100

Unit

V

Details/Conditions

–

V_LVI2

V

V_LVI3

V

V_LVI4

V

V_LVI5

V

V_LVI6

V

V_LVI7

V

V_LVI8

V

V_LVI9

V

V_LVI10

V_LVI11

V_LVI12

V_LVI13

V_LVI14

V_LVI15

V_LVI16

LVI_IDD

V

µA

Document Number: 002-00023 Rev. *K

Page 26 of 43

CYBLE-014008-00

Table 46. Voltage Monitor AC Specifications

Parameter

T_MONTRIP

Description

Min

Typ

Max

Unit

Details/Conditions

Voltage monitor trip time

–

1

µs

–

SWD Interface

Table 47. SWD Interface Specifications

Parameter

F_SWDCLK1

F_SWDCLK2

Description

3.3 V  V_DD 5.5 V

1.71 V  V_DD 3.3 V

Min

Typ

Max

Unit

Details/Conditions

–

14

MHz SWDCLK 1/3 CPU clock frequency

–

7

T_SWDI_SETUP T = 1/f SWDCLK

T_SWDI_HOLD T = 1/f SWDCLK

0.25 × T

–

ns

–

0.25 × T

–

0.5 × T

–

T_SWDO_VALID T = 1/f SWDCLK

T_SWDO_HOLD T = 1/f SWDCLK

–

1

Internal Main Oscillator

Table 48. IMO DC Specifications

Parameter

I_IMO1

Description

Min

–

Typ

–

Max

1000

325

225

180

150

Unit

µA

Details/Conditions

IMO operating current at 48 MHz

IMO operating current at 24 MHz

IMO operating current at 12 MHz

IMO operating current at 6 MHz

IMO operating current at 3 MHz

–

I_IMO2

I_IMO3

I_IMO4

I_IMO5

–

Table 49. IMO AC Specifications

Parameter

F_IMOTOL3

Description

Min

–

Typ

–

Max

±2

–

Unit

%

Details/Conditions

Frequency variation from 3 to

48 MHz

With API-called calibration

–

F_IMOTOL3

IMO startup time

–

12

µs

Internal Low-Speed Oscillator

Table 50. ILO DC Specifications

Parameter

I_ILO2

Description

ILO operating current at 32 kHz

Min

Typ

Max

Unit

Details/Conditions

–

0.3

1.05

µA

–

Table 51. ILO AC Specifications

Parameter

T_STARTILO1

F_ILOTRIM1

Description

Min

–

Typ

–

Max

2

Unit

ms

Details/Conditions

ILO startup time

–

32-kHz trimmed frequency

15

32

50

kHz

Table 52. Recommended ECO Trim Value

Parameter

Description

24-MHz trim value

(firmware configuration)

Value

0x00009595

Details/Conditions

Recommended trim value that needs to be loaded to register

CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG

ECO_TRIM

Document Number: 002-00023 Rev. *K

Page 27 of 43

CYBLE-014008-00

Table 53. UDB AC Specifications

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

Data Path performance

Max frequency of 16-bit timer in a UDB

pair

F_MAX-TIMER

F_MAX-ADDER

F_{MAX_CRC}

–

48

MHz

–

Max frequency of 16-bit adder in a UDB

pair

Max frequency of 16-bit CRC/PRS in a

UDB pair

PLD Performance in UDB

Max frequency of 2-pass PLD function

F_{MAX_PLD}

–

48

MHz

–

in a UDB pair

Clock to Output Performance

Prop. delay for clock in to data out at

T_{CLK_OUT_UDB1}

–

15

25

–

ns

–

25 °C, Typical

Prop. delay for clock in to data out,

Worst case

T_{CLK_OUT_UDB2}

Table 54. BLE Subsystem

Parameter

Description

Min

Typ

Max

Unit

Details/Conditions

RF Receiver Specification

RXS, IDLE

RX sensitivity with idle transmitter

–

–89

–91

–

dBm

–

RX sensitivity with idle transmitter

excluding Balun loss

Guaranteed by design

simulation

RF-PHY Specification

(RCV-LE/CA/01/C)

RXS, DIRTY

RXS, HIGHGAIN

PRXMAX

RX sensitivity with dirty transmitter

–

–87

–91

–1

–70

–

dBm

RX sensitivity in high-gain mode with idle

transmitter

–

RF-PHY Specification

(RCV-LE/CA/06/C)

Maximum input power

–10

–

Cochannel interference,

Wanted signal at –67 dBm and Interferer

at FRX

RF-PHY Specification

(RCV-LE/CA/03/C)

CI1

CI2

CI3

CI4

CI5

CI3

–

9

21

15

–

dB

Adjacent channel interference

Wanted signal at –67 dBm and Interferer

at FRX ±1 MHz

RF-PHY Specification

(RCV-LE/CA/03/C)

3

Adjacent channel interference

Wanted signal at –67 dBm and Interferer

at FRX ±2 MHz

RF-PHY Specification

(RCV-LE/CA/03/C)

–29

–39

–20

–30

Adjacent channel interference

Wanted signal at –67 dBm and Interferer

at FRX ±3 MHz

RF-PHY Specification

(RCV-LE/CA/03/C)

–

Adjacent channel interference

Wanted Signal at –67 dBm and Interferer

RF-PHY Specification

(RCV-LE/CA/03/C)

–

at Image frequency (F_IMAGE

)

Adjacent channel interference

Wanted signal at –67 dBm and Interferer

at Image frequency (F_IMAGE± 1 MHz)

RF-PHY Specification

(RCV-LE/CA/03/C)

–

Document Number: 002-00023 Rev. *K

Page 28 of 43

CYBLE-014008-00

Table 54. BLE Subsystem (continued)

Parameter Description

Min

Typ

Max

Unit

Details/Conditions

Out-of-band blocking,

Wanted signal at –67 dBm and Interferer

at F = 30–2000 MHz

RF-PHY Specification

(RCV-LE/CA/04/C)

OBB1

–30

–27

–

dBm

Out-of-band blocking,

Wanted signal at –67 dBm and Interferer

at F = 2003–2399 MHz

RF-PHY Specification

(RCV-LE/CA/04/C)

OBB2

OBB3

OBB4

IMD

–35

–30

–50

–

–27

–

dBm

Out-of-band blocking,

Wanted signal at –67 dBm and Interferer

at F = 2484–2997 MHz

RF-PHY Specification

(RCV-LE/CA/04/C)

Out-of-band blocking,

Wanted signal a –67 dBm and Interferer

at F = 3000–12750 MHz

RF-PHY Specification

(RCV-LE/CA/04/C)

–

Intermodulation performance

Wanted signal at –64 dBm and 1-Mbps

BLE, third, fourth, and fifth offset channel

RF-PHY Specification

(RCV-LE/CA/05/C)

–

100-kHz measurement

bandwidth

ETSI EN300 328 V1.8.1

Receiver spurious emission

30 MHz to 1.0 GHz

RXSE1

RXSE2

–

–57

–47

1-MHz measurement

bandwidth

ETSI EN300 328 V1.8.1

Receiver spurious emission

1.0 GHz to 12.75 GHz

–

RF Transmitter Specifications

TXP, ACC

RF power accuracy

–

±1

20

0

–

dB

–

TXP, RANGE

TXP, 0dBm

RF power control range

Output power, 0-dB Gain setting (PA7)

dBm

Output power, maximum power setting

(PA10)

TXP, MAX

TXP, MIN

F2AVG

–

3

–18

–

dBm

kHz

–

Output power, minimum power setting

(PA1)

Average frequency deviation for

10101010 pattern

RF-PHY Specification

(TRM-LE/CA/05/C)

185

225

0.8

–150

–50

–20

–

Average frequency deviation for

11110000 pattern

RF-PHY Specification

(TRM-LE/CA/05/C)

F1AVG

250

–

275

–

RF-PHY Specification

(TRM-LE/CA/05/C)

EO

Eye opening = F2AVG/F1AVG

Frequency accuracy

RF-PHY Specification

(TRM-LE/CA/06/C)

FTX, ACC

FTX, MAXDR

FTX, INITDR

FTX, DR

IBSE1

–

150

50

kHz

RF-PHY Specification

(TRM-LE/CA/06/C)

Maximum frequency drift

Initial frequency drift

–

RF-PHY Specification

(TRM-LE/CA/06/C)

–

20

RF-PHY Specification

(TRM-LE/CA/06/C)

Maximum drift rate

–

20

kHz/50 µs

dBm

In-band spurious emission at 2-MHz

offset

RF-PHY Specification

(TRM-LE/CA/03/C)

–

–20

-30

-55.5

In-band spurious emission at 3-MHz

offset

RF-PHY Specification

(TRM-LE/CA/03/C)

IBSE2

–

dBm

Transmitter spurious emissions

(average), <1.0 GHz

TXSE1

–

dBm

FCC-15.247

Document Number: 002-00023 Rev. *K

Page 29 of 43

CYBLE-014008-00

Table 54. BLE Subsystem (continued)

Parameter Description

TXSE2

Min

Typ

Max

Unit

Details/Conditions

Transmitter spurious emissions

(average), >1.0 GHz

–

-41.5

dBm

FCC-15.247

RF Current Specifications

IRX

Receive current in normal mode

–

18.7

16.4

21.5

20

–

mA

–

IRX_RF

Radio receive current in normal mode

Receive current in high-gain mode

TX current at 3-dBm setting (PA10)

TX current at 0-dBm setting (PA7)

Radio TX current at 0 dBm setting (PA7)

Measured at V_DDR

IRX, HIGHGAIN

ITX, 3dBm

ITX, 0dBm

ITX_RF, 0dBm

–

16.5

15.6

–

Measured at V_DDR

Radio TX current at 0 dBm excluding

Balun loss

Guaranteed by design

simulation

ITX_RF, 0dBm

–

14.2

–

mA

ITX,-3dBm

ITX,-6dBm

ITX,-12dBm

ITX,-18dBm

TX current at –3-dBm setting (PA4)

TX current at –6-dBm setting (PA3)

TX current at –12-dBm setting (PA2)

TX current at –18-dBm setting (PA1)

–

15.5

14.5

13.2

12.5

–

mA

–

TXP: 0 dBm; ±20-ppm

master and slave clock

accuracy.

Average current at 1-second BLE

connection interval

Iavg_1sec, 0dBm

Iavg_4sec, 0dBm

–

17.1

6.1

–

µA

For empty PDU exchange

TXP: 0 dBm; ±20-ppm

master and slave clock

accuracy.

Average current at 4-second BLE

connection interval

For empty PDU exchange

General RF Specifications

FREQ

RF operating frequency

2400

–

2

2482

–

MHz

kbps

µs

–

CHBW

Channel spacing

–

DR

On-air data rate

1000

120

75

–

IDLE2TX

IDLE2RX

RSSI Specifications

RSSI, ACC

RSSI, RES

RSSI, PER

BLE.IDLE to BLE. TX transition time

BLE.IDLE to BLE. RX transition time

140

120

µs

RSSI accuracy

–

±5

1

–

dB

µs

–

RSSI resolution

RSSI sample period

6

Document Number: 002-00023 Rev. *K

Page 30 of 43

CYBLE-014008-00

Environmental Specifications

Environmental Compliance

This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF)

directives. The Cypress module and components used to produce this module are RoHS and HF compliant.

RF Certification

The CYBLE-014008-00 module is certified under the following RF certification standards:

■ FCC ID: WAP4008

■ CE

■ IC: 7922A-4008

■ MIC: 203-JN0505

■ KC: MSIP-CRM-Cyp-4008

Environmental Conditions

Table 55 describes the operating and storage conditions for the Cypress BLE module.

Table 55. Environmental Conditions for CYBLE-014008-00

Description

Operating temperature

Minimum Specification

Maximum Specification

85 °C

–40 °C

Operating humidity (relative, non-condensation)

Thermal ramp rate

5%

85%

–

–40 °C

–

3 °C/minute

85 °C

Storage temperature

Storage temperature and humidity

85 °C at 85%

ESD: Module integrated into system

Components^[7]

15-kV Air

2.2-kV Contact

–

ESD and EMI Protection

Exposed components require special attention to ESD and electromagnetic interference (EMI).

A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure

near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground.

Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.

Note

7. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.

Document Number: 002-00023 Rev. *K

Page 31 of 43

CYBLE-014008-00

Regulatory Information

FCC

FCC NOTICE:

The device CYBLE-014008-00 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter

approval as detailed in FCC public Notice DA00-1407. Transmitter Operation is subject to the following two conditions: (1) This device

may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause

undesired operation.

CAUTION:

The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by

Cypress Semiconductor may void the user's authority to operate the equipment.

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.

These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment

generates and can radiate radio frequency energy and, if not installed and used in accordance with the instructions,ê may cause

harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.

If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment

off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

■ Reorient or relocate the receiving antenna.

■ Increase the separation between the equipment and receiver.

■ Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

■ Consult the dealer or an experienced radio/TV technician for help

LABELING REQUIREMENTS:

The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible

label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well

as the FCC Notice above. The FCC identifier is FCC ID: WAP4008.

In any case the end product must be labeled exterior with "Contains FCC ID: WAP4008"

ANTENNA WARNING:

This device is tested with a standard SMA connector and with the antennas listed in Table 7 on page 14. When integrated in the OEMs

product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna

not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for

emissions.

RF EXPOSURE:

To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved

antenna in the previous.

The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas

in Table 7 on page 14, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal

instructions about the integrated radio module is not allowed.

The radiated output power of CYBLE-014008-00 is far below the FCC radio frequency exposure limits. Nevertheless, use

CYBLE-014008-00 in such a manner that minimizes the potential for human contact during normal operation.

End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with

transmitter operating conditions for satisfying RF exposure compliance.

Document Number: 002-00023 Rev. *K

Page 32 of 43

CYBLE-014008-00

Industry Canada (IC) Certification

CYBLE-014008-00 is licensed to meet the regulatory requirements of Industry Canada (IC),

License: IC: 7922A-4008

Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure

compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from

www.ic.gc.ca.

This device has been designed to operate with the antennas listed in Table 7 on page 14, having a maximum gain of 0.5 dBi. Antennas

not included in this list or having a gain greater than 0.5 dBi are strictly prohibited for use with this device. The required antenna

impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna

or transmitter.

IC NOTICE:

The device CYBLE-014008-00 complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter

approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful

interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.

IC RADIATION EXPOSURE STATEMENT FOR CANADA

This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1)

this device may not cause interference, and (2) this device must accept any interference, including interference that may cause

undesired operation of the device.

Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est

autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter

tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

LABELING REQUIREMENTS:

The Original Equipment Manufacturer (OEM) must ensure that IC labelling requirements are met. This includes a clearly visible label

on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the IC

Notice above. The IC identifier is 7922A-4008. In any case, the end product must be labeled in its exterior with "Contains IC:

7922A-4008".

European R&TTE Declaration of Conformity

Hereby, Cypress Semiconductor declares that the Bluetooth module CYBLE-014008-00 complies with the essential requirements and

other relevant provisions of Directive 1999/5/EC. As a result of the conformity assessment procedure described in Annex III of the

Directive 1999/5/EC, the end-customer equipment should be labeled as follows:

All versions of the CYBLE-014008-00 in the specified reference design can be used in the following countries: Austria, Belgium,

Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxem-

bourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.

Document Number: 002-00023 Rev. *K

Page 33 of 43

CYBLE-014008-00

MIC Japan

CYBLE-014008-00 is certified as a module with type certification number 203-JN0505. End products that integrate CYBLE-014008-00

do not need additional MIC Japan certification for the end product.

End product can display the certification label of the embedded module.

KC Korea

CYBLE-014008-00 is certified for use in Korea with certificate number MSIP-CRM-Cyp-4008.

Document Number: 002-00023 Rev. *K

Page 34 of 43

CYBLE-014008-00

Packaging

Table 56. Solder Reflow Peak Temperature

Module Part Number

Package

Maximum Peak Temperature Maximum Time at PeakTemperature No. of Cycles

260 °C 30 seconds

CYBLE-014008-00

32-pad SMT

2

Table 57. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Module Part Number

Package

MSL

CYBLE-014008-00

32-pad SMT

MSL 3

The CYBLE-014008-00 is offered in tape and reel packaging. Figure 10 details the tape dimensions used for the CYBLE-014008-00.

Figure 10. CYBLE-014008-00 Tape Dimensions

Figure 11 details the orientation of the CYBLE-014008-00 in the tape as well as the direction for unreeling.

Figure 11. Component Orientation in Tape and Unreeling Direction

Document Number: 002-00023 Rev. *K

Page 35 of 43

CYBLE-014008-00

Figure 12 details reel dimensions used for the CYBLE-014008-00.

Figure 12. Reel Dimensions

The CYBLE-014008-00 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The

center-of-mass for the CYBLE-014008-00 is detailed in Figure 13.

Figure 13. CYBLE-014008-00 Center of Mass

Document Number: 002-00023 Rev. *K

Page 36 of 43

CYBLE-014008-00

Ordering Information

Table 58 lists the CYBLE-014008-00 part number and features. Table 59 lists the reel shipment quantities for the CYBLE-014008-00.

Table 58. Ordering Information

Features

MPN

CYBLE-014008-00

48

128

16

4

✓

1 Msps

1

4

2

4

✓

25 32-SMT

Table 59. Tape and Reel Package Quantity and Minimum Order Amount

Description

Minimum Reel Quantity Maximum Reel Quantity

Comments

Ships in 500 unit reel quantities.

Reel Quantity

500

–

Minimum Order Quantity (MOQ)

Order Increment (OI)

–

The CYBLE-014008-00 is offered in tape and reel packaging. The CYBLE-014008-00 ships with a maximum of 500 units/reel.

Part Numbering Convention

The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.

For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales

representative. To locate the nearest Cypress office, visit our website.

U.S. Cypress Headquarters Address

U.S. Cypress Headquarter Contact Info

Cypress website address

198 Champion Court, San Jose, CA 95134

(408) 943-2600

http://www.cypress.com

Document Number: 002-00023 Rev. *K

Page 37 of 43

CYBLE-014008-00

Acronyms

Table 60. Acronyms Used in this Document (continued)

Table 60. Acronyms Used in this Document

Acronym

EMIF

Description

external memory interface

Acronym

ABUS

Description

analog local bus

EOC

EOF

EPSR

ESD

ETM

FCC

FET

FIR

end of conversion

ADC

AG

analog-to-digital converter

analog global

end of frame

execution program status register

electrostatic discharge

AMBA (advanced microcontroller bus

architecture) high-performance bus, an ARM

data transfer bus

AHB

embedded trace macrocell

Federal Communications Commission

field-effect transistor

finite impulse response, see also IIR

flash patch and breakpoint

full-speed

ALU

arithmetic logic unit

AMUXBUS analog multiplexer bus

API

application programming interface

APSR

ARM^®

ATM

BLE

application program status register

advanced RISC machine, a CPU architecture

automatic thump mode

FPB

FS

general-purpose input/output, applies to a PSoC

GPIO

Bluetooth Low Energy

HCI

HVI

IC

host controller interface

Bluetooth

SIG

Bluetooth Special Interest Group

high-voltage interrupt, see also LVI, LVD

integrated circuit

BW

bandwidth

Controller Area Network, a communications

protocol

IDAC

IDE

current DAC, see also DAC, VDAC

integrated development environment

CAN

CE

European Conformity

Inter-Integrated Circuit, a communications

protocol

I²C, or IIC

CSA

CMRR

CPU

Canadian Standards Association

common-mode rejection ratio

central processing unit

IC

Industry Canada

IIR

infinite impulse response, see also FIR

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

integral nonlinearity, see also DNL

input/output, see also GPIO, DIO, SIO, USBIO

initial power-on reset

cyclic redundancy check, an error-checking

protocol

ILO

IMO

INL

I/O

CRC

DAC

DFB

digital-to-analog converter, see also IDAC, VDAC

digital filter block

digital input/output, GPIO with only digital

capabilities, no analog. See GPIO.

DIO

IPOR

IPSR

IRQ

ITM

KC

interrupt program status register

interrupt request

DMIPS

DMA

DNL

DNU

DR

Dhrystone million instructions per second

direct memory access, see also TD

differential nonlinearity, see also INL

do not use

instrumentation trace macrocell

Korea Certification

LCD

liquid crystal display

port write data registers

Local Interconnect Network, a communications

protocol.

DSI

digital system interconnect

data watchpoint and trace

error correcting code

LIN

DWT

ECC

ECO

LR

link register

LUT

LVD

LVI

lookup table

external crystal oscillator

low-voltage detect, see also LVI

low-voltage interrupt, see also HVI

low-voltage transistor-transistor logic

electrically erasable programmable read-only

memory

EEPROM

EMI

LVTTL

electromagnetic interference

Document Number: 002-00023 Rev. *K

Page 38 of 43

CYBLE-014008-00

Table 60. Acronyms Used in this Document (continued)

Acronym Description

MAC multiply-accumulate

Table 60. Acronyms Used in this Document (continued)

Acronym

SDA

Description

I²C serial data

MCU

microcontroller unit

S/H

sample and hold

Ministry of Internal Affairs and Communications

(Japan)

SINAD

signal to noise and distortion ratio

MIC

special input/output, GPIO with advanced

features. See GPIO.

SIO

MISO

NC

master-in slave-out

no connect

surface-mount technology; a method for

producing electronic circuitry in which the

components are placed directly onto the surface

of PCBs

NMI

nonmaskable interrupt

non-return-to-zero

SMT

NRZ

NVIC

NVL

nested vectored interrupt controller

nonvolatile latch, see also WOL

operational amplifier

SOC

SOF

start of conversion

start of frame

Opamp

PAL

Serial Peripheral Interface, a communications

protocol

SPI

programmable array logic, see also PLD

program counter

SR

slew rate

PC

SRAM

SRES

STN

SWD

SWV

TD

static random access memory

software reset

PCB

PGA

PHUB

PHY

PICU

PLA

printed circuit board

programmable gain amplifier

peripheral hub

super twisted nematic

serial wire debug, a test protocol

single-wire viewer

physical layer

port interrupt control unit

programmable logic array

programmable logic device, see also PAL

phase-locked loop

transaction descriptor, see also DMA

total harmonic distortion

transimpedance amplifier

twisted nematic

THD

TIA

PLD

PLL

TN

PMDD

POR

PRES

PRS

PS

PSoC^®

PSRR

PWM

QDID

RAM

RISC

RMS

RTC

RTL

package material declaration data sheet

power-on reset

TRM

TTL

technical reference manual

transistor-transistor logic

precise power-on reset

pseudo random sequence

port read data register

Programmable System-on-Chip™

power supply rejection ratio

pulse-width modulator

qualification design ID

random-access memory

reduced-instruction-set computing

root-mean-square

Germany: Technischer Überwachungs-Verein

(Technical Inspection Association)

TUV

TX

transmit

Universal Asynchronous Transmitter Receiver, a

communications protocol

UART

UDB

USB

universal digital block

Universal Serial Bus

USB input/output, PSoC pins used to connect to

a USB port

USBIO

VDAC

WDT

voltage DAC, see also DAC, IDAC

watchdog timer

real-time clock

WOL

write once latch, see also NVL

watchdog timer reset

external reset I/O pin

crystal

register transfer language

remote transmission request

receive

WRES

XRES

XTAL

RTR

RX

SAR

SC/CT

SCL

successive approximation register

switched capacitor/continuous time

I²C serial clock

Document Number: 002-00023 Rev. *K

Page 39 of 43

CYBLE-014008-00

Document Conventions

Units of Measure

Table 61. Units of Measure

Symbol

°C

Unit of Measure

degrees Celsius

decibel

dB

dBm

fF

decibel-milliwatts

femtofarads

hertz

Hz

KB

1024 bytes

kbps

Khr

kHz

k

kilobits per second

kilohour

kilohertz

kilo ohm

ksps

LSB

Mbps

MHz

M

Msps

µA

kilosamples per second

least significant bit

megabits per second

megahertz

mega-ohm

megasamples per second

microampere

microfarad

µF

µH

microhenry

µs

microsecond

microvolt

µV

µW

mA

ms

microwatt

milliampere

millisecond

mV

nA

millivolt

nanoampere

nanosecond

nanovolt

ns

nV



ohm

pF

picofarad

ppm

ps

parts per million

picosecond

second

s

sps

sqrtHz

V

samples per second

square root of hertz

volt

Document Number: 002-00023 Rev. *K

Page 40 of 43

CYBLE-014008-00

Document History Page

Document Title: CYBLE-014008-00 EZ-BLE™ PSoC^®Module

Document Number: 002-00023

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

4895738

4910660

DSO

8/26/2015 Preliminary datasheet for CYBLE-014008-00 module.

*A

9/07/2015 Modify reference of VDD/VDDA minimum voltage from 1.8V to 1.71V.

Update Table 2 on page 6 Connections number from 21 to 32.

Remove Footnotes 4, 5, and 6 on Page 8.

Update Table 5 on page 10 to remove LPCOMP capabilities from Pads 2, 3, 4,

14, 30, and 31.

Update Table 5 on page 10 to specify Vref (Pad 26) as Optional.

Update Figure 7 on page 11 to swap diagram descriptions.

Update Table 11 on page 17 T_Hibernatefrom 2 ms to 800 µs.

Update Table 54 on page 28 - changed power consumption Iavg_1sec from

18.5 mA to 17.1 mA.

Update Table 54 on page 28 - changed power consumption Iavg_4sec from

6.25 mA to 6.1 mA.

*B

4944131

DSO

09/25/2015 Update Table 3 on page 8 to correct a typo in seventh row - changed “Distance

from top right corner to Pad 6 center” to ““Distance from Pad 5 center to Pad

6 center”.

Corrected Footnotes 3 to specify ground connection as Pad 1 and Pad 32.

Added V_DDAto V_{DDD_RIPPLE}specification description Table 8 on page 15.

Update Table 10 on page 15, parameters V_DD1and V_DD2to specify that

V_DD= V_DDA= V_DDR

Removed Table 14 (OVT GPIO DC Specifications) and Table 15 (OVT GPIO

AC Specifications).

Added regulatory certification country in RF Certification on page 31.

Added Document History Page section on page 41.

*C

5060713

DSO

01/07/2016 Update General Description to add reference link to PSoC^®4 BLE datasheet

and include Declaration ID number.

Added More Information section to the datasheet.

Updated Figure 1, Figure 2, Figure 3, and Figure 4 to improve clarity and

viewing.

Added Figure 5 in Recommended Host PCB Layout section to show solder pad

location from module origin.

Updated Figure 6 and Table 3 in Recommended Host PCB Layout section to

show solder pad location from module origin.

Update Regulatory Information section to include final FCC, IC, and KC

certification identification numbers.

Added French translation for IC Radiation Exposure Statement For Canada in

Industry Canada (IC) Certification section on page 33 in accordance with IC

requirements.

Updated MIC Japan section on page 34 to specify final MIC certification

number.

Added Packaging section.

Added Table 56 and Table 57 on page 35.

*D

5099201

DSO

01/22/2016 Remove Preliminary from datasheet header and release as final.

Update More Information section to add KBA210574 (Certification Test

Reports) to reference list.

Update General Description to include reference and link for QDID and

Declaration ID.

Updated orientation of module drawings in Figure 1, Figure 2, Figure 3,

Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, and Figure 13 to

match

orientation in PSoC Creator.

Document Number: 002-00023 Rev. *K

Page 41 of 43

CYBLE-014008-00

Document History Page (continued)

Document Title: CYBLE-014008-00 EZ-BLE™ PSoC^®Module

Document Number: 002-00023

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

*E

5146846

DSO

02/22/2016 Updated Table 4 to add Positive (P) and Negative (N) indicator to TCPWM

functionalities.

*F

5152410

5424383

DSO

02/26/2016 Updated Up to 25 Programmable GPIOs.

*G

09/02/2016 Updated General Description:

Updated Power Consumption:

Replaced “Stop: 60 nA with XRES wakeup” with “Stop: 60 nA with GPIO (P2.2)

or XRES wakeup” under “Low power mode support”.

Updated More Information:

Added additional Knowledge Base Article references.

Updated Electrical Specification:

Updated System Resources:

Updated Internal Low-Speed Oscillator:

Updated Table 52 (Updated details in “Value” column corresponding to

ECO_TRIMparameter).

Updated Ordering Information:

No change in part numbers.

Added Table 59 (To specify minimum and maximum reel quantities that ship

for orders of the CYBLE-014008-00 module).

Updated to new template.

*H

5528433

DSO

11/21/2016 Updated More Information:

Added EZ-Serial™ BLE Firmware Platform section.

Updated Overview:

Updated Figure 1 to specify that Bottom View is “Seen from Bottom”.

Updated Recommended Host PCB Layout:

Updated Figure 4, Figure 5, and Figure 6 captions to specify that these as

“Seen on Host PCB”.

Updated Power Supply Connections and Recommended External Compo-

nents:

Updated Figure 7 and Figure 8 to specify that these are “Seen from Bottom”.

Updated Digital and Analog Capabilities and Connections:

Updated Table 4:

Updated TCPWM column to add TCPWM capability on Port 2 pins.

Added Footnote 3.

Updated Document History Page:

Remove “,” from Document Title.

*I

5553544

DSO

12/14/2016 Updated Table 5:

Port 2.x OPAMP definitions changed to CTBm0 instead of CTBm1.

Updated Power Supply Connections and Recommended External Compo-

nents:

Updated typo to state that the use of one to three ferrite beads will depend on

the application configuration.

*J

5709580

6002363

GNKK

DSO

04/24/2017 Updated the Cypress logo and copyright information.

12/22/2017 Updated reel dimensions in Figure 10 and Figure 12.

*K

Document Number: 002-00023 Rev. *K

Page 42 of 43

CYBLE-014008-00

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

Arm^®Cortex^®Microcontrollers

cypress.com/arm

cypress.com/automotive

cypress.com/clocks

cypress.com/interface

cypress.com/iot

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU

Automotive

Cypress Developer Community

Clocks & Buffers

Interface

Technical Support

Internet of Things

Memory

cypress.com/support

cypress.com/memory

cypress.com/mcu

Microcontrollers

PSoC

cypress.com/psoc

Power Management ICs

Touch Sensing

USB Controllers

Wireless Connectivity

cypress.com/pmic

cypress.com/touch

cypress.com/usb

cypress.com/wireless

including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries

worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other

intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress

hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to

modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users

(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as

provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation

of the Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing

device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,

such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product

to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any

liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming

code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this

information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons

systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances

management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device

or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you

shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from

and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

Document Number: 002-00023 Rev. *K

Revised December 22, 2017

Page 43 of 43


型号：	CYBLE-014008-00
厂家：	CYPRESS
描述：	Microprocessor Circuit, CMOS, PACKAGE 外围集成电路
文件：	总43页 (文件大小：943K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CYBLE-014008-00 [CYPRESS]

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