ESDALC6V1P [ETC]

QUAD LOW CAPACITANCE TRANSIL ARRAY FOR ESD PROTECTION ; 四路低电容TRANSIL阵列，用于ESD保护\n


型号：	ESDALC6V1P
厂家：	ETC
描述：	QUAD LOW CAPACITANCE TRANSIL ARRAY FOR ESD PROTECTION 四路低电容TRANSIL阵列，用于ESD保护\n
文件：	总9页 (文件大小：199K)
中文：	中文翻译
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ESDALC6V1P6

QUAD LOW CAPACITANCE TRANSIL™

ARRAY FOR ESD PROTECTION

Application Specific Discretes

A.S.D.

MAIN APPLICATIONS

Where transient overvoltage protection in ESD

sensitive equipment is required, such as :

■

Computers

Printers

Communication systems and cellular phones

Video equipment

This device is particularly adapted to the protection

of symmetrical signals.

SOT666

FEATURES

■

4 UNIDIRECTIONAL TRANSIL™ FUNCTIONS.

BREAKDOWN VOLTAGE V_BR= 6.1V MIN.

LOW DIODE CAPACITANCE (12pF @ 0V)

LOW LEAKAGE CURRENT < 500 nA

VERY SMALL PCB AREA < 2.6 mm²

FUNCTIONAL DIAGRAM

DESCRIPTION

The ESDALC6V1P6 is a monolithic array designed

to protect up to 4 lines against ESD transients.

I/O1

GND

I/O2

I/O4

GND

I/O3

This device is ideal for applications where both

reduced line capacitance and board space saving

are required.

BENEFITS

■

High ESD protection level.

High integration.

Suitable for high density boards.

COMPLIES WITH THE FOLLOWING STANDARDS :

■

IEC61000-4-2 level 4: 15 kV (air discharge)

8 kV (contact discharge)

■

MIL STD 883E-Method 3015-7: class 3

25kV HBM (Human Body Model)

March 2003 - Ed: 2A

1/9

ESDALC6V1P6

ABSOLUTE RATINGS (T_amb= 25°C)

Symbol

Parameter

Test conditions

Value

Unit

V_PP

ESD discharge - IEC61000-4-2 air discharge

IEC61000-4-2 contact discharge

± 15

± 8

P_PP

T_j

Peak pulse power (8/20 µs) (see note 1)

Junction temperature

T_jinitial = Tamb

125

°C

T_stg

T_L

Storage temperature range

- 55 to + 150

260

Maximum lead temperature for soldering during 10s at N/A

Operating temperature range

T_op

- 40 to + 125

Note 1: for a surge greater than the maximum values, the diode will fail in short-circuit.

THERMAL RESISTANCES

Symbol

Parameter

Value

Unit

R_th(j-a)

Junction to ambient on printed circuit on recommended pad layout

220

°C/W

ELECTRICAL CHARACTERISTICS (T_amb= 25°C)

Symbol

V_RM

V_BR

V_CL

I_RM

I_PP

Parameter

Stand-off voltage

I_F

Breakdown voltage

Clamping voltage

V_F

Leakage current

V_CLV_BRV_RM

I_RM

Peak pulse current

Voltage tempature coefficient

Forward voltage drop

Capacitance per line

Dynamic resistance

αT

V_F

Slope: 1/R_d

I_PP

R_d

V_BR

I_R

I_RM

V_RM

αT

typ.

@ 0V

min.

max.

typ.

max.

Types

µA

Ω

10^-4/°C

4.5

ESDALC6V1P6

6.1

7.2

0.5

1.5

Note 1 : Square pulse Ipp = 15A, tp=2.5µs.

Note 2 : ∆ V

= αT* (Tamb -25°C) * V

(25°C)

2/9

ESDALC6V1P6

Fig. 1: Relative variation of peak pulse power

versus initial junction temperature.

Fig. 2: Peak pulse power versus exponential pulse

duration.

P_PP[T_jinitial] / P_PP[T_jinitial=25°C)

1.1

P_PP(W)

1000

T_jinitial=25°C

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

100

0.1

T_j(°C)

T_p(µs)

0.0

100

125

150

100

Fig. 3: Clamping voltage versus peak pulse

current (typical values, rectangular waveform).

Fig. 4: Forward voltage drop versus peak forward

current (typical values).

I_FM(A)

I_PP(A)

100.0

1.E+00

t_p=2.5µs

T_jinitial=25°C

T_j=125°C

T_j=25°C

1.E-01

10.0

1.0

1.E-02

V_CL(V)

V_FM(V)

1.0

1.E-03

0.1

0.0

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.0

Fig. 5: Junction capacitance versus reverse

voltage applied (typical values).

Fig. 6: Relative variation of leakage current versus

junction temperature (typical values).

C(pF)

[T ] / I [T =25°C]

j R j

1000

100

F=1MHz

V_OSC=30mV_RMS

T_j=25°C

V_R=3V

(V)

T (°C)

100

125

3/9

ESDALC6V1P6

TECHNICAL INFORMATION

1. ESD protection by ESDALC6V1P6

Fig. A1: Application example.

With the focus of lowering the operation levels, the

problem of malfunction caused by the environment

is critical. Electrostatic discharge (ESD) is a major

cause of failure in electronic systems.

I/O2

I/O1

transient voltage suppressor, the

to be

protected

ESDALC6V1P6 is an ideal choice for ESD protec-

tion by suppressing ESD events. It is capable of

clamping the incoming transient to a low enough

level such that any damage is prevented on the de-

vice to be protected by ESDALC6V1P6.

I/O4

I/O3

ESDALC6V1P6 serves as a parallel protection

element, connected between signal line and

ground. As the transient rises above the operating

voltage of the device, the ESDALC6V1P6

becomes a low impedance path diverting the

transient current to ground.

The clamping voltage is given by the following formula:

V_CL= V_BR+ R_d.I_PP

As shown in figure A2, the ESD strikes are clamped by the transient voltage suppressor.

Fig. A2: ESD clamping behavior.

LOAD

V(i/o)

Device

to be

ESD surge

ESDALC6V1P6

protected

slope =

= V +R x I

To have a good approximation of the remaining voltages at both Vi/o side, we provide the typical dynamical

resistance value R_d. By taking into account the following hypothesis:

R_G> R_dand R_load> R_d

we have:

V_g

V i / o = V + R_d×

( )

R_g

The results of the calculation done for V_G= 8kV, R_G= 330Ω (IEC61000-4-2 standard), V_BR= 6.4V (typ.)

and R_d= 1.5Ω (typ.) give:

V i / o = 42.8Volts

( )

This confirms the very low remaining voltage across the device to be protected. It is also important to note

that in this approximation the parasitic inductance effect was not taken into account. This could be a few

tenths of volts during a few ns at the Vi/o side.

4/9

ESDALC6V1P6

Fig. A3: ESD test board.

Fig. A4: ESD test configuration.

± 15kV ESD

Air discharge

I/O1, I/O2, I/O3 or I/O4

V(i/o)

± 15kV ESD

V(i/o)

Air discharge

GND

ESDALC6V1P6

The measurements done here after show very clearly (figure A5) the high efficiency of the ESD protection:

the clamping voltage V(i/o) becomes very close to V_BR(positive way, figure A5a) and -V_F(negative way,

figure A5b).

Fig. A5: Remaining voltage during ESD surge.

a: Response in the positive way

b: Response in the negative way

One can note that the ESDALC6V1P6 is not only acting for positive ESD surges but, also, for negative

ones. For this kind of disturbances, it clamps close to ground voltage as shown in figure A5b.

5/9

ESDALC6V1P6

2. Crosstalk behavior

Fig. A6: Crosstalk phenomenon.

RG1

Line 1

Line 2

VG1

R_L1

α₁V_G1+ β₁₂V_G2

RG2

VG2

R_L2

α₂V_G2+ β₂₁V_G1

DRIVERS

RECEIVERS

The crosstalk phenomena are due to the coupling between 2 lines. Coupling factors ( β12 or β21 ) increase

when the gap across lines decreases, particularly in silicon dice. In the example above, the expected signal

on load R_L2is α₂V_G2, in fact the real voltage at this point has got an extra value β₂₁V_G2. This part of the V_G1

signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has

to be taken into account when the drivers impose fast digital data or high frequency analog signals. The

perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ).

Fig. A7: Analog crosstalk test configuration.

Fig. A8: Typical analog crosstalk response.

0.00

-10.00

I/O1

50Ω

unloaded

-20.00

-30.00

-40.00

-50.00

-60.00

-70.00

-80.00

-90.00

-100.00

Port 1

GND

50Ω

Port 2

I/O4

100.0k

1.0M

10.0M

100.0M

1.0G

f/Hz

Figure A7 gives the measurement circuit for the analog crosstalk application. In figure 8, the curve shows

the effect of the cell I/O1 on the cell I/O4. In usual frequency range of analog signals (up to 100 MHz) the

effect on disturbed line is less than -55dB.

6/9

ESDALC6V1P6

Fig. A9: Digital crosstalk test configuration.

Fig. A10: Typical digital crosstalk response.

I/O1

unloaded

V_G1

V^G1

0 - 5V

pulse generator

F= 100kHz

GND

β21VG1

t^R= 20ns

β₂₁V_G1

unloaded

I/O4

Figure A9 shows the measurement circuit used to quantify the crosstalk effect in a classical digital

application.

Figure A10 shows that in such a condition, ie signal from 0 to 5V and rise time of a few ns, the impact on the

disturbed line is less than 5 mV peak to peak. No data disturbance was noted on the concerned line. The

measurements performed with falling edges give an impact within the same range.

3. PCB layout recommendations

As ESD is a fast event, the di/dt caused by this surge is about 30A/ns (risetime=1ns, Ipeak=30A), that

means each nH causes an overvoltage of 30V.

Thus, the circuit board layout is a critical design step in the suppression of ESD induced transients by

reducing parasitic inductances. To ensure that, the following guidelines are recommended :

■

The ESDALC6V1P6 should be placed as close as possible to the input terminals or connectors.

The path length between the ESD suppressor and the protected line should be minimized.

All conductive loops, including power and ground loops should be minimized.

The ESD transient return path to ground should be kept as short as possible.

The connections from the ground pins to the ground plane should be the shortest possible.

4. Comparison with varistors

Varistors

TRANSIL™

Leakage current

+++

Protection efficiency

Ageing

Low leakage current for Transil™ device

■

Improve the autonomy of portable equipments as mobile

Better efficiency in terms of ESD protection by using Transil™ device

■

Varistors are bidirectional devices and so are not suitable to protect sensitive ICs, because they will be

submitted to high voltages in the negative way.

■

Ratio V_CL/V_BRlower for Transil™ device

Less dispersion in terms of V_BR

No ageing phenomena regarding ESD events with Transil™ device

Higher efficiency in terms of ESD protection

■

7/9

ESDALC6V1P6

ORDER CODE

ESDA LC 6V1 P6

ESD ARRAY

LOW CAPACITANCE

PACKAGE: SOT666

V^BRmin

Ordering type

ESDALC6V1P6

Marking

Package

Weight

Base qty

Delivery mode

Tape & reel

SOT666

2.9 mg.

3000

8/9

ESDALC6V1P6

PACKAGE MECHANICAL DATA

SOT-666

DIMENSIONS

Millimeters Inches

Min.

REF.

Min.

Max.

0.60

0.27

0.18

1.70

1.30

Max.

0.024

0.011

0.007

0.067

0.051

0.50

0.17

0.08

1.50

1.10

0.020

0.007

0.003

0.060

0.043

1.00

0.50

0.040

0.020

0.059

0.004

1.50

0.10

1.70

0.30

0.067

0.012

FOOT PRINT (in millimeters)

0.36

0.30

0.62

2.30

0.84

0.20

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of

use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by

implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied.

STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap-

proval of STMicroelectronics.

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9/9

ESDALC6V1P [ETC]

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