NJU6823 [ETC]
128-common x (128+2)-RGB segment 4096-color STN Bitmap LCD Driver ; 128常见×（ 128 + 2 ） -RGB段4096色STN液晶屏位图驱动
| 型号： | NJU6823 |
| 厂家： | 
ETC |
| 描述： | 128-common x (128+2)-RGB segment 4096-color STN Bitmap LCD Driver
|
| 文件： | 总111页 (文件大小：998K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJU6823
Preliminary
128-common x (128+2) RGB-Segment, in 4096-Color
STN LCD DRIVER
ꢀ GENERAL DESCRIPTION
ꢀ PACKAGE OUTLINE
The NJU6823 is a STN LCD driver with 128-common x
(128+2) RGB-segment in 4096-color. It consists of
384(128xRGB)-segment + 6(2xRGB)-icon segment, 128-
common drivers, serial and parallel MPU interface circuits,
internal power supply circuits, gradation palettes and
196,608-bit for graphic display data RAM.
Each segment driver outputs 16-gradation level out of
32-gradation level of gradation palette.
NJU6823CJ
Since the NJU6823 provides low operating voltage of
1.7V and low operating current, it is ideally suited for
battery-powered handheld applications.
ꢀ FEATURES
ꢁ 4096-color STN LCD driver
ꢁ LCD drivers
128 commons, 128RGB-segments, 2 RGB-icon segments
196,608-bit for graphic display
ꢁ Display data RAM (DDRAM)
ꢁ Color display mode
16 gradation level out of 32-gradation level of gradation palette
128 x 384 pixels in 16-gradation level or 128 x 384 pixels in B&W
ꢁ Black & white display mode
ꢁ 256-color driving mode
ꢁ 8/16bit Parallel interface directly-connective to 68/80 series MPU
ꢁ Programmable 8- or 16-bit data bus length for display data
ꢁ 3-/4-line serial interface
ꢁ Programmable duty and bias ratios
ꢁ Programmable internal voltage booster (Maximum 6-times)
ꢁ Bias voltage adjustment circuits
Programmable clock frequency
ꢁ Programmable contrast control using 128-step EVR
ꢁ Various instructions
Display data read/write, Display ON/OFF, Reverse display ON/OFF, All pixels ON/OFF,
column address, row address, N-line inversion, Initial display line, Initial COM line, Read-modify-write,
Gradation mode control, Increment control, Data bus length, Discharge ON/OFF,
Duty cycle ratio, LCD bias ratio, Boost level, EVR control, Power save ON/OFF, etc
ꢁ Low operating current
ꢁ Low logic supply voltage
ꢁ LCD driving supply voltage
ꢁ C-MOS technology
ꢁ Rectangle out look for COG
ꢁ Package
1.7V to 3.3V
5.0V to 18.0V
Bumped chip / TCP
02/11/22
- 1 -
NJU6823
ꢀ PAD LOCATION
DMY44
DMY45
DMY46
COM114
COM127
DMY47
DMY71
1
Note1) The same name PADs are shorted mutually in the LSI.
Note2) The DMY PADs are electrically open.
Chip Center
Chip Size
:X= 0µm, Y= 0µm
:22.07mm x 2.55mm
Chip Thickness
Bump Size
:625µm ± 25µm
:28µm x 110µm(COM/SEG Output, DMY10 ~ DMY71),
60µm x 100µm(Interface),
28µm x 100µm(DMY0 ~ DMY9)
:43µm(Min)
Bump Pitch
Bump Height
Bump Material
:14.0~22.5µm (Typical 18µm) <tolerance : ±3µm >
:Au
Alignment marks
a: 30µm
b: 6µm
c: 120µm
d: 27µm
Alignment mark coordinates
X=-10866µm, Y= 1106µm
X= 10866µm, Y=-1106µm
- 2 -
NJU6823
X
- 3 -
NJU6823
DMY37
DMY36
DMY35
COM50
Y
X
COM63
DMY34
DMY10
- 4 -
NJU6823
ꢀ PAD COORDINATES 1
Chip Size 22070µm x 2550µm (Chip Center 0µm x 0µm )
PAD
PAD
No.
PAD
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
No.
1
No.
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
DMY0
DMY1
DMY2
VSSA
-10642.5 -1090.0 52
-10599.5 -1090.0 53
-10556.5 -1090.0 54
-10475.5 -1090.0 55
-10402.5 -1090.0 56
-10293.0 -1090.0 57
-10220.0 -1090.0 58
-10110.5 -1090.0 59
-10037.5 -1090.0 60
-9928.0 -1090.0 61
-9855.0 -1090.0 62
-9745.5 -1090.0 63
-9672.5 -1090.0 64
-9563.0 -1090.0 65
-9490.0 -1090.0 66
-9380.5 -1090.0 67
-9271.0 -1090.0 68
-9198.0 -1090.0 69
-9088.5 -1090.0 70
-8979.0 -1090.0 71
-8906.0 -1090.0 72
-8796.5 -1090.0 73
-8687.0 -1090.0 74
-8614.0 -1090.0 75
-8504.5 -1090.0 76
-8395.0 -1090.0 77
-8322.0 -1090.0 78
-8212.5 -1090.0 79
-8139.5 -1090.0 80
-7993.5 -1090.0 81
-7920.5 -1090.0 82
-7774.5 -1090.0 83
-7701.5 -1090.0 84
-7555.5 -1090.0 85
-7482.5 -1090.0 86
D10
D10
-5584.5 -1090.0
-5511.5 -1090.0
-5365.5 -1090.0
-5292.5 -1090.0
-5146.5 -1090.0
-5073.5 -1090.0
-4927.5 -1090.0
-4854.5 -1090.0
-4708.5 -1090.0
-4635.5 -1090.0
-4489.5 -1090.0
-4416.5 -1090.0
-4197.5 -1090.0
-4124.5 -1090.0
-4051.5 -1090.0
-3978.5 -1090.0
-3905.5 -1090.0
-3832.5 -1090.0
-3759.5 -1090.0
-3613.5 -1090.0
-3540.5 -1090.0
-3394.5 -1090.0
-3321.5 -1090.0
-3175.5 -1090.0
-3102.5 -1090.0
-2956.5 -1090.0
-2883.5 -1090.0
-2701.0 -1090.0
-2628.0 -1090.0
-2409.0 -1090.0
-2336.0 -1090.0
-2044.0 -1090.0
-1971.0 -1090.0
-1898.0 -1090.0
-1825.0 -1090.0
-1752.0 -1090.0
-1679.0 -1090.0
-1606.0 -1090.0
-1460.0 -1090.0
-1387.0 -1090.0
-1277.5 -1090.0
-1204.5 -1090.0
-1095.0 -1090.0
-1022.0 -1090.0
V4A2
VSSA
VSSA
VLCD
VLCD
VLCD
VLCD
VLCD
VLCD
V1
-292.0
-182.5
-109.5
0.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
2
3
D11
4
D11
5
VSSA
D12
73.0
6
SEL68
SEL68
VDDA
D12
146.0
219.0
292.0
365.0
511.0
584.0
657.0
730.0
803.0
876.0
7
D13
8
D13
9
VDDA
D14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
P/S
D14
P/S
D15
V1
VSSA
D15
V1
VSSA
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CL
V1
RESb
RESb
DMY3
CSb
V1
V1
V2
1022.0 -1090.0
1095.0 -1090.0
1168.0 -1090.0
1241.0 -1090.0
1314.0 -1090.0
1387.0 -1090.0
1533.0 -1090.0
1606.0 -1090.0
1679.0 -1090.0
1752.0 -1090.0
1825.0 -1090.0
1898.0 -1090.0
2044.0 -1090.0
2117.0 -1090.0
2190.0 -1090.0
2263.0 -1090.0
2336.0 -1090.0
2409.0 -1090.0
2555.0 -1090.0
2628.0 -1090.0
2701.0 -1090.0
2774.0 -1090.0
2847.0 -1090.0
2920.0 -1090.0
3029.5 -1090.0
3102.5 -1090.0
3175.5 -1090.0
3248.5 -1090.0
3321.5 -1090.0
3394.5 -1090.0
3504.0 -1090.0
3577.0 -1090.0
3650.0 -1090.0
3723.0 -1090.0
3796.0 -1090.0
3869.0 -1090.0
V2
CSb
V2
DMY4
RS
V2
V2
RS
CL
V2
DMY5
WRb
WRb
DMY6
RDb
FLM
FLM
FR
V3
V3
V3
FR
V3
CLK
CLK
OSC1
OSC1
OSC2
OSC2
VSS
V3
RDb
V3
VDDA
V4
VDDA
V4
D0/SCL
D0/SCL
D1/SDA
D1/SDA
D2
V4
V4
V4
VSS
V4
VSS
VREG
VREG
VREG
VREG
VREG
VREG
VREF
VREF
VREF
VREF
VREF
VREF
VBA
VBA
VBA
VBA
VBA
VBA
D2
VSS
36 D3/SMODE -7336.5 -1090.0 87
37 D3/SMODE -7263.5 -1090.0 88
VSS
VSS
38
39
40
41
42
43
44
45
46
47
48
49
50
51
D4/SPOL
D4/SPOL
D5
-7117.5 -1090.0 89
-7044.5 -1090.0 90
-6898.5 -1090.0 91
-6825.5 -1090.0 92
-6679.5 -1090.0 93
-6606.5 -1090.0 94
-6460.5 -1090.0 95
-6387.5 -1090.0 96
-6241.5 -1090.0 97
-6168.5 -1090.0 98
-6022.5 -1090.0 99
-5949.5 -1090.0 100
-5803.5 -1090.0 101
-5730.5 -1090.0 102
VSS
V1A1
V1A1
VDDA
VDDA
V1A2
V1A2
VSSA
VSSA
V4A1
V4A1
VDDA
VDDA
V4A2
D5
D6
D6
D7
D7
-912.5
-839.5
-730.0
-657.0
-547.5
-474.5
-365.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
-1090.0
VSSA
VSSA
D8
D8
D9
D9
- 5 -
NJU6823
ꢀ PAD COORDINATES 2
Chip Size 22070µm x 2550µm (Chip Center 0µm x 0µm )
PAD
PAD
No.
PAD
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
No.
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
No.
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VSSH
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VEE
VEE
VEE
VEE
VEE
VEE
VEE
C1+
C1+
C1+
C1+
C1+
C1+
C1-
4051.5 -1090.0 205
4124.5 -1090.0 206
4197.5 -1090.0 207
4270.5 -1090.0 208
4343.5 -1090.0 209
4416.5 -1090.0 210
4489.5 -1090.0 211
4672.0 -1090.0 212
4745.0 -1090.0 213
4818.0 -1090.0 214
4891.0 -1090.0 215
4964.0 -1090.0 216
5037.0 -1090.0 217
5110.0 -1090.0 218
5292.5 -1090.0 219
5365.5 -1090.0 220
5438.5 -1090.0 221
5511.5 -1090.0 222
5584.5 -1090.0 223
5657.5 -1090.0 224
5730.5 -1090.0 225
5840.0 -1090.0 226
5913.0 -1090.0 227
5986.0 -1090.0 228
6059.0 -1090.0 229
6132.0 -1090.0 230
6205.0 -1090.0 231
6314.5 -1090.0 232
6387.5 -1090.0 233
6460.5 -1090.0 234
6533.5 -1090.0 235
6606.5 -1090.0 236
6679.5 -1090.0 237
6789.0 -1090.0 238
6862.0 -1090.0 239
6935.0 -1090.0 240
7008.0 -1090.0 241
7081.0 -1090.0 242
7154.0 -1090.0 243
7263.5 -1090.0 244
7336.5 -1090.0 245
7409.5 -1090.0 246
7482.5 -1090.0 247
7555.5 -1090.0 248
7628.5 -1090.0 249
7738.0 -1090.0 250
7811.0 -1090.0 251
7884.0 -1090.0 252
7957.0 -1090.0 253
8030.0 -1090.0 254
8103.0 -1090.0 255
C3-
C3-
8212.5 -1090.0
8285.5 -1090.0
8358.5 -1090.0
8431.5 -1090.0
8504.5 -1090.0
8577.5 -1090.0
8687.0 -1090.0
8760.0 -1090.0
8833.0 -1090.0
8906.0 -1090.0
8979.0 -1090.0
9052.0 -1090.0
9161.5 -1090.0
9234.5 -1090.0
9307.5 -1090.0
9380.5 -1090.0
9453.5 -1090.0
9526.5 -1090.0
9636.0 -1090.0
9709.0 -1090.0
9782.0 -1090.0
9855.0 -1090.0
9928.0 -1090.0
10001.0 -1090.0
10110.5 -1090.0
10183.5 -1090.0
10256.5 -1090.0
10329.5 -1090.0
10402.5 -1090.0
10475.5 -1090.0
10556.5 -1090.0
10599.5 -1090.0
10642.5 -1090.0
10845.0 -881.5
10845.0 -838.5
10845.0 -795.5
10845.0 -752.5
10845.0 -709.5
10845.0 -666.5
10845.0 -623.5
10845.0 -580.5
10845.0 -537.5
10845.0 -494.5
10845.0 -451.5
10845.0 -408.5
10845.0 -365.5
10845.0 -322.5
10845.0 -279.5
10845.0 -236.5
10845.0 -193.5
10845.0 -150.5
DMY28
DMY29
DMY30
DMY31
DMY32
DMY33
DMY34
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
DMY35
DMY36
DMY37
DMY38
DMY39
DMY40
COM49
COM48
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
COM31
COM30
COM29
COM28
COM27
COM26
10845.0 -107.5
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
10845.0
-64.5
-21.5
21.5
C3-
C3-
C3-
64.5
C3-
107.5
150.5
193.5
236.5
279.5
322.5
365.5
408.5
451.5
494.5
537.5
580.5
623.5
666.5
709.5
752.5
795.5
838.5
881.5
C4+
C4+
C4+
C4+
C4+
C4+
C4-
C4-
C4-
C4-
C4-
C4-
C5+
C5+
C5+
C5+
C5+
C5+
C5-
10642.5 1085.0
10599.5 1085.0
10556.5 1085.0
10513.5 1085.0
10470.5 1085.0
10427.5 1085.0
10384.5 1085.0
10341.5 1085.0
10298.5 1085.0
10255.5 1085.0
10212.5 1085.0
10169.5 1085.0
10126.5 1085.0
10083.5 1085.0
10040.5 1085.0
C5-
C5-
C5-
C1-
C5-
C1-
C5-
C1-
DMY7
DMY8
DMY9
DMY10
DMY11
DMY12
DMY13
DMY14
DMY15
DMY16
DMY17
DMY18
DMY19
DMY20
DMY21
DMY22
DMY23
DMY24
DMY25
DMY26
DMY27
C1-
C1-
C2+
C2+
C2+
C2+
C2+
C2+
C2-
9997.5
9954.5
9911.5
9868.5
9825.5
9782.5
9739.5
9696.5
9653.5
9610.5
9567.5
9524.5
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
C2-
C2-
C2-
C2-
C2-
C3+
C3+
C3+
C3+
C3+
C3+
- 6 -
NJU6823
ꢀ PAD COORDINATES 3
Chip Size 22070µm x 2550µm (Chip Center 0µm x 0µm )
PAD
PAD
No.
PAD
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
No.
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
No.
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
9481.5 1085.0 358
9438.5 1085.0 359
9395.5 1085.0 360
9352.5 1085.0 361
9309.5 1085.0 362
9266.5 1085.0 363
9223.5 1085.0 364
9180.5 1085.0 365
9137.5 1085.0 366
9094.5 1085.0 367
9051.5 1085.0 368
9008.5 1085.0 369
8965.5 1085.0 370
8922.5 1085.0 371
8879.5 1085.0 372
8836.5 1085.0 373
8793.5 1085.0 374
8750.5 1085.0 375
8707.5 1085.0 376
8664.5 1085.0 377
8621.5 1085.0 378
8578.5 1085.0 379
8535.5 1085.0 380
8492.5 1085.0 381
8449.5 1085.0 382
8406.5 1085.0 383
8363.5 1085.0 384
8320.5 1085.0 385
8277.5 1085.0 386
8234.5 1085.0 387
8191.5 1085.0 388
8148.5 1085.0 389
8105.5 1085.0 390
8062.5 1085.0 391
8019.5 1085.0 392
7976.5 1085.0 393
7933.5 1085.0 394
7890.5 1085.0 395
7847.5 1085.0 396
7804.5 1085.0 397
7761.5 1085.0 398
7718.5 1085.0 399
7675.5 1085.0 400
7632.5 1085.0 401
7589.5 1085.0 402
7546.5 1085.0 403
7503.5 1085.0 404
7460.5 1085.0 405
7417.5 1085.0 406
7374.5 1085.0 407
7331.5 1085.0 408
SEGB7
SEGC7
SEGA8
7288.5 1085.0
7245.5 1085.0
7202.5 1085.0
7159.5 1085.0
SEGB24
SEGC24
SEGA25
SEGB25
SEGC25
SEGA26
SEGB26
SEGC26
SEGA27
SEGB27
SEGC27
SEGA28
SEGB28
SEGC28
SEGA29
SEGB29
SEGC29
SEGA30
SEGB30
SEGC30
SEGA31
SEGB31
SEGC31
SEGA32
SEGB32
SEGC32
SEGA33
SEGB33
SEGC33
SEGA34
SEGB34
SEGC34
SEGA35
SEGB35
SEGC35
SEGA36
SEGB36
SEGC36
SEGA37
SEGB37
SEGC37
SEGA38
SEGB38
SEGC38
SEGA39
SEGB39
SEGC39
SEGA40
SEGB40
SEGC40
SEGA41
5095.5
5052.5
5009.5
4966.5
4923.5
4880.5
4837.5
4794.5
4751.5
4708.5
4665.5
4622.5
4579.5
4536.5
4493.5
4450.5
4407.5
4364.5
4321.5
4278.5
4235.5
4192.5
4149.5
4106.5
4063.5
4020.5
3977.5
3934.5
3891.5
3848.5
3805.5
3762.5
3719.5
3676.5
3633.5
3590.5
3547.5
3504.5
3461.5
3418.5
3375.5
3332.5
3289.5
3246.5
3203.5
3160.5
3117.5
3074.5
3031.5
2988.5
2945.5
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
SEGB8
SEGC8
SEGA9
SEGB9
7116.5
1085.0
7073.5 1085.0
7030.5 1085.0
6987.5 1085.0
6944.5 1085.0
6901.5 1085.0
6858.5 1085.0
6815.5 1085.0
6772.5 1085.0
6729.5 1085.0
6686.5 1085.0
6643.5 1085.0
6600.5 1085.0
6557.5 1085.0
6514.5 1085.0
6471.5 1085.0
6428.5 1085.0
6385.5 1085.0
6342.5 1085.0
6299.5 1085.0
6256.5 1085.0
6213.5 1085.0
6170.5 1085.0
6127.5 1085.0
6084.5 1085.0
6041.5 1085.0
5998.5 1085.0
5955.5 1085.0
5912.5 1085.0
5869.5 1085.0
5826.5 1085.0
5783.5 1085.0
5740.5 1085.0
5697.5 1085.0
5654.5 1085.0
SEGC9
SEGA10
SEGB10
SEGC10
SEGA11
SEGB11
SEGC11
SEGA12
SEGB12
SEGC12
SEGA13
SEGB13
SEGC13
SEGA14
SEGB14
SEGC14
SEGA15
SEGB15
SEGC15
SEGA16
SEGB16
SEGC16
SEGA17
SEGB17
SEGC17
SEGA18
SEGB18
SEGC18
SEGA19
SEGB19
SEGC19
SEGA20
SEGB20
SEGC20
SEGA21
SEGB21
SEGC21
SEGA22
SEGB22
SEGC22
SEGA23
SEGB23
SEGC23
SEGA24
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
SEGSA0
SEGSB0
SEGSC0
SEGA0
SEGB0
SEGC0
SEGA1
SEGB1
SEGC1
SEGA2
SEGB2
SEGC2
SEGA2
SEGB3
SEGC3
SEGA4
SEGB4
SEGC4
SEGA5
SEGB5
SEGC5
SEGA6
SEGB6
SEGC6
SEGA7
5611.5
1085.0
5568.5 1085.0
5525.5 1085.0
5482.5 1085.0
5439.5 1085.0
5396.5 1085.0
5353.5 1085.0
5310.5 1085.0
5267.5 1085.0
5224.5 1085.0
5181.5 1085.0
5138.5 1085.0
- 7 -
NJU6823
ꢀ PAD COORDINATES 4
Chip Size 22070µm x 2550µm (Chip Center 0µm x 0µm )
PAD
PAD
No.
PAD
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
No.
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
No.
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
SEGB41
SEGC41
SEGA42
SEGB42
SEGC42
SEGA43
SEGB43
SEGC43
SEGA44
SEGB44
SEGC44
SEGA45
SEGB45
SEGC45
SEGA46
SEGB46
SEGC46
SEGA47
SEGB47
SEGC47
SEGA48
SEGB48
SEGC48
SEGA49
SEGB49
SEGC49
SEGA50
SEGB50
SEGC50
SEGA51
SEGB51
SEGC51
SEGA52
SEGB52
SEGC52
SEGA53
SEGB53
SEGC53
SEGA54
SEGB54
SEGC54
SEGA55
SEGB55
SEGC55
SEGA56
SEGB56
SEGC56
SEGA57
SEGB57
SEGC57
SEGA58
2902.5 1085.0
2859.5 1085.0
2816.5 1085.0
2773.5 1085.0
2730.5 1085.0
2687.5 1085.0
2644.5 1085.0
2601.5 1085.0
2558.5 1085.0
2515.5 1085.0
2472.5 1085.0
2429.5 1085.0
2386.5 1085.0
2343.5 1085.0
2300.5 1085.0
2257.5 1085.0
2214.5 1085.0
2171.5 1085.0
2128.5 1085.0
2085.5 1085.0
2042.5 1085.0
1999.5 1085.0
1956.5 1085.0
1913.5 1085.0
1870.5 1085.0
1827.5 1085.0
1784.5 1085.0
1741.5 1085.0
1698.5 1085.0
1655.5 1085.0
1612.5 1085.0
1569.5 1085.0
1526.5 1085.0
1483.5 1085.0
1440.5 1085.0
1397.5 1085.0
1354.5 1085.0
1311.5 1085.0
1268.5 1085.0
1225.5 1085.0
1182.5 1085.0
1139.5 1085.0
1096.5 1085.0
1053.5 1085.0
1010.5 1085.0
967.5 1085.0
924.5 1085.0
881.5 1085.0
838.5 1085.0
795.5 1085.0
752.5 1085.0
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
SEGB58
SEGC58
SEGA59
SEGB59
SEGC59
SEGA60
SEGB60
SEGC60
SEGA61
SEGB61
SEGC61
SEGA62
SEGB62
SEGC62
SEGA63
SEGB63
SEGC63
SEGA64
SEGB64
SEGC64
SEGA65
SEGB65
SEGC65
SEGA66
SEGB66
SEGC66
SEGA67
SEGB67
SEGC67
SEGA68
SEGB68
SEGC68
SEGA69
SEGB69
SEGC69
SEGA70
SEGB70
SEGC70
SEGA71
SEGB71
SEGC71
SEGA72
SEGB72
SEGC72
SEGA73
SEGB73
SEGC73
SEGA74
SEGB74
SEGC74
SEGA75
709.5
666.5
623.5
580.5
537.5
494.5
451.5
408.5
365.5
322.5
279.5
236.5
193.5
150.5
107.5
64.5
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
1085.0
SEGB75
SEGC75
SEGA76
SEGB76
SEGC76
SEGA77
SEGB77
SEGC77
SEGA78
SEGB78
SEGC78
SEGA79
SEGB79
SEGC79
SEGA80
SEGB80
SEGC80
SEGA81
SEGB81
SEGC81
SEGA82
SEGB82
SEGC82
SEGA83
SEGB83
SEGC83
SEGA84
SEGB84
SEGC84
SEGA85
SEGB85
SEGC85
SEGA86
SEGB86
SEGC86
SEGA87
SEGB87
SEGC87
SEGA88
SEGB88
SEGC88
SEGA89
SEGB89
SEGC89
SEGA90
SEGB90
SEGC90
SEGA91
SEGB91
SEGC91
SEGA92
-1483.5 1085.0
-1526.5 1085.0
-1569.5 1085.0
-1612.5 1085.0
-1655.5 1085.0
-1698.5 1085.0
-1741.5 1085.0
-1784.5 1085.0
-1827.5 1085.0
-1870.5 1085.0
-1913.5 1085.0
-1956.5 1085.0
-1999.5 1085.0
-2042.5 1085.0
-2085.5 1085.0
-2128.5 1085.0
-2171.5 1085.0
-2214.5 1085.0
-2257.5 1085.0
-2300.5 1085.0
-2343.5 1085.0
-2386.5 1085.0
-2429.5 1085.0
-2472.5 1085.0
-2515.5 1085.0
-2558.5 1085.0
-2601.5 1085.0
-2644.5 1085.0
-2687.5 1085.0
-2730.5 1085.0
-2773.5 1085.0
-2816.5 1085.0
-2859.5 1085.0
-2902.5 1085.0
-2945.5 1085.0
-2988.5 1085.0
-3031.5 1085.0
-3074.5 1085.0
-3117.5 1085.0
-3160.5 1085.0
-3203.5 1085.0
-3246.5 1085.0
-3289.5 1085.0
-3332.5 1085.0
-3375.5 1085.0
-3418.5 1085.0
-3461.5 1085.0
-3504.5 1085.0
-3547.5 1085.0
-3590.5 1085.0
-3633.5 1085.0
21.5
-21.5
-64.5
-107.5
-150.5
-193.5
-236.5
-279.5
-322.5
-365.5
-408.5
-451.5
-494.5
-537.5
-580.5
-623.5
-666.5
-709.5
-752.5
-795.5
-838.5
-881.5
-924.5
-967.5
-1010.5 1085.0
-1053.5 1085.0
-1096.5 1085.0
-1139.5 1085.0
-1182.5 1085.0
-1225.5 1085.0
-1268.5 1085.0
-1311.5 1085.0
-1354.5 1085.0
-1397.5 1085.0
-1440.5 1085.0
- 8 -
NJU6823
ꢀ PAD COORDINATES 5
Chip Size 22070µm x 2550µm (Chip Center 0µm x 0µm )
PAD
PAD
No.
PAD
Terminal
SEGB92
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
No.
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
No.
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
-3676.5 1085.0
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
SEGB109
SEGC109
SEGA110
SEGB110
SEGC110
SEGA111
SEGB111
SEGC111
SEGA112
SEGB112
SEGC112
SEGA113
SEGB113
SEGC113
SEGA114
SEGB114
SEGC114
SEGA115
SEGB115
SEGC115
SEGA116
SEGB116
SEGC116
SEGA117
SEGB117
SEGC117
SEGA118
SEGB118
SEGC118
SEGA119
SEGB119
SEGC119
SEGA120
SEGB120
SEGC120
SEGA121
SEGB121
SEGC121
SEGA122
SEGB122
SEGC122
SEGA123
SEGB123
SEGC123
SEGA124
SEGB124
SEGC124
SEGA125
SEGB125
SEGC125
SEGA126
-5869.5 1085.0
-5912.5 1085.0
-5955.5 1085.0
-5998.5 1085.0
-6041.5 1085.0
-6084.5 1085.0
-6127.5 1085.0
-6170.5 1085.0
-6213.5 1085.0
-6256.5 1085.0
-6299.5 1085.0
-6342.5 1085.0
-6385.5 1085.0
-6428.5 1085.0
-6471.5 1085.0
-6514.5 1085.0
-6557.5 1085.0
-6600.5 1085.0
-6643.5 1085.0
-6686.5 1085.0
-6729.5 1085.0
-6772.5 1085.0
-6815.5 1085.0
-6858.5 1085.0
-6901.5 1085.0
-6944.5 1085.0
-6987.5 1085.0
-7030.5 1085.0
-7073.5 1085.0
-7116.5 1085.0
-7159.5 1085.0
-7202.5 1085.0
-7245.5 1085.0
-7288.5 1085.0
-7331.5 1085.0
-7374.5 1085.0
-7417.5 1085.0
-7460.5 1085.0
-7503.5 1085.0
-7546.5 1085.0
-7589.5 1085.0
-7632.5 1085.0
-7675.5 1085.0
-7718.5 1085.0
-7761.5 1085.0
-7804.5 1085.0
-7847.5 1085.0
-7890.5 1085.0
-7933.5 1085.0
-7976.5 1085.0
-8019.5 1085.0
SEGB126
SEGC126
SEGA127
SEGB127
SEGC127
SEGSA1
SEGSB1
SEGSC1
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
COM89
COM90
COM91
COM92
COM93
COM94
COM95
COM96
COM97
COM98
COM99
COM100
COM101
COM102
COM103
COM104
COM105
COM106
-8062.5 1085.0
-8105.5 1085.0
-8148.5 1085.0
-8191.5 1085.0
-8234.5 1085.0
-8277.5 1085.0
-8320.5 1085.0
-8363.5 1085.0
-8406.5 1085.0
-8449.5 1085.0
-8492.5 1085.0
-8535.5 1085.0
-8578.5 1085.0
-8621.5 1085.0
-8664.5 1085.0
-8707.5 1085.0
-8750.5 1085.0
-8793.5 1085.0
-8836.5 1085.0
-8879.5 1085.0
-8922.5 1085.0
-8965.5 1085.0
-9008.5 1085.0
-9051.5 1085.0
-9094.5 1085.0
-9137.5 1085.0
-9180.5 1085.0
-9223.5 1085.0
-9266.5 1085.0
-9309.5 1085.0
-9352.5 1085.0
-9395.5 1085.0
-9438.5 1085.0
-9481.5 1085.0
-9524.5 1085.0
-9567.5 1085.0
-9610.5 1085.0
-9653.5 1085.0
-9696.5 1085.0
-9739.5 1085.0
-9782.5 1085.0
-9825.5 1085.0
-9868.5 1085.0
-9911.5 1085.0
-9954.5 1085.0
-9997.5 1085.0
-10040.5 1085.0
-10083.5 1085.0
-10126.5 1085.0
-10169.5 1085.0
-10212.5 1085.0
SEGC92 -3719.5 1085.0
SEGA93
SEGB93
-3762.5 1085.0
-3805.5 1085.0
SEGC93 -3848.5 1085.0
SEGA94
SEGB94
-3891.5 1085.0
-3934.5 1085.0
SEGC94 -3977.5 1085.0
SEGA95
SEGB95
-4020.5 1085.0
-4063.5 1085.0
SEGC95 -4106.5 1085.0
SEGA96
SEGB96
-4149.5 1085.0
-4192.5 1085.0
SEGC96 -4235.5 1085.0
SEGA97
SEGB97
-4278.5 1085.0
-4321.5 1085.0
SEGC97 -4364.5 1085.0
SEGA98
SEGB98
-4407.5 1085.0
-4450.5 1085.0
SEGC98 -4493.5 1085.0
SEGA99
SEGB99
-4536.5 1085.0
-4579.5 1085.0
SEGC99 -4622.5 1085.0
SEGA100 -4665.5 1085.0
SEGB100 -4708.5 1085.0
SEGC100 -4751.5 1085.0
SEGA101 -4794.5 1085.0
SEGB101 -4837.5 1085.0
SEGC101 -4880.5 1085.0
SEGA102 -4923.5 1085.0
SEGB102 -4966.5 1085.0
SEGC102 -5009.5 1085.0
SEGA103 -5052.5 1085.0
SEGB103 -5095.5 1085.0
SEGC103 -5138.5 1085.0
SEGA104 -5181.5 1085.0
SEGB104 -5224.5 1085.0
SEGC104 -5267.5 1085.0
SEGA105 -5310.5 1085.0
SEGB105 -5353.5 1085.0
SEGC105 -5396.5 1085.0
SEGA106 -5439.5 1085.0
SEGB106 -5482.5 1085.0
SEGC106 -5525.5 1085.0
SEGA107 -5568.5 1085.0
SEGB107 -5611.5 1085.0
SEGC107 -5654.5 1085.0
SEGA108 -5697.5 1085.0
SEGB108 -5740.5 1085.0
SEGC108 -5783.5 1085.0
SEGA109 -5826.5 1085.0
- 9 -
NJU6823
ꢀ PAD COORDINATES 6
Chip Size 22070µm x 2550µm (Chip Center 0µm x 0µm )
PAD
PAD
No.
817
PAD
Terminal
X(µm)
Y(µm)
Terminal
DMY71
X(µm)
Y(µm)
Terminal
X(µm)
Y(µm)
No.
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
No.
COM107 -10255.5 1085.0
COM108 -10298.5 1085.0
COM109 -10341.5 1085.0
-10845.0 -881.5
COM110
COM111
COM112
COM113
DMY41
DMY42
DMY43
DMY44
DMY45
DMY46
COM114
COM115
COM116
COM117
COM118
COM119
-10384.5 1085.0
-10427.5 1085.0
-10470.5 1085.0
-10513.5 1085.0
-10556.5 1085.0
-10599.5 1085.0
-10642.5 1085.0
-10845.0 881.5
-10845.0 838.5
-10845.0 795.5
-10845.0 752.5
-10845.0 709.5
-10845.0 666.5
-10845.0 623.5
-10845.0 580.5
-10845.0 537.5
COM120 -10845.0 494.5
COM121 -10845.0 451.5
COM122 -10845.0 408.5
COM123 -10845.0 365.5
COM124 -10845.0 322.5
COM125 -10845.0 279.5
COM126 -10845.0 236.5
COM127 -10845.0 193.5
DMY47
DMY48
DMY49
DMY50
DMY51
DMY52
DMY53
DMY54
DMY55
DMY56
DMY57
DMY58
DMY59
DMY60
DMY61
DMY62
DMY63
DMY64
DMY65
DMY66
DMY67
DMY68
DMY69
DMY70
-10845.0 150.5
-10845.0 107.5
-10845.0
-10845.0
64.5
21.5
-10845.0 -21.5
-10845.0 -64.5
-10845.0 -107.5
-10845.0 -150.5
-10845.0 -193.5
-10845.0 -236.5
-10845.0 -279.5
-10845.0 -322.5
-10845.0 -365.5
-10845.0 -408.5
-10845.0 -451.5
-10845.0 -494.5
-10845.0 -537.5
-10845.0 -580.5
-10845.0 -623.5
-10845.0 -666.5
-10845.0 -709.5
-10845.0 -752.5
-10845.0 -795.5
-10845.0 -838.5
- 10 -
NJU6823
ꢀ BLOCK DIAGRAM
VSSH
VSS
VSSA
VVDDA
VDD
Segment Driver
Common Driver
5
VLCD, V1 -V4
Gradation Circuit
Data Latch Circuit
Shift Register
V1A1, V1A2,
V4A1, V4A2
4
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
Voltage
booster
Voltage
regulator
VOUT
VEE
Display Data RAM
(DD RAM)
128x128x(4+4+4)bit
VREF
VBA
VREG
D15
Column Address Decoder
Column Address Counter
Column Address Register
D14
FR
D13
RAM
Interface
Display
Timing
Generator
FLM
CL
D12
D11
D10
D9
CLK
D8
OSC2
OSC1
Oscillator
D7
D6
D5
D4/SPOL
D3/SMODE
D2
Instruction
Decoder
Register Read
Control
Bus Holder
Pole Control
Internal Bus
D1/SDA
D0/SCL
MPU Interface
CSb RS
RDb WRb P/S
SEL68 RESb
- 11 -
NJU6823
ꢀPOWER SUPPLY CIRCUITS BLOCK DIAGRAM
Reference
+
-
-
Voltage
VBA
VLCD
Generator
-
Voltage regulator
V1
VREG
VREF
+
-
-
V2
Gain
-
V3
Control
(1x-7x)
E.V.R
1/2VREG
-
V4
EVR register
V1/V4 Bias Voltage
Adjustment
Boost level register
V1A1 V1A2 V4A1 V4A2
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
C5+
C5-
Voltage
Booster
VOUT
VEE
- 12 -
NJU6823
ꢀ TERMINAL DESCRIPTION 1
No.
Symbol
VDD
I/O
Function
64~70
83~89
154~160
8,9,
Power
Power
Power
Power
Power supply for logic circuits
VSS
GND for logic circuits
VSSH
VDDA
GND for high voltage circuits
This terminal is internally connected to the VDD level.
•This terminal is used to fix the selection terminals to the VDD
level.
28,29,
92,93,
100,101
Note) Do not use this terminal for a main power supply.
This terminal is internally connected to the VSS level.
•This terminal is used to fix the selection terminals to the VSS
level.
4,5,
VSSA
Power
12,13,
46,47,
96,97,
Note) Do not use this terminal for a main GND.
104,105
106~111
112~117
118~123
124~129
130~135
VLCD
V1
Power/O LCD driving voltages
•When the internal voltage booster is not used, external LCD
V2
driving voltages (V1 to V4 and VLCD) must be supplied onto these
terminals. The external voltages must be maintained with the
following relation.
V3
V4
VSS<V4<V3<V2<V1<VLCD
• When the internal voltage booster is used, the LCD driving
voltages (V1 to V4 and VLCD) are enabled by the “Power control”
instruction. The capacitors between the VSS and these terminals
are necessary.
175~180
181~186
187~192
193~198
199~204
205~210
211~216
217~222
223~228
229~234
148~153
142~147
168~174
C1+
C1-
O
O
O
O
O
Capacitor connection terminals for the voltage booster
C2+
C2-
Capacitor connection terminals for the voltage booster
Capacitor connection terminals for the voltage booster
Capacitor connection terminals for the voltage booster
Capacitor connection terminals for the voltage booster
C3+
C3-
C4+
C4-
C5+
C5-
VBA
VREF
VEE
O
I
Power
Output of the reference-voltage generator
Input of the voltage regulator
Input of the voltage booster
•This terminal is normally connected to the VDD level.
161~167
VOUT
Power/O Output of the voltage booster
Input for high voltage circuits in using external power supply
136~141
90,91
VREG
V1A1
V1A2
V4A1
V4A2
RESb
O
I
Output of the voltage regulator
V1 bias voltage adjustment terminal
94,95
98,99
I
I
I
V4 bias voltage adjustment terminal
102,103
14,15
Reset
Active “0”
6,7
SEL68
MPU interface type select
SEL86
Status
H
L
68 series
80 series
- 13 -
NJU6823
ꢀ TERMINAL DESCRIPTION 2
No.
Symbol
D0/SCL
I/O
I/O
Function
30,31
Parallel interface:
D7 to D0 : 8-bit bi-directional bus
•In the parallel interface mode (P/S=“1”), these terminals
connect to 8-bit bi-directional MPU bus.
32,33
36,37
D1/SDA
I/O
I/O
Serial interface:
SDA : serial data
D3/SMODE
SCL : serial clock
SMODE : 3-/4-line serial interface mode selection
SPOL : RS polarity selection (in the 3-line serial interface mode)
38,39
D4/SPOL
I/O
I/O
•In the 3-/4-line serial interface mode (P/S=“0”), the D0 terminal is
assigned to the SCL and the D1 terminal to the SDA.
•In the 3-line serial interface mode, the D4 terminal is assigned to
the SPOL.
34,35
40,41
42,43
44,45
D2
D5
D6
D7
•Serial data on the SDA is fetched at the rising edge of the SCL
signal in the order of the D7, D6…D0, and the fetched data is
converted into 8-bit parallel data at the falling edge of the 8th
SCL signal.
•The SCL signal must be set to “0” after data transmissions or
during non-access.
48,49
50,51
52,53
54,55
56,57
58,59
60,61
62,63
17,18
D8
D9
I/O
8-bit bi-directional bus
•In the 16-bit data bus mode, these terminals are assigned to the
upper 8-bit data bus.
D10
D11
D12
D13
D14
D15
•In the serial interface mode or 8-bit data bus mode of the parallel
interface, these terminals must be fixed to “1” or “0”.
I
I
Chip select
CSb
Active “0”
20,21
Resister select
RS
•This signal distinguishes transferred data as an instruction or
display data as follows.
RS
Distinct.
H
L
Instruction
Display data
26,27
23,24
I
I
80 series MPU interface (P/S=“1”, SEL68=“0”)
RDb signal. Active “0”.
RDb (E)
68 series MPU interface (P/S=“1”, SEL68=“1”)
Enable signal. Active “1”.
80 series MPU interface (P/S=“1”, SEL68=“0”)
WRb signal. Active “0”.
WRb (R/W)
68 series MPU interface (P/S=“1”, SEL68=“1”)
R/W signal.
R/W
Status
H
Read
L
Write
- 14 -
NJU6823
ꢀ TERMINAL DESCRIPTION 3
No.
10,11
Symbol
P/S
I/O
I
Function
Parallel / serial interface mode selection
Chip
Data/
Read/Writ
e
RDb, WRb
P/S
Data
Serial clock
-
Select
Instruction
H
L
CSb
RS
D0 ~ D7
CSb
RS
SDA (D1)
Write only
SCL (D0)
•Since the D15 to D5 and D2 terminals are in the high impedance in the
serial inter face mode (P/S=”0”), they must be fixed to “1” or “0”. The
RDb and WRb terminals also must be “1” or “0”.
71,72
CL
O
This terminal must be opened.
73,74
75,76
77,78
FLM
FR
O
O
O
This terminal must be opened.
This terminal must be opened.
CLK
This terminal must be opened.
79,80
OSC1
I
OSC
81,82
OSC2
O
•When the internal oscillator clock is used, OSC1 terminal must be
fixed to “1” or “0”, and the OSC2 terminal must be opened. When the
oscillation frequency from the internal oscillator is adjusted by an
external resistor between OSC1 terminal and OSC2.
•When an external oscillator is used, external clock is input to the
OSC1 terminal or an external resistor is connected between the OSC1
and OSC2 terminals.
- 15 -
NJU6823
ꢀ TERMINAL DESCRIPTION 4
No.
336~719
Symbol
I/O
O
Function
SEGA0 ~ SEGA127
,
Segment output
SEGB0 ~ SEGB127
,
SEGC0 ~ SEGC127
REV Mode
Turn-off
Turn-on
0
1
1
0
Normal
Reverse
•These terminals output LCD driving waveforms in accordance
with the combination of the FR signal and display data.
In the B/W mode
FR signal
Display data
Normal display mode
V2
VLCD
V2
V 3
VSS
V3
Reverse
mode
display
VLCD
VSS
333,720
334,721
335,722
332~283,
276~263,
723~772,
779~792
SEGSA0, SEGSA1
SEGSB0, SEGSB1
SEGSC0, SEGSC1
COM0 ~ COM127
O
O
Icon segment output terminal
•These terminals are assigned at both edge of normal segment
output terminals line for out line frame display.
Common output
•These terminals output LCD driving waveforms in accordance
with the combination of the FR signal and scanning data.
Data
H
FR
H
H
L
Output level
VSS
V1
L
H
VLCD
V4
L
L
(Terminal No. 1~3,16,19,22,25,235~262,277~282,773~778,793~817 are dummy.)
- 16 -
NJU6823
ꢀ Functional Description
(1) MPU Interface
(1-1) Selection of parallel / serial interface mode
The P/S terminal is used to select parallel or serial interface mode as shown in the following table. In the
serial interface mode, it is not possible to read out display data from the DDRAM and status from the
internal registers.
Table1
WRb
WRb
-
P/S
H
P/S mode
Parallel I/F
Serial I/F
CSb
CSb
CSb
RS
RS
RS
RDb
RDb
-
SEL68
SEL68
-
SDA
SDA
SCL
SCL
Data
D7-D0 (D15-D0)
L
-
Note 1) “ -” : Fix to “1” or “0”.
(1-2) Selection of MPU interface type
In the parallel interface mode, the SEL68 terminal is used to select 68- or 80-series MPU interface type
as shown in the following table.
Table2
WRb
R/W
WRb
SEL68
MPU type
68 series MPU
80 series MPU
CSb
CSb
CSb
RS
RS
RS
RDb
E
RDb
Data
D7-D0 (D15-D0)
D7-D0 (D15-D0)
H
L
(1-3) Data distinction
In the parallel interface mode, the combination of RS, RDb, and WRb (R/W) signals distinguishes
transferred data between the LSI and MPU as instruction or display data, as shown in the following table.
Table3
68 series
80 series
Function
RS
RDb
WRb
R/W
Read out instruction data
Write instruction data
Read out display data
Write display data
H
H
L
H
L
H
L
H
L
L
H
H
L
L
L
H
(1-4) Selection of serial interface mode
In the serial interface mode, the SMODE terminal is used to select the 3- or 4-line serial interface mode
as shown in the following table.
Table4
SMODE
Serial interface mode
H
L
3-line
4-line
- 17 -
NJU6823
(1-5) 4-line serial interface mode
In the 4-line serial interface mode, when the chip select is active (CSb=“0”), the SDA and the SCL are
enabled. When the chip select is not active (CSb=“1”), the SDA and the SCL are disabled and the internal
shift register and the counter are being initialized. The 8-bit serial data on the SDA is fetched at the rising
edge of the SCL signal (serial clock) in order of the D7, D6…D0, and the fetched data is converted into the
8-bit parallel data at the rising edge of the 8th SCL signal.
In the 4-line serial interface mode, the transferred data on the SDA is distinguished as display data or
instruction data in accordance with the condition of the RS signal.
Table5
RS
H
L
Data distinction
Instruction data
Display data
Since the serial interface operation is sensitive to external noises, the SCL should be set to “0” after data
transmissions or during non-access. To release a mal-function caused by the external noises, the chip-
selected status should be released (CSb=“1”) after each of the 8-bit data transmissions. The following
figure illustrates the interface timing for the 4-line serial interface operation.
CSb
RS
VALID
D0
SDA
D7
1
D6
2
D5
3
D4
4
D3
5
D2
D1
SCL
6
7
8
Fig1 4-line serial interface timing
(1-6) 3-line serial interface mode
In the 3-line serial interface mode, when the chip select is active (CSb=“0”), the SDA and SCL are
enabled. When the chip select is not active (CSb=“1”), the SDA and SCL are disabled and the internal shift
register and counter are being initialized. 9-bit serial data on the SDA is fetched at the rising edge of the
SCL signal in order of the RS, D7, D6…D0, and the fetched data is converted into the 9-bit parallel data at
the rising edge of the 9th SCL signal.
In the 3-line serial interface mode, data on the SDA is distinguished as display data or instruction data in
accordance with the condition of the RS bit of the SDA data and the status of the SPOL, as follows.
Table6
SPOL=L
Data distinction
SPOL=H
Data distinction
RS
L
H
RS
L
H
Display data
Instruction data
Instruction data
Display data
- 18 -
NJU6823
Since the serial interface operation is sensitive to external noises, the SCL must be set to “0” after data
transmissions or during non-access. To release a mal-function caused by the external noises, the chip-
selected status should be released (CSb=“1”) after each of 9-bit data transmissions. The following figure
illustrates the interface timing of the 3-line serial interface operation.
CSb
SDA
SCL
RS
1
D7
2
D6
D5
4
D4
5
D3
D2
D1
D0
3
6
7
8
9
Fig2 3-line serial interface timing
- 19 -
NJU6823
(2) Access to the DDRAM
When the CSb signal is ”0”, the transferred data from MPU is written into the DDRAM or instruction register
in accordance with the condition of the RS signal.
When the RS signal is “1”, the transferred data is distinguished as display data. After the “column address”
and “row address” instructions are executed, the display data can be written into the DDRAM by the “display
data write” instruction. The display data is written at the rising edge of the WRb signal in the 80 series MPU
mode, or at the falling edge of the E signal in the 68 series MPU mode.
Table6
RS
L
H
Data
Display RAM Data
Internal Command Register
In the sequence of the “display data read” operation, the transferred data from MPU is temporarily held in the
internal bus-holder, then transferred to the internal data-bus. When the “display data read” operation is
executed just after the “column address” and “row address” instructions or “display data write” instruction,
unexpected data on the bus-holder is read out at the 1st execution, then the data of designated DDRAM
address is read out from the 2nd execution. For this reason, a dummy read cycle must be executed to avoid
the unexpected 1st data read.
Display data write operation
n
n+1
n+2
n+3
n+4
D0 to D15
WRb
n
n+1
n+2
n+3
n+4
Bus Holder
WRb
Display data read operation
WRb
D0 to D7(D0 to D15)
n
n
n+1
Data Read
n+1 Address n+2 Address
n+2
Data Read
Address Set
n
Dummy
Read
Data Read
n Address
RDb
Fig3
Note) In the16-bit data bus mode, instruction data must be 16-bit as well as the display data.
- 20 -
NJU6823
(3) Access to the instruction register
Each instruction resisters is assigned to each address between 0H and FH, and the content of the instruction
register can be read out by the combination of the “Instruction resister address” and ”Instruction resister read”.
WRb
M
m
N
n
D0 to D7
RDb
Instruction resister
Instruction resister Instruction resister Instruction resister
address set
contents read
address set
contents read
Fig4
(4) 8-/16-bit data bus length for display data (in the parallel interface mode)
The 8- or 16-bit data bus length for display data is determined by the “WLS” of the “Data bus length”
instruction.
In the 16-bit data bus mode, instruction data must be 16-bit data (D15 to D0) as well as display data. However,
for the access to the instruction register, the only lower 8-bit data (D7 to D0) of the 16-bit data is valid. For the
access to the DDRAM, all of the 16-bit data (D15 to D0) is valid.
Table8
WLS
L
H
Data bus length mode
8-bit
16-bit
(5) Initial display line register
The initial display line resister specifies the line address, corresponding to the initial COM line, by the “Initial
display line” instruction. The initial COM line signifies the common driver, starting scanning the display data in
the DDRAM, and specified by the “Initial COM line” instruction.
The line address, established in the initial display line resister, is preset into the line counter whenever the
FLM signal becomes “1”. At the rising edge of the CL signal, the line counter is counted-up and addressed 384-
bit display data corresponding to the counted-up line address, is latched into the data latch circuit. At the falling
edge of the CL signal, the latched data outputs to the segment drivers.
- 21 -
NJU6823
(6) DDRAM mapping
The DDRAM is capable of 1,536-bit (12-bit x 128-segment) for the column address and 128-bit for the row
address.
In the gradation mode, each pixel for RGB corresponds to successive 3-segment drivers, and each segment
driver has 16-gradation. Therefore, the LSI can drive up to 128x128 pixels in 4096-color display (16-gradation x
16-gradation x 16-gradation).
ꢁ In the 8-bit data bus length mode
column-address
0H
1H
5bit
FEH
7bit
FFH
5bit
0 H
7bit
row-address
7FH
0 H
7bit
5bit
7bit
5bit
column-address
column-address
column-address
0H
4bit
1H
8bit
FEH
4bit
FFH
8bit
ABS=’1’
row-address
7FH
0 H
4bit
8bit
4bit
8bit
0H
8bit
1H
8bit
BEH
8bit
BFH
8bit
HSW=’1’
row-address
7FH
0 H
8bit
8bit
8bit
8bit
0H
8bit
1H
8bit
7EH
8bit
7FH
8bit
C256=’1’
row-address
7FH
8bit
8bit
8bit
8bit
Fig5
- 22 -
NJU6823
ꢁ In the 16-bit data bus length mode
column-address
0H
7FH
12bit
0 H
12bit
row-address
7FH
12bit
12bit
Fig6
In the B&W mode, only MSB data from each 4-bit display data group in the DDRAM is used. Therefore, 384 x
128 pixels in the B&W and 128 x 128 pixels in the 8-gradation are available.
The range of the column address varies depending on data bus length. The range between 00H and FFH is
used in the 8-bit data bus length and the range between 00H and 7FH is in the 16-bit data bus length.
The increments for the column address and row address are set to the auto-increment mode by
programming the “AXI” and “AYI” registers of the “Increment control” instruction. In this mode, the contents of
the column address and row address counters automatically increment whenever the DDRAM is accessed.
The column address and row address counters, independent of the line counter. They are used to designate
the column and row addresses for the display data transferred from MPU. On the other hand, the line counter is
used to generate the line address, and output display data to the segment drivers, being synchronized with the
display control timing of the FLM and CL signals.
- 23 -
NJU6823
REF
SWAP
WLS
ABS
HSW
REF
256
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
WLS
ABS
HSW
REF
256
A3
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
- 24 -
NJU6823
REF
SWAP
WLS
ABS
HSW
REF
256
WLS
ABS
HSW
REF
256
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
A3
A2
A1
A0
B3
B2
B1
B0
C3
C2
C1
C0
- 25 -
NJU6823
(7) Window addressing mode
In addition to the above usual DDRAM addressing, it is possible to access some part of DDRAM in using the
window addressing mode, in which the start and end points are designated. The start point is determined by the
“column address” and “row address” instructions, and the end point is determined by the “Window end column
address” and “Window end row address” instructions, The setting example of the window addressing is listed,
as follows.
1. Set WIN=1, AXI=1 and AYI=1 by the “Increment control” instruction
2. Set the start point by the “column address” and “row address” instructions
3. Set the end point by the “Window end column address” and “Window end row address” instructions
4. Enable to access to the DDRAM in the window addressing mode
In the window addressing mode (WIN=1, AXI=1, AYI=1), the read-modify-write operation is available by
setting “0” to the “AIM” register of the ”Increment control” instruction.
And in the window addressing mode, the following start and end point must be maintained to abide a
malfunction.
AX (column address of start point) < EX (column address of end point) < Maximum of column address
AY (row address of start point) < EY (row address of end point) < Maximum of row address
column address
(X, Y)
Start point
End point
Window display area
(X, Y)
Whole DDRAM area
Fig7
(8) Reverse display ON/OFF
The “Reverse display ON/OFF” function is used to reverse the display data without changing the contents of
the DDRAM.
Table9
REV
Display
Normal
DDRAM data → Display data
0
1
0
1
0
1
1
0
0
1
Reverse
(9) Segment direction
The “Segment direction” function is used to reverse the assignment for the segment drivers and column
address, and it is possible to reduce the restrictions for the placement of the LSI on the LCD modules.
- 26 -
NJU6823
(10)The relationship among the DDRAM column address, display data and segment drivers
In the color mode, and 16-bit data bus mode
HSW ABS REF SWAP
Column address / bit / segment assign
*
*
0
0
0
1
0
1
X=00H
X=7FH
ꢂꢃ
ꢂꢃ
X=7FH
X=00H
ꢂꢃ
ꢂꢃ
ꢂꢃ
HSW ABS REF SWAP
Column address / bit / segment assign
*
*
0
0
0
1
1
0
X=00H
X=7FH
ꢂꢃ
ꢂꢃ
X=7FH
X=00H
ꢂꢃ
ꢂꢃ
ꢂꢃ
HSW ABS REF SWAP
Column address / bit / segment assign
*
*
1
1
0
1
0
1
X=00H
X=7FH
ꢂꢃ
ꢂꢃ
X=7FH
X=00H
ꢂꢃ
ꢂꢃ
ꢂꢃ
HSW ABS REF SWAP
Column address / bit / segment assign
*
*
1
1
0
1
1
0
X=00H
X=7FH
ꢂꢃ
ꢂꢃ
X=7FH
X=00H
ꢂꢃ
ꢂꢃ
ꢂꢃ
- 27 -
NJU6823
In the color mode, and 8-bit data bus mode
HSW ABS REF SWAP
Column address / bit / segment assign
0
0
0
0
0
1
0
1
X=00H
X=FEH
X=01H
X=FFH
ꢂꢃ
ꢂꢃ
X=FEH
X=00H
X=FFH
X=01H
ꢂꢃ
ꢂꢃ
ꢂꢃ
HSW ABS REF SWAP
Column address / bit / segment assign
0
0
0
0
0
1
1
0
X=00H
X=FEH
X=01H
X=FFH
ꢂꢃ
ꢂꢃ
X=FEH
X=00H
X=FFH
X=01H
ꢂꢃ
ꢂꢃ
ꢂꢃ
HSW ABS REF SWAP
Column address / bit / segment assign
0
0
1
1
0
1
0
1
X=00H
X=01H
X=FFH
ꢂꢃ
ꢂꢃ
X=FEH
X=00H
X=FFH
X=FEH
X=01H
ꢂꢃ
ꢂꢃ
ꢂꢃ
HSW ABS REF SWAP
Column address / bit / segment assign
0
0
1
1
0
1
1
0
X=00H
X=FEH
X=01H
X=FFH
ꢂꢃ
ꢂꢃ
X=FEH
X=00H
X=FFH
X=01H
ꢂꢃ
ꢂꢃ
ꢂꢃ
- 28 -
NJU6823
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
SEGA
0
SEGC
0
SEGC
0
SEGA
0
Palette A
Palette B
Palette C
Palette A
Palette B
Palette C
Palette A
Palette B
Palette C
Palette A
Palette B
Palette C
Palette A
Palette B
Palette C
Palette A
Palette B
Palette C
Palette A
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SEGB
0
SEGB
0
SEGB
0
SEGB
0
Palette B
Palette C
Palette A
Palette B
Palette C
SEGC
0
SEGA
0
SEGA
0
SEGC
0
SEGA
1
SEGC
1
SEGC
1
SEGA
1
SEGB
1
SEGB
1
SEGB
1
SEGB
1
SEGC
1
SEGA
1
SEGA
1
SEGC
1
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SEGA
126
SEGC
126
SEGC
126
SEGA
126
Palette A
Palette B
Palette C
Palette A
Palette B
Palette C
Palette A
Palette B
Palette C
Palette A
Palette B
Palette C
Palette A
Palette B
Palette C
Palette A
Palette B
Palette C
Palette A
Palette B
Palette C
Palette A
Palette B
Palette C
SEGB
126
SEGB
126
SEGB
126
SEGB
126
SEGC
126
SEGA
126
SEGA
126
SEGC
126
SEGA
127
SEGC
127
SEGC
127
SEGA
127
SEGB
127
SEGB
127
SEGB
127
SEGB
127
SEGC
127
SEGA
127
SEGA
127
SEGC
127
- 29 -
NJU6823
In the color mode, 8-bit data bus mode, and C256 mode (C256=1)
HSW ABS REF SWAP
Column address / bit / segment assign
*
*
*
*
0
1
0
1
X=00H
X=7FH
ꢂꢃ
ꢂꢃ
X=7FH
X=00H
ꢂꢃ
ꢂꢃ
ꢂꢃ
HSW ABS REF SWAP
Column address / bit / segment assign
*
*
*
*
0
1
1
0
X=00H
X=7FH
ꢂꢃ
ꢂꢃ
X=7FH
X=00H
ꢂꢃ
ꢂꢃ
ꢂꢃ
- 30 -
NJU6823
In the B&W mode, and 16-bit data bus mode
HSW ABS REF SWAP
Column address / bit / segment assign
*
*
0
0
0
1
0
1
X=00H
X=7FH
ꢂꢃ
ꢂꢃ
X=7FH
X=00H
ꢂꢃ
ꢂꢃ
HSW ABS REF SWAP
Column address / bit / segment assign
*
*
0
0
0
1
1
0
X=00H
X=7FH
ꢂꢃ
ꢂꢃ
X=7FH
X=00H
ꢂꢃ
ꢂꢃ
HSW ABS REF SWAP
Column address / bit / segment assign
*
*
1
1
0
1
0
1
X=00H
X=7FH
ꢂꢃ
ꢂꢃ
X=7FH
X=00H
ꢂꢃ
ꢂꢃ
HSW ABS REF SWAP
Column address / bit / segment assign
*
*
1
1
0
1
1
0
X=00H
X=7FH
ꢂꢃ
ꢂꢃ
X=7FH
X=00H
ꢂꢃ
ꢂꢃ
- 31 -
NJU6823
In the B&W mode, and 8-bit data bus mode
HSW ABS REF SWAP
Column address / bit / segment assign
0
0
0
0
0
1
0
1
X=00H
X=FEH
X=01H
X=FFH
ꢂꢃ
ꢂꢃ
X=FEH
X=00H
X=FFH
X=01H
ꢂꢃ
ꢂꢃ
HSW ABS REF SWAP
Column address / bit / segment assign
0
0
0
0
1
1
0
X=00H
X=FEH
X=01H
X=FFH
ꢂꢃ
ꢂꢃ
X=FEH
X=00H
X=FFH
X=01H
0
ꢂꢃ
ꢂꢃ
HSW ABS REF SWAP
Column address / bit / segment assign
0
0
1
1
0
1
0
1
X=00H
X=01H
X=FFH
ꢂꢃ
ꢂꢃ
X=FEH
X=00H
X=FFH
X=FEH
X=01H
ꢂꢃ
ꢂꢃ
HSW ABS REF SWAP
Column address / bit / segment assign
0
0
1
1
0
1
1
0
X=00H
X=FEH
X=01H
X=FFH
ꢂꢃ
ꢂꢃ
X=FEH
X=00H
X=FFH
X=01H
ꢂꢃ
ꢂꢃ
- 32 -
NJU6823
SEGA 0
SEGB 0
SEGC 0
SEGA 1
SEGB 1
SEGC 1
SEGC 0
SEGB 0
SEGA 0
SEGC 1
SEGB 1
SEGA 1
SEGC 0
SEGB 0
SEGA 0
SEGC 1
SEGB 1
SEGA 1
SEGA 0
SEGB 0
SEGC 0
SEGA 1
SEGB 1
SEGC 1
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SEGA 126
SEGB 126
SEGC 126
SEGA 127
SEGB 127
SEGC 127
SEGC 126
SEGB 126
SEGA 126
SEGC 127
SEGB 127
SEGA 127
SEGC 126
SEGB 126
SEGA 126
SEGC 127
SEGB 127
SEGA 127
SEGA 126
SEGB 126
SEGC 126
SEGA 127
SEGB 127
SEGC 127
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
- 33 -
NJU6823
Bit assignments between write and read data (in the 16-bit data bus mode)
ABS=0
Write data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
*
D5
*
D4
D4
D3
D3
D2
D2
D1
D1
D0
*
Read data
D15
D14
D13
D12
*
D10
D9
D8
D7
ABS=1
Write data
D15
D14
D13
D12
D11
D11
D10
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Read data
*
*
*
*
Examples of write and read data (In the 8 bit bus mode)
ABS=0, HSW=0, C256=0 (Address; 00, 02……FC,FEH)
Write data
D7
D6
D5
D4
D3
D2
D1
D0
D0
Read data
D7
D6
D5
D4
1
D2
D1
ABS=0, HSW=0, C256=0 (Address; 01,03……FD,FFH)
Write data
D7
D6
D5
D4
D3
D2
D1
D1
D0
1
Read data
D7
1
1
D4
D3
D2
ABS=1, HSW=0, C256=0 (Address; 00, 02……FC,FEH)
Write data
D7
D6
D5
D4
D3
D2
D1
D0
D0
Read data
1
1
1
1
D3
D2
D1
ABS=1, HSW=0, C256=0 (Address; 01,03……FD,FFH)
Write data
D7
D6
D5
D4
D3
D2
D1
D1
D0
D0
Read data
D7
D6
D5
D4
D3
D2
ABS=0, HSW=1, C256=0 (Address; 00, 01……BE,BFH)
Write data
D7
D6
D5
D4
D3
D2
D1
D0
D0
Read data
D7
D6
D5
D4
D3
D2
D1
ABS=0, HSW=0, C256=1 (Address; 00, 01…… 7E ,7FH)
Write data
D7
D6
D5
D4
D3
D2
D1
D0
D0
Read data
D7
D6
D5
D4
D3
D2
D1
*:Invalid Data
- 34 -
NJU6823
Icon segment register address bit assignment
In the color mode, and 16-bit data bus mode
REF
SWAP
Column address / bit segment assign
0
1
0
1
X=00H
X=01H
X=01H
X=00H
REF
SWAP
Column address / bit segment assign
0
1
1
0
X=00H
X=01H
X=01H
X=00H
In the color mode, and 8-bit data bus mode
REF
SWAP
Column address / bit segment assign
0
1
0
1
X=00H
X=03H
X=01H
X=02H
X=02H
X=01H
X=03H
X=00H
REF
SWAP
Column address / bit segment assign
0
1
1
0
X=00H
X=03H
X=01H
X=02H
X=02H
X=01H
X=03H
X=00H
- 35 -
NJU6823
In the B/W mode, and 16-bit data bus mode
REF
SWAP
Column address / bit segment assign
0
1
0
X=00H
X=01H
X=01H
X=00H
1
REF
SWAP
Column address / bit segment assign
0
1
1
0
X=00H
X=01H
X=01H
X=00H
In the B/W mode, and 8-bit data bus mode
REF
SWAP
Column address / bit segment assign
0
1
0
1
X=00H
X=03H
X=01H
X=02H
X=02H
X=01H
X=03H
X=00H
REF
SWAP
Column address / bit segment assign
0
1
1
0
X=00H
X=03H
X=01H
X=02H
X=02H
X=01H
X=03H
X=00H
- 36 -
NJU6823
(11)Gradation palette
In the gradation mode, either variable or fixed gradation mode is selected by programming the “PWM”
register of the “Gradation control” instruction.
PWM=0:
Variable gradation mode
(Select 16 gradation levels out of 32-gradation level of the gradation palette)
PWM=1:
Fixed gradation mode
(Fixed 8-gradation levels)
In these modes, each of the gradation palettes Aj, Bj and Cj can select 16-gradation level out of 32-gradation
level by setting 5-bit data to the “PA” registers in the “Gradation palette j” instructions (j=0 to Fh).
For instance, the gradation palettes Aj correspond to the SEGAi, the Bj to SEGBi and the Cj to SEGCi (j=0 to
15, i=0 to 127).
- 37 -
NJU6823
Correspondence between display data and gradation palettes
Table 10 (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))
(MSB) Display data (LSB)
Gradation palette
Palette 0
Palette 1
Palette 2
Palette 3
Palette 4
Palette 5
Palette 6
Palette 7
Palette 8
Palette 9
Palette10
Palette11
Palette12
Palette13
Palette14
Palette15
Default palette value
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Gradation palette table (Variable gradation mode, PWM=”0”, MON=”0”)
Table 11 (Palette Aj, Palette Bj, Palette Cj (j=0 to 15))
Palette
Gradation
level
Palette value
Gradation level
Gradation palette
Gradation palette
value
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
0
Palette 0(default)
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
1 0 1 0 0
1 0 1 0 1
1 0 1 1 0
1 0 1 1 1
1 1 0 0 0
1 1 0 0 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 0 1
1 1 1 1 0
1 1 1 1 1
16/31
17/31
18/31
19/31
20/31
21/31
22/31
23/31
24/31
25/31
26/31
27/31
28/31
29/31
30/31
31/31
1/31
2/31
3/31
4/31
5/31
6/31
7/31
8/31
9/31
10/31
11/31
12/31
13/31
14/31
15/31
Palette 0(default)8
Palette 9(default)
Palette 10(default)
Palette 11(default)
Palette 12(default)
Palette 13(default)
Palette 14(default)
Palette 15(default)
Palette 1(default)
Palette 2(default)
Palette 3(default)
Palette 4(default)
Palette 5(default)
Palette 6(default)
Palette 7(default)
- 38 -
NJU6823
Gradation palette table (Fixed gradation mode, PWM=”1”, MON=”0”)
Table 12 8-gradation segment drivers
(MSB) Display data (LSB)
Gradation
level
(MSB) Display data (LSB)
Gradation level
0/7
0
0
*
*
0
0
0
*
0/7
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
*
*
*
*
*
*
*
1/7
2/7
3/7
4/7
5/7
6/7
7/7
0
0
0
1
1
1
1
0
1
1
0
0
1
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
3/7
5/7
7/7
Correspondence between display data and gradation level (B&W mode, MON=”1”)
Table 13
Gradation
(MSB) Display data (LSB)
level
0
1
*
*
*
*
*
*
0
1
*:Don’t care
- 39 -
NJU6823
(12)Gradation control and display data
(12-1) Gradation mode
In the graduation mode, each pixel for RGB corresponds to successive 3 segment drivers, and each
segment driver provides 16-gradation PWM output by controlling 4 bit display data of the DDRAM.
Accordingly, the LSI can drive up to 128x128 pixels in 4096-color (16-gradation x 16-gradation x 16-
gradation = 4-bit x 4-bit x 4-bit).
In addition, the LSI can transfer the display data for the RGB by 16-bit at once or 8-bit two-times. The
data assignment between gradation palettes and segment drivers varies in accordance with setting for the
“SWAP” and “REF” registers of the "Display control (2)" instruction.
(REF, SWAP)=(0, 0) or (1, 1)
SEGAi
SEGBi
SEGCi
(i=0 to 127)
Gradation palette
j=0 to 15
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
0
0
0
0
0
0
0
1
1
1
1
1
MSB
LSB MSB
LSB MSB
LSB
Display data from MPU
Column address:2nH:2n+1H
0
D7
(DD
(D7 D
(DD
0
D6
0
0
D4
D
D4
*
0
0
0
1
D7
D
D
*
1
1
1
D2
D
D
*
1
D5
D
D
D
D2
D
D
D
D1
D
D2
D
D0
D
D1
D
D4
D
D7
D
D3
D
D
D
D1
D
D4
ABS=1
HSW=1
C256=1
Note) DDRAM column address
:2nH ,2nH+1H
:FEH -2nH , FFH-(2nH+1H)
(REF=”0”)
(REF=”1”)
HSW=1; 00H to BFH, C256=1; 00H to 7FH
- 40 -
NJU6823
(REF, SWAP)=(0, 1) or (1, 0)
SEGAi
SEGBi
SEGCi
(i=0 to 127)
Gradation palette
j=0 to 15
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
1
LSB
1
1
0
1
1
0
0
0
0
0
0
0
1
0
1
0
MSB
MSB LSB
MSB LSB
Display data from MPU
0
0
0
0
1
1
1
D
D
D
D1
D5
D
D0
D4
D
D7
D3
D
D6
D2
D
D5
D1
D
D4
D0
D
D3
D7
D
D2
D6
D
D1
D5
D
Column address:2nH:2n+1H
ABS=1
HSW=1
(D3 D2
D0
(D7 D6
(D7 D
D4
C256=1
D
*
D4
D
D2
*
D1
D
*
Note) DDRAM column address
: 2nH ,2nH+1H
: FEH -2nH , FFH-(2nH+1H)
(REF=”0”)
(REF=”1”)
HSW=1; 00H to BFH, C256=; 00H to 7FH
In the 16-bit data bus mode, the data assignments between the gradation palettes and the segment
drivers vary in accordance with setting for the “SWAP” and “REF” bit of the "Display control (2)" instruction
as well as the assignment in the 8-bit data bus mode.
(REF, SWAP)=(0, 0) or (1, 1)
SEGAi
SEGBi
SEGCi
(i=0 to 127)
Gradation palette
j=0 to 15
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
0
MSB
0
0
0
0
0
0
0
0
0
1
1
1
1
1
LSB
LSB MSB
LSB MSB
Display data from MPU
0
0
0
0
1
1
1
1
1
D15 D14 D13 D12 D10 D9
(DDDDDD
Note) DDRAM column address :nH
D8
D7
D4
D3
D2
D1
Column address; nH
D
D
D
D
D
D
ABS=1
(REF=”0”)
:7FH - nH(REF=”1”)
- 41 -
NJU6823
(REF, SWAP)=(0, 1) or (1, 0)
SEGAi
SEGBi
SEGCi
i=0 to 127
Gradation palette
j=0 to 15
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
1
LSB
1
0
1
0
1
1
0
0
0
0
0
0
0
1
0
1
0
MSB
MSB LSB
MSB LSB
Display data from MPU
0
0
0
1
1
1
DD14 DD12 DD
D
D5
D7
D4
D4
D3
D
D2
D2
D1
D1
D0
Column address ; nH
(D11 D10 D9
D8
D7
D6
ABS=1
Note) DDRAM column address
:nH
(REF=”0”)
:7FH -nH (REF=”1”)
- 42 -
NJU6823
(12-2) B&W mode (MON=”1”)
In the B&W mode, 3 bits of the MSB data are used in both of the 16-bit and 8-bit data bus modes.
In the 16-bit data bus mode (Similarly 8-bit data bus access)
(REF, SWAP)=(0, 0) or (1, 1)
SEGAi
SEGBi
SEGCi
(i=0 to 127)
Gradation palette
j=0 to 15
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
0
MSB
0
0
0
0
0
0
0
0
0
1
1
1
1
1
LSB
LSB MSB
LSB MSB
Display data in DDRAM
0
0
0
0
1
1
1
1
1
D15 D14 D13 D12 D10 D9
(D11 D10 D9 D8 D7 D6
: nH
D8
D5
D7
D4
D4
D3
D3
D2
D2
D1
D1
D0
Column address; nH
ABS=1
Note) DDRAM column address
(REF=”0”)
(REF=”1”)
: 7FH-nH
(REF, SWAP)=(0, 1) or (1, 0)
SEGAi
SEGBi
SEGCi
(i=0 to 127)
Gradation palette
j=0 to 15
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
1
LSB
1
0
1
0
1
1
0
0
0
0
0
0
0
1
0
1
0
MSB
MSB LSB
MSB LSB
Display data in DDRAM
0
0
0
1
1
1
D15 D14 D13 D12 D10 D9
(D11 DDDD7 D
D8
D
D7
D4
D4
D
D3
D2
D2
D1
D1
D
Column address; nH
ABS=1
Note ) DDRAM column address
: nH
: 7FH-nH
(REF=”0”)
(REF=”1”)
The correlation of display data with gradation control is also applied to Icon segment.
- 43 -
NJU6823
(13)Display timing generator
The display-timing generator creates the timing pulses such as the CL, the FLM, the FR and the CLK by
dividing the oscillation frequency oscillate an external or internal resister mode. The each of timing pulses is
outputted through the each output terminals by “SON”=1.
(14)LCD line clock (CL)
The LCD line clock (CL) is used as a count-up signal for the line counter and a latch signal for the data latch
circuit. At the rising edge of the CL signal, the line counter is counted-up and the 384-bit display data,
corresponding to this line address, is latched into the data latch circuit. And at the falling edge of the CL signal,
this latched data output on the segment drivers. Read out timing of the display data, from DDRAM to the latch
circuits is completely independent of the access timing to the MPU. For this reason, the MPU can access to the
LSI regardless of an internal operation.
(15)LCD alternate signal (FR) and LCD synchronous signal (FLM)
The FR and FLM signals are created from the CL signal. The FR signal is used to alternate the crystal
polarization on a LCD panel. It is programmed that the FR signal is toggle on every frame in the default setting
or once every N lines in the N-line inversion mode. The FLM signal is used to indicate a start line of a new
display frame. It presets an initial display line address of the line counter when the FLM signal becomes ”1”.
(16) Data latch circuit
The data latch circuit is used temporarily store the display data that will output to the segment drivers. The
display data in this circuit is updated in synchronization of the CL signal.
The “All pixels ON/OFF”, “Display ON/OFF” and “Reverse display ON/OFF” instructions change the display
data in this circuit but do not change the display data of the DDRAM.
(17)Common and segment drivers
The LSI includes 384+6-segment drivers and 128-common drivers. The common drivers generate the LCD
driving waveforms composed of the VLCD, V1, V4 and VSS in accordance with the FR signal and scanning data.
The segment drivers generate waveforms composed of the VLCD, V2, V3 and VSS in accordance with the FR
signal and display data.
- 44 -
NJU6823
LCD Driving waveforms (In the B&W mode, Reverse display OFF, 1/129 duty)
COM0
1
2
3
4
5
1
2
3
4
5
1
129
129
129
COM1
CL
FLM
FR
VLCD
V1
V2
COM0
V3
V4
VSS
VLCD
V1
V2
COM1
SEG0
V3
V4
VSS
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
SEG1
V2
V3
V4
VSS
Fig 8
- 45 -
NJU6823
(18)Icon Segment Driver Circuit
Each 3 outputs (SEGSA0 to SEGSA1, SEGSB0 to SEGSB1, SEGSC0 to SEGSC1) placed at both edges of
normal segment output terminals line are Segment outputs for Icon. Although normal Segment output generates
the LCD driving voltage corresponding with the data in Display Data RAM, Icon segment driver provides the
register instead of the display data RAM. The data corresponding to SEGSA0, SEGSB0 and SEGSC0 are in 12-
bit register and output the same driving voltage on the row direction. (The data corresponding to SEGSA1,
SEGSB1 and SEGSC1 are same as SEGSA0, SEGSB0 and SEGSC0.)
The outputs of SEGSA0 to SEGSA1 assign the same gradation pallet as SEGA0 to SEGA127, SEGSB0 to
SEGSB1 are SEGB0 to SEGB127 and SEGSC0 to SEGSC1 are SEGC0 to SEGC127.
Icon Segment Driver Circuit operates for the outline frame display or background. These displays are
changed in accordance with attribute of ALLON or REV command, but no change by LREV command.
The capacity of register corresponding with Icon segment driver (SEGSA0 to SEGSA1, SEGSB0 to SEGSB1,
SEGSC0 to SEGSC1) is 24 bits. The access to from this register performed at DMY="1"..
Table14
80 type
68type
RS
DMY
Function
R/W
H
RDb
WRb
L
L
L
L
0
0
1
1
L
H
L
H
L
Display data read
L
Display data write
H
H
L
Icon segment register read
Icon segment register read
L
H
Read out function from the Icon segment register is restricted as same as the display data read out function
from Display Data RAM. After address set, the addressed data does not come out by the first read instruction
immediately but comes out by the second read instruction. Therefore, one dummy read out function is required
for data read from Icon segment register after the address set or the data write operation.
When the Icon segment registers are accessed in DMY="1", the valid addressing is just a column address.
Because of 24 bits Icon register, the valid addresses are "00h", "01h", "02h" and "03h" in 8-bit mode, and "00h"
and "01h" in 16-bit mode.
When the Icon segment registers are accessed in DMY="1", the data write operation into Icon register is
enabled with the increment operation.
the column addressing operates in accordance with the status of REF (Segment output order setting
register) register and the column address increment operates as shown below. But the auto carry up operation
like as the maximum address to "00h" does not operate of the display data RAM access.
00h -> Max.
8-bit data bus mode (DMY=”1”)
Column address
00H, 01H: SEGSA0, SEGSB0, SEGSC0
02H, 03H: SEGSA1, SEGSB1, SEGSC1
16-bit data bus mode (DMY=”1”)
Column address
00H:
01H:
SEGSA0, SEGSB0, SEGSC0
SEGSA1, SEGSB1, SEGSC1
Note) Refer the “Icon segment register address bit assignment” in (10) The relationship among the DDRAM
column address, display data and segment drivers. Both of Icon segment register and Display data RAM
operate a same address counter so that the address is set again in the status transition of DMY = "0" to "1"
or "1" to "0".
- 46 -
NJU6823
Examples for the dummy segment registers (DMY=”1”)
(In the 16-bit data bus mode, gradation mode, (REF,SWAP)=(0,0))
Column address: 00H
SEGSA0
SEGSB0
SEGSC0
Gradation palette
Palette Aj
Palette Bj
Palette Cj
j=0 to 15
Gradation control circuit
Display data in DDRAM
Display data in DDRAM
0
MSB
0
0
0
0
0
0
0
0
0
1
1
1
1
1
LSB
LSB MSB
LSB MSB
0
0
0
0
1
1
1
1
1
D15 D14 D13 D12 D10 D9
D8
D7
D4
D3
D2
D1
(D11 D10 D9 D8 D7 D6
D5
D4
D3
D2
D1
D0)
ABS=1
Column address: 01H
SEGSA1
SEGSB1
SEGSC1
Gradation palette
j=0 to 15
Palette Aj
Palette Bj
Palette Cj
Gradation control circuit
Display data in DDRAM
0
MSB
0
0
0
0
0
0
0
0
0
1
1
1
1
1
LSB
LSB MSB
LSB MSB
Display data in DDRAM
0
0
0
0
1
1
1
1
1
D15 D14 D13 D12 D10 D9
D8
D7
D4
D3
D2
D1
(D11 DDDD7 D
D
D4
D
D2
D1
D
ABS=1
- 47 -
NJU6823
(19)Oscillator
The oscillator generates internal clocks for the display timing and the voltage booster. Since the LSI has internal
capacitor (C) and resistor (R) for the oscillation, external capacitor and resistor are not usually required. However,
in case that an external resistor is used, the resister is connected between the OSC1 and OSC2 terminals. The
external resistor becomes enabled by setting “1” to the “CKS” register of “Data bus length” instruction. When the
internal oscillator is not used, the external clocks with 50% duty cycle ratio must be input to the OSC1 terminal.
In addition, the feed back resister for the oscillation is varied by programming the “Rf” register of the “Frequency
control” instruction, so that it is possible to optimize the frame frequency for a LCD panel. Setting examples of the
MON (B&W /Gradation) and the PWM (Variable gradation /Fixed gradation) are described, as follows.
Internal oscillation mode (CKS=0)
Symbol
MON PWM
Display mode
f1
f2
f3
0
0
1
0
1
*
Variable gradation mode
Fixed gradation mode
B&W mode
*: Don’t care
External resistor oscillation mode(CKS=1)
The internal clocks must be adjusted to the same frequency as the one in using the internal oscillation
mode, and the “MON” and “PWM” registers must be set as well.
External clock input mode(CKS=1)
The external clocks must be adjusted to the same frequency as the one in using the internal oscillation
mode, and the “MON” and “PWM” registers must be set as well.
(20)Power supply circuits
The internal power supply circuits are composed of the voltage booster, the electrical variable resister (EVR),
the voltage regulator, reference voltage generator and the voltage followers.
The condition of the power supply circuits is arranged by programming the “DCON” and “AMPON” registers
on the “Power control” instruction. For this arrangement, some parts of the internal power supply circuits are
activated in using an external power supply, as shown in the following table.
Table 15
Voltage followers
DCON
AMPON
Voltage booster
Voltage regulator
External voltage
Note
EVR
0
0
1
0
1
1
Disable
Disable
Enable
Disable
Enable
Enable
1, 3
2, 3
−
V
OUT, VLCD, V1, V2, V3, V4
VOUT
−
Note1) The internal power circuits are not used. The external VOUT is required and the C1+, C1-, C2+, C2-, C3+,
C3-, C4+, C4-, C5+, C5-, VREF, VREG and VEE terminals must be open.
Note2) The internal power circuits except the voltage booster are used. The external VOUT is required and the
C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5- and VEE terminals must be open. The reference voltage is
required to VREF terminal.
Note3) The relation among the voltages should be maintained as follows.
VOUT ≥ VLCD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
- 48 -
NJU6823
(21)Voltage booster
The voltage booster generates maximum 6x voltage of the VEE level. It is programmed so that the boost level
is selected out of 1x, 2x, 3x, 4x, 5x and 6x by the “Boost level select” instruction. The boosted voltage VOUT
must not exceed beyond the value of 18.0V, otherwise the voltage stress may cause a permanent damage to
the LSI.
Boosted voltages
VOUT=18V
VOUT=9V
VEE=3V
VSS=0V
VEE=3V
VSS=0V
6-time boost
3-time boost
Capacitor connections for the voltage Booster
6-time boost
5-time boost
C1+
C1-
C1+
+
+
+
+
+
+
+
+
+
+
C1-
C2+
C2-
C2+
C2-
C3+
C3-
C3+
C3-
C4+
C4-
C4+
C4-
C5+
C5-
C5+
C5-
VOUT
VSS
VOUT
VSS
+
4-time boost
3-time boost
2-time boost
C1+
C1-
C1+
C1-
C1+
C1-
+
+
+
+
+
+
+
C2+
C2-
C2+
C2-
C2+
C2-
C3+
C3-
C3+
C3-
C3+
C3-
C4+
C4-
C4+
C4-
C4+
C4-
C5+
C5-
C5+
C5-
C5+
C5-
VOUT
VSS
VOUT
VSS
VOUT
VSS
+
+
Fig 9
- 49 -
NJU6823
(22)Reference voltage generator
The reference voltage generator is used to produce the reference voltage (VBA), which is output from the VBA
terminal and should be input to the VREF terminal.
VBA = VEE x 0.9
(23)Voltage regulator
The voltage regulator, composed of the gain control circuit and an operational amplifier, and is used to gain
the reference voltage (VREF) and to create the regulated voltage (VREG). The VREG is used as an input voltage to
the EVR circuits, which is programmed by the “VU” register of the “Boost level” instruction.
VREG = VREF x N
(N: register value for the boost level)
(24)Electrical variable resister (EVR)
The EVR is variable within 128-step, and is used to fine-tune the LCD driving voltage (VLCD) by programming
the “DV” register in the “EVR control” instruction, so that it is possible to optimize the contrast level for a LCD
panels.
VLCD = 0.5 x VREG + M (VREG - 0.5 x VREG) / 127 (M: register value for the EVR)
(25)LCD driving voltage generation circuit
LCD driving voltage generation circuit generates the VLCD voltage levels as VLCD, V1, V2, V3 and V4 with
internal E.V.R and the Bleeder resistors. The bias ratio of the LCD driving voltage is selected out of 1/5, 1/6, 1/7,
1/8, 1/9, 1/10, 1/11 and 1/12.
In using the internal power supply, the capacitors CA2 must be connected to the VLCD, V1, V2, V3 and V4
terminals, and the CA2 value must be determined by the evaluation with actual LCD modules.
In using the external power supply, the external LCD driving voltages such as the VLCD, V1, V2, V3 and V4 are
supplied and the internal power supply circuits must be set to “OFF” by DCON = AMPON = "0". In this mode,
voltage booster terminals such as C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, VEE, VREF and VREG must be
opened.
In case that the voltage booster is not used but only some parts of internal power supply circuits (Voltage
followers, Voltage regulator and EVR) are used, the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+ and C5-
terminals must be opened. And, the external power supply is input to the VOUT terminal, and the reference
voltage to the VREF terminal. The capacitor CA3 must connect to the VREG terminal for voltage stabilization.
< Bias adjustment function >
NJU6823 prepares bias adjustment terminals V1A1, V1A2, V4A1 and V4A2 for fine adjustment of V1 and V4
out of voltages.
The status combination of V1A1 terminal and V1A2 can adjust V1 voltage in below table and V4A1 and V4A2
can adjust V4 voltage. These adjustment performes by the connection change between the Bleeder resistors
and the output buffer operational amplifier as voltage follower circuit.
V1A1
V1A2
Fluctuation
V4A1
V4A2
Fluctuation
terminal
terminal
voltage [mV] *1
terminal
terminal
voltage [mV] *1
0
0
1
1
0
1
0
1
0
+5
-5
0
0
1
1
0
1
0
1
0
+5
-5
+10
-10
note 1) The fluctuation voltage is a adjusted voltage against the default voltage at (V1A1, V1A2 = "0, 0" and
V4A1, V4A2 = "0, 0"). The "+" mark means a direction of voltage fluctuation to VLCD and the "-" is to VSS.
Note 2) The fluctuation voltage is an ideal value.
Note 3) The fluctuation voltage is at VLCD=13.5V.
Note 4) "0" of V1A1, V1A2, V4A1 and V4A2 means VSS and "1" means VDD.
- 50 -
NJU6823
Connections of the capacitors for voltage boost
Using all of the internal power supply circuits
(6-time boost)
Using only external power supply circuits
VDD
VDD
VDD
VEE
VDD
VEE
CA1
CA1
VBA
VBA
VREF
VREG
VREF
CA3
VREG
CA3
VSS
VSS
C1-
C1+
C2-
C2+
C3-
C3+
C4-
C4+
C5-
C5+
C1-
C1+
C2-
C2+
C3-
C3+
C4-
C4+
C5-
C5+
CA1
CA1
CA1
CA1
CA1
NJU6823
NJU6823
VOUT
VOUT
CA1
VSS
CA1
VLCD
V1
VLCD
V1
VLCD
V1
CA2
CA2
CA2
CA2
CA2
External
V2
V2
V3
V4
V2
Power
circuit
V3
V3
V4
V4
VSS
CA2
CA2
CA2
Fig 10
Fig11
CA2
Reference values
CA1
CA2
CA3
1.0 to 4.7uF
1.0 to 2.2uF
0.1uF
Note1) B grade capacitor is recommended for CA1-CA3. Testing actual samples with an LCD panel is
recommended to decide an optimum value of these capacitors.
Note2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4)
reduces the step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation
and display quality. To minimize this impact, use the shortest possible wires and place the capacitors
to be as close as possible to the LSI.
- 51 -
NJU6823
Using internal power supply circuits
Using internal power supply circuit
Without the reference voltage generator(2)
(6-time boost)
Without the reference voltage generator(1)
(6-time boost)
VDD
VDD
VDD
VDD
VEE
VEE
CA1
CA1
VBA
VBA
VREF
VREF
VREG
VREG
CA3
VSS
CA1
CA3
VSS
C1-
C1-
CA1
C1+
C1+
C2-
CA1
C2-
CA1
C2+
C2+
C3-
C3-
CA1
CA1
C3+
C3+
C4-
C4-
CA1
CA1
NJU6823
CA1
CA1
NJU6823
C4+
C5-
C5+
C4+
C5-
C5+
VOUT
VOUT
CA1
VSS
CA1
VSS
VLCD
V1
VLCD
V1
CA2
CA2
CA2
CA2
CA2
CA2
CA2
CA2
CA2
CA2
V2
V2
V3
V3
V4
V4
VSS
VSS
Fig 12
Fig 13
Reference value
CA1
CA2
CA3
1.0 to 4.7µF
1.0 to 2.2µF
0.1µF
Note1) B grade capacitor is recommended for CA1-CA3. Testing actual samples with an LCD panel is
recommended to decide an optimum value of these capacitors.
Note2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4)
reduces the step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation
and display quality. To minimize this impact, use the shortest possible wires and place the capacitors
to be as close as possible to the LSI.
- 52 -
NJU6823
Using internal power supply circuits
Without the voltage booster
VDD
VDD
VEE
VBA
CA3
VREF
VREG
CA3
VSS
VSS
C1-
C1+
C2-
C2+
C3-
C3+
C4-
C4+
C5-
C5+
NJU6823
External
Power
circuit
VOUT
VLCD
V1
CA2
CA2
CA2
CA2
CA2
V2
V3
V1
VSS
Fig 14
Reference value
CA1
CA2
CA3
1.0 to 4.7µF
1.0 to 2.2µF
0.1µF
Note1) B grade capacitor is recommended for CA1-CA3. Testing actual samples with an LCD panel is
recommended to decide an optimum value of these capacitors.
Note2) Parasitic resistance on the power supply lines (VDD, VSS, VEE, VSSH, VOUT, VLCD, V1, V2, V3 and V4)
reduces the step-up efficiency of the voltage booster, and may have an impact on the LSI’s operation
and display quality. To minimize this impact, use the shortest possible wires and place the capacitors
to be as close as possible to the LSI.
- 53 -
NJU6823
(26) Partial display function
The partial display function is used to partially specify some parts of display area on LCD panels. By using
this function, LCD modules can work in lower duty cycle ratio, lower LCD bias ratio, lower boost level and lower
LCD driving voltage. It is usually used to display a time and calendar, and is also used to optimize the LSI
condition in accordance with the display size. It can be programmed to select the duty cycle ratio (1/17, 1/25,
1/33, 1/41, 1/49, 1/57, 1/65, 1/73, 1/81, 1/89, 1/97, 1/105, 1/113, 1/121, 1/129, in DSE=0), the LCD bias ratio,
the boost level and the EVR value by the instructions.
Partial display image
NJRC
LCD DRIVER
Low Power and
Low Voltage
LCD DRIVER
Partial display
Normal display
Partial display sequence
Optional status
Display OFF (ON/OFF=”0”)
Internal Power supply OFF (DCON=”0”, AMPON=”0”)
WAIT
Setting for LCD driving voltage-related functions
Internal Power supply ON (DCON=”1”, AMPON=”1”)
- Boost level
- EVR value
- LCD bias ratio
WAIT
- Duty cycle ratio
- Initial display line
- Initial COM line
- Other instructions
Setting for display-related functions
Display ON (ON/OFF =”1”)
Partial display Status
- 54 -
NJU6823
(27) Discharge circuit
Discharge circuit is used to discharge the electric charge of the capacitors on the V1 to V4 and VLCD terminals.
This circuit is activated by setting “0” to the “DIS” register of the “Discharge” instruction or by setting “RESb”
terminal to ”0” level. The “Discharge ON/OFF” instruction is usually required just after the internal power supply
is turned off by setting “0” into the “DCON” and “AMPON” registers, or just after the external power supply is
turned off. During the discharge operation, the internal or external power supply must not be turned on.
(28)Reset circuit
The reset circuit initializes the LSI into the following default status. It is activated by setting the RESb terminal
to “0”. The RESb terminal is usually required to connect to MPU reset terminal in order that the LSI can be
initialized at the same timing of the MPU.
ꢀ Default status
1. DDRAM display data
2. Column address
3. Row address
:Undefined
:(00)H
:(00)H
4. Initial display line
5. Display ON/OFF
6. Reverse display ON/OFF
7. Duty cycle ratio
8. N-line Inversion ON/OFF
9. COM scan direction
10. Increment mode
:(0)H (1st line)
:OFF
:OFF (normal)
:1/129 duty(DSE=0)
:OFF
:COM0 → COM127
:OFF
11. Reverse SEG direction
12. SWAP mode
13. EVR value
14. Internal power supply
15. Display mode
16. LCD bias ratio
:OFF (normal)
:OFF (normal)
:(0, 0, 0, 0, 0, 0, 0)
:OFF
:Gradation display mode
:1/9 bias
17. Gradation Palette 0
18. Gradation Palette 1
19. Gradation Palette 2
20. Gradation Palette 3
21. Gradation Palette 4
22. Gradation Palette 5
23. Gradation Palette 6
24. Gradation Palette 7
25. Gradation Palette 8
26. Gradation Palette 9
27. Gradation Palette 10
28. Gradation Palette 11
29. Gradation Palette 12
30. Gradation Palette 13
31. Gradation Palette 14
32. Gradation Palette 15
33. Gradation mode control
34. Data bus length
:(0, 0, 0, 0, 0)
:(0, 0, 0, 1, 1)
:(0, 0, 1, 0, 1)
:(0, 0, 1, 1, 1)
:(0, 1, 0, 0, 1)
:(0, 1, 0, 1, 1)
:(0, 1, 1, 0, 1)
:(0, 1, 1, 1, 1)
:(1, 0, 0, 0, 1)
:(1, 0, 0, 1, 1)
:(1, 0, 1, 0, 1)
:(1, 0, 1, 1, 1)
:(1, 1, 0, 0, 1)
:(1, 1, 0, 1, 1)
:(1, 1, 1, 0, 1)
:(1, 1, 1, 1, 1)
:Variable gradation mode
:8-bit data bus length
:(DIS, DIS2)=(0, 0)
35. Discharge circuit
- 55 -
NJU6823
(29)Power supply ON/OFF sequences
The following paragraphs describe power supply ON/OFF sequences, which are to protect the LSI from over
current.
(29-1) Using an external power supply
ꢀ Power supply ON sequence
Logic voltage (VDD) must be always input first, and next the LCD driving voltages (V1 to V4 and VLCD
)
are turned on. In using the external VOUT, the VDD must be input first, next the reset operation must be
performed, and finally the VOUT can be input.
ꢀ Power supply OFF sequence
Either the reset operation, cutting off the V1 to V4 and VLCD from the LSI by the RESb terminal or the
“Power control” instruction must be performed first, and next the VDD is turned off. It is recommended
that a series-resister between 50Ω and 100Ω is added on the VLCD line (or VOUT line in using only the
external VOUT voltage) in order to protect the LSI from the over current.
(29-2) Using the internal power supply circuits
ꢀ Power supply ON sequence
The VDD must be input first, next the reset operation must be performed, and finally the V1 to V4 and
VLCD can be turned on by setting “1” to the “DCON” and “AMPON” registers of the “Power control”
instruction.
ꢀ Power supply OFF sequence
Either the reset operation by the RESb terminal or the “Power control” instruction must be
performed first, and next the input voltage for the voltage booster (VEE) and the VDD can be turned off.
If the VEE is supplied from different power sources for VDD, the VEE is turned off first, and next the VDD
is turned off.
- 56 -
NJU6823
(30)Referential instruction sequences
(30-1) Initialization in using the internal power supply circuits
VDD, VEE power ON
Wait for power-ON stabilization
RESET Input
WAIT
Setting for LCD driving voltage-related functions
End of initialization
- EVR value
- LCD bias ratio
- Power control (DCON=”1”, AMPON=”1”)
(30-2) Display data writing
End of Initialization
Setting for display-related functions
- Initial display line
- Increment mode
- Column address
- Row address
Display data write
Display ON (ON/OFF =”1”)
- 57 -
NJU6823
(30-3) Power OFF
Optional status
- All COM/SEG output VSS level.
Power save or reset operation
Discharge ON
WAIT
VEE, VDD power OFF
- 58 -
NJU6823
(31)Instruction table
Instruction Table (1)
Code (80 series MPU I/F)
Code
Functions
Instructions
WRb
CSb RS RDb
RE2 RE1 RE0 D7 D6 D5 D4 D3
D2
D1
D0
Display data write
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0/1 0/1 0/1
0/1 0/1 0/1
Write Data
Write display data to DDRAM
Display data read
column address
Read Data
Read display data from DDRAM
DDRAM column address
DDRAM column address
DDRAM row address
AX3
AX7
AY3
*
AX2
AX6
AY2
AY6
LA2
LA6
N2
AX1
AX5
AY1
AY5
LA1
LA5
N1
AX0
AX4
AY0
AY4
LA0
LA4
N0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(Lower) [0H]
column address
(Upper) [1H]
row address
(Lower) [2H]
row address
(Upper) [3H]
DDRAM row address
Initial display line
(Lower) [4H]
Row address for an initial COM line
(Scan start line)
LA3
*
Initial display line
(Upper) [5H]
Row address for an initial COM line
(Scan start line)
N-line inversion
(Lower) [6H]
N3
*
The number of N-line inversion
N-line inversion
(Upper) [7H]
N6
N5
N4
The number of N-line inversion
SHIFT: Common direction
Display control (1)
ALL
ON
ON/ MON: Gradation or B/W display mode
SHIFT MON
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
OFF
ALLON: All pixels ON/OFF
ON/OFF: Display ON/OFF
[8H]
[9H]
REV: Reverse display ON/OFF
NLIN: N-line inversion ON/OFF,
SWAP: SWAP mode ON/OFF
REF: Segment direction
Display control (2)
REV NLIN SWAP REF
WIN: Window addressing mode ON/OFF
AIM: Read-modify-write ON/OFF
AYI: Row auto-increment mode ON/OFF
AXI: Column auto-increment mode
ON/OFF
AMPON: Voltage followers ON/OFF
HALT: Power save ON/OFF
DCON: Voltage booster ON/OFF
ACL: Reset
Increment control
Power control
WIN
AIM
AYI
AXI
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
[AH]
[BH]
AMP
ON
DC
ON
HALT
ACL
Duty cycle ratio
Boost level
DS3 DS2 DS1 DS0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Sets LCD duty cycle ratio
Sets boost level
[CH]
[DH]
[EH]
[FH]
VU2 VU1 VU0
*
*
LCD bias ratio
RE register
B2
B1
B0
Sets LCD bias ratio
RE flag set
TST0 RE2 RE1 RE0
0/1 0/1 0/1
Note 1)
*
: Don’t care.
Note 2) [ NH ] : Address of instruction register
Note 3)
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 59 -
NJU6823
Instruction Table (2)
Instructions
Code (80 series MPU I/F)
Code
Functions
WRb
CSb RS RDb
RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
Gradation palette A0/A8
(Lower) [0H]
Sets palette values to gradation
palette A0(PS=0)/A8(PS=1)
PA03/ PA02/ PA01/ PA00/
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
PA83 PA82 PA81 PA80
Gradation palette A0/A8
(Upper) [1H]
Sets palette values to gradation
palette A0(PS=0)/A8(PS=1)
PA04/
*
*
*
PA84
Gradation palette A1/A9
(Lower) [2H]
Sets palette values to gradation
palette A1(PS=0)/A9(PS=1)
PA13/ PA12/ PA11/ PA10/
PA93 PA92 PA91 PA90
Gradation palette A1/A9
(Upper) [3H]
Sets palette values to gradation
palette A1(PS=0)/A9(PS=1)
PA14/
*
*
*
PA94
Gradation palette A2/A10
(Lower) [4H]
Sets palette values to gradation
palette A2(PS=0)/A10(PS=1)
PA23/ PA22/ PA21/ PA20/
PA103 PA102 PA101 PA100
Gradation palette A2/A10
(Upper) [5H]
Sets palette values to gradation
palette A2(PS=0)/A10(PS=1)
PA24/
*
*
*
PA104
Gradation palette A3/A11
(Lower) [6H]
Sets palette values to gradation
palette A3(PS=0)/A11(PS=1)
PA33/ PA32/ PA31/ PA30/
PA113 PA112 PA111 PA110
Gradation palette A3/A11
(Upper) [7H]
Sets palette values to gradation
palette A3(PS=0)/A11(PS=1)
PA34/
*
*
*
PA114
Gradation palette A4/A12
(Lower) [8H]
Sets palette values to gradation
palette A4(PS=0)/A12(PS=1)
PA43/ PA42/ PA41/ PA40/
PA123 PA122 PA121 PA120
Gradation palette A4/A12
(Upper) [9H]
Sets palette values to gradation
palette A4(PS=0)/A12(PS=1)
PA44/
*
*
*
PA124
Gradation palette A5/A13
(Lower) [AH]
Sets palette values to gradation
palette A5(PS=0)/A13(PS=1)
PA53/ PA52/ PA51/ PA50/
PA133 PA132 PA131 PA130
Gradation palette A5/A13
(Upper) [BH]
Sets palette values to gradation
palette A5(PS=0)/A13(PS=1)
PA54/
*
*
*
PA134
Gradation palette A6/A14
(Lower) [CH]
Sets palette values to gradation
palette A6(PS=0)/A14(PS=1)
PA63/ PA62/ PA61/ PA60/
PA143 PA142 PA141 PA140
Gradation palette A6/A14
(Upper) [DH]
Sets palette values to gradation
palette A6(PS=0)/A14(PS=1)
PA64/
*
*
*
PA144
RE register
[FH]
TST0 RE2 RE1 RE0
0/1 0/1 0/1
RE flag set
Note 1)
*
: Don’t care.
Note 2) [ NH ] : Address of Instruction register
Note 3)
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 60 -
NJU6823
Instruction Table (3)
Code (80 series MPU I/F)
Code
Instructions
Functions
WRb
CSb RS RDb
RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
Gradation palette A7/A15
(Lower) [0H]
Sets palette values to gradation
palette A7(PS=0)/A15(PS=1)
PA73/ PA72/ PA71/ PA70/
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
PA153 PA152 PA151 PA150
Gradation palette A7/A15
(Upper) [1H]
Sets palette values to gradation
palette A7(PS=0)/A15(PS=1)
PA74/
*
*
*
PA154
Gradation palette B0/B8
(Lower) [2H]
Sets palette values to gradation
palette B0(PS=0)/B8(PS=1)
PB03/ PB02/ PB01/ PB00/
PB83 PB82 PB81 PB80
Gradation palette B0/B8
(Upper) [3H]
Sets palette values to gradation
palette B0(PS=0)/B8(PS=1)
PB04/
*
*
*
PB84
Gradation palette B1/B9
(Lower) [4H]
Sets palette values to gradation
palette B1(PS=0)/B9(PS=1)
PB13/ PB12/ PB11/ PB10/
PB93 PB92 PB91 PB90
Gradation palette B1/B9
(Upper) [5H]
Sets palette values to gradation
palette B1(PS=0)/B9(PS=1)
PB14/
*
*
*
PB94
Gradation palette B2/B10
(Lower) [6H]
Sets palette values to gradation
palette B2(PS=0)/B10(PS=1)
PB23/ PB22/ PB21/ PB20/
PB103 PB102 PB101 PB100
Gradation palette B2/B10
(Upper) [7H]
Sets palette values to gradation
palette B2(PS=0)/B10(PS=1)
PB24/
*
*
*
PB104
Gradation palette B3/B11
(Lower) [8H]
Sets palette values to gradation
palette B3(PS=0)/B11(PS=1)
PB33/ PB32/ PB31/ PB30/
PB113 PB112 PB111 PB110
Gradation palette B3/B11
(Upper) [9H]
Sets palette values to gradation
palette B3(PS=0)/B11(PS=1)
PB34/
*
*
*
PB114
Gradation palette B4/B12
(Lower) [AH]
Sets palette values to gradation
palette B4(PS=0)/B12(PS=1)
PB43/ PB42/ PB41/ PB40/
PB123 PB122 PB121 PB120
Gradation palette B4/B12
(Upper) [BH]
Sets palette values to gradation
palette B4(PS=0)/B12(PS=1)
PB44/
*
*
*
PB124
Gradation palette B5/B13
(Lower) [CH]
Sets palette values to gradation
palette B5(PS=0)/B13(PS=1)
PB53/ PB52/ PB51/ PB50/
PB133 PB132 PB131 PB130
Gradation palette B5/B13
(Upper) [DH]
Sets palette values to gradation
palette B5(PS=0)/B13(PS=1)
PB54/
*
*
*
PB134
RE register
[FH]
TST0 RE2 RE1 RE0
0/1 0/1 0/1
RE flag set
Note 1)
*
: Don’t care.
Note 2) [ NH ] : Address of Instruction register
Note 3)
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 61 -
NJU6823
Instruction Table (4)
Instructions
Code (80 series MPU I/F)
Code
Functions
WRb
CSb RS RDb
RE2 RE1 RE0 D7
D6
0
D5
0
D4
D3 D2
D1 D0
Gradation palette B6/B14
(Lower) [0H]
Sets palette values to gradation
palette B6(PS=0)/B14(PS=1)
PB63/ PB62/ PB61/ PB60/
PB143 PB142 PB141 PB140
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
Gradation palette B6/B14
(Upper) [1H]
Sets palette values to gradation
palette B6(PS=0)/B14(PS=1)
PB64/
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
*
*
*
PB144
Gradation palette B7/B15
(Lower) [2H]
Sets palette values to gradation
palette B7(PS=0)/B15(PS=1)
PB73/ PB72/ PB71/ PB70/
PB153 PB152 PB151 PB150
Gradation palette B7/B15
(Upper) [3H]
Sets palette values to gradation
palette B7(PS=0)/B15(PS=1)
PB74/
*
*
*
PB154
Gradation palette C0/C8
(Lower) [4H]
Sets palette values to gradation
palette C0(PS=0)/C8(PS=1)
PC03/ PC02/ PC01/ PC00/
PC83 PC82 PC81 PC80
Gradation palette C0/C8
(Upper) [5H]
Sets palette values to gradation
palette C0(PS=0)/C8(PS=1)
PC04/
*
*
*
PC84
Gradation palette C1/C9
(Lower) [6H]
Sets palette values to gradation
palette C1(PS=0)/C9(PS=1)
PC13/ PC12/ PC11/ PC10/
PC93 PC92 PC91 PC90
Gradation palette C1/C9
(Upper) [7H]
Sets palette values to gradation
palette C1(PS=0)/C9(PS=1)
PC14/
*
*
*
PC94
Gradation palette C2/C10
(Lower) [8H]
Sets palette values to gradation
palette C2(PS=0)/C10(PS=1)
PC23/ PC22/ PC21/ PC20/
PC103 PC102 PC101 PC100
Gradation palette C2/C10
(Upper) [9H]
Sets palette values to gradation
palette C2(PS=0)/C10(PS=1)
PC24/
*
*
*
PC104
Gradation palette C3/C11
(Lower) [AH]
Sets palette values to gradation
palette C3(PS=0)/C11(PS=1)
PC33/ PC32/ PC31/ PC30/
PC113 PC112 PC111 PC110
Gradation palette C3/C11
(Upper) [BH]
Sets palette values to gradation
palette C3(PS=0)/C11(PS=1)
PC34/
*
*
*
PC114
Gradation palette C4/C12
(Lower) [CH]
Sets palette values to gradation
palette C4(PS=0)/C12(PS=1)
PC43/ PC42/ PC41/ PC40/
PC123 PC122 PC121 PC120
Gradation palette C4/C12
(Upper) [DH]
Sets palette values to gradation
palette C4(PS=0)/C12(PS=1)
PC44/
*
*
*
PC124
RE register
[FH]
TST0 RE2 RE1 RE0
0/1 0/1 0/1
RE flag set
Note 1)
*
: Don’t care.
Note 2) [ NH ] : Address of Instruction register
Note 3)
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 62 -
NJU6823
Instruction Table (5)
Code (80 series MPU I/F)
Code
Instructions
Functions
WRb
CSb RS RDb
RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
Gradation palette C5/C13
(Lower) [0H]
Sets palette values to gradation
palette C5(PS=0)/C13(PS=1)
PC53/ PC52/ PC51/ PC50/
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
PC133 PC132 PC131 PC130
Gradation palette C5/C13
(Upper) [1H]
Sets palette values to gradation
palette C5(PS=0)/C13(PS=1)
PC54/
*
*
*
PC134
Gradation palette C6/C14
(Lower) [2H]
Sets palette values to gradation
palette C6(PS=0)/C14(PS=1)
PC63/P PC62/ PC61/ PC60/
C143 PC142 PC141 PC140
Gradation palette C6/C14
(Upper) [3H]
Sets palette values to gradation
palette C6(PS=0)/C14(PS=1)
PC64/
*
*
*
PC144
Gradation palette C7/C15
(Lower) [4H]
Sets palette values to gradation
palette C7(PS=0)/C15(PS=1)
PC73/ PC72/ PC71/ PC70/
PC153 PC152 PC151 PC150
Gradation palette C7/C15
(Upper) [5H]
Sets palette values to gradation
palette C7(PS=0)/C15(PS=1)
PC74/
*
*
*
PC154
Initial COM line
[6H]
SC3 SC2 SC1 SC0
Sets scan-starting common driver
Display control Signal/
Duty Select
[7H]
SON : Display clock ON/OFF
DSE : Duty-1 ON/OFF
SON
DSE
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
1
0
1
*
*
PWM : Variable/Fixed gradation mode
Gradation mode control
PWM C256 FDC1 FDC2 C256 : 256-Color Mode ON/OFF
[8H]
FDC : Boost Clock
HSW : High speed access ON/OFF
Data bus length
[9H]
ABS : ABS mode ON/OFF
HSW ABS CKS WLS
CKS : Internal/external oscilation
WLS : Display data Length
EVR control
Sets EVR level
DV3 DV2 DV1 DV0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
*
0
0
1
1
1
1
*
1
1
0
1
1
0
*
0
1
1
0
1
0
*
(Lower) [AH]
(Lower bit)
EVR control
Sets EVR level
DV6 DV5 DV4
RF2 RF1 RF0
*
*
*
(Upper) [BH]
(Upper bit)
Frequency control
[DH]
Oscillation frequency
Discharge ON/OFF
[EH]
Discharge the electric charge in
capacitors on V1 to V4 and VLCD
DIS
DIS2
*
RE register
[FH]
TST0 RE2 RE1 RE0
Reading address
Read Data
0/1 0/1 0/1
RE flag
Instruction register address
[CH]
1
0
0
Sets instruction register address
Read out instruction register data
Instruction register read
0/1 0/1 0/1
Note 1)
*
: Don’t care.
Note 2) [ NH ] : Address of Instruction register
Note 3)
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
Note 4)
CKS=0: Internal oscillation mode (default)
CKS=1: External oscillation mode
- 63 -
NJU6823
Instruction Table (6)
Instructions
Code (80 series MPU I/F)
Code
Functions
WRb
CSb RS RDb
RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 D0
Window end
column address
(Lower) [0H]
Window end
column address
(Upper) [1H]
EX3 EX2 EX1 EX0
EX7 EX6 EX5 EX4
EY3 EY2 EY1 EY0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Sets column address for end point
Sets column address for end point
Sets row address for end point
Sets row address for end point
Sets address for reverse line
Sets address for reverse line
Sets address for reverse line
Sets address for reverse line
Window end row address
(Lower) [2H]
Window end row address
(Upper) [3H]
*
EY6 EY5 EY4
Initial reverse line
(Lower) [4H]
LS3 LS2 LS1 LS0
Initial reverse line
(Upper) [5H]
*
LS6 LS5 LS4
Last reverse line
(Lower) [6H]
LE3 LE2 LE1 LE0
Last reverse line
(Upper) [7H]
*
LE6 LE5 LE4
Reverse line display
ON/OFF
BT : Blink type setting
BT LREV
*
*
*
LREV : Reverse line display ON/OFF
[8H]
Gradation palette setting
control
address
[9H]
/
Icon SEG
set
PS : gradation setting
PS
DMY
0
1
1
0
1
1
0
0
1
1
1
0
0
1
*
DMY : Icon SEG address set
PWM control
PWM PWM PWM PWM
0
0
1
1
1
1
0
0
1
1
0
1
1
1
0
1
Sets PWM mode
RE flag
S
A
B
C
[AH]
[FH]
RE register
TST0 RE2 RE1 RE0
0/1 0/1 0/1
Note 1)
*
: Don’t care.
Note 2) [ NH ] : Address of Instruction register
Note 3)
The dual instructions including upper and lower bytes is enabled after either upper or lower
bytes are set into the register. The only “EVR control” instruction is enabled after both of the
upper and lower bytes are set.
- 64 -
NJU6823
(32)Instruction descriptions
This chapter provides detail descriptions and instruction registers. Nonexistent instruction codes must not be
set into the LSI.
(32-1) Display data write
The “Display data write” instruction is used to write 8-bit display data into the DDRAM.
WRb
CSb RS RDb
RE2 RE1 RE0
0/1 0/1 0/1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
Display data
(32-2) Display data read
The “Display data read” instruction is used to read out 8-bit display data from the DDRAM, where the
column address and row address must be specified beforehand by the “column address” and “row
address” instructions. The dummy read is required just after the “column address” and “row address”
instructions.
WRb
CSb RS RDb
RE2 RE1 RE0
0/1 0/1 0/1
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
Display data
(32-3) Column address
The “column address” instruction is used to specify the column address for the display data’s reading
and writing operations. It requires dual bytes for lower 4-bit and upper 4-bit data. The instruction for the
lower 4-bit data must be executed first, next the instruction for the upper 4-bit.
WRb
CSb RS RDb
RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
0
AX3 AX2 AX1 AX0
WRb
CSb RS RDb
RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
D2
D1
D0
0
1
1
0
0
0
0
AX7 AX6 AX5 AX4
(32-4) Row address
The “row address” instruction is used to specify the row address for the display data read and write
operations. It requires dual bytes for lower 4-bit and upper 3-bit data. The instruction for the lower 4-bit
data must be executed first, next the instruction for upper 3-bit. The row address is specified in between
00H and 7FH. The setting for nonexistent row address between 80H and FFH is prohibited.
WRb
CSb RS RDb
RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
0
AY3 AY2
AY1 AY0
WRb
CSb RS RDb
RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
D1
D0
0
1
1
0
0
0
0
AY6
AY5 AY4
- 65 -
NJU6823
(32-5) Initial display line
The “Initial display line” instruction is used to specify the line address corresponding to the initial COM
line. The initial COM line specified by the “Initial COM line” instruction and indicates the common driver
that starts scanning data.
WRb
CSb RS RDb
RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
0
LA3
LA2
LA1 LA0
WRb
CSb RS RDb
RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
D1
D0
0
1
1
0
0
0
0
LA6
LA5 LA4
LA6
0
0
LA5
0
0
LA4
0
0
LA3
0
0
LA2
0
0
LA1
0
0
LA0
0
1
Line address
0
1
:
:
:
:
1
1
1
1
1
1
1
127
(32-6) N-line inversion
The “N-line inversion” instruction is used to control the alternate rates of the liquid crystal direction. It is
programmed to select the N value between 2 and 128, and the FR signal toggles once every N lines by
setting “1” into the “NLIN” register of the “Display control (2)” instruction. When the N-line inversion is
disabled by setting “0” into the “NLIN” register, the FR signal toggles by the frame.
WRb
CSb RS RDb
RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
0
N3
N2
N1
N0
WRb
CSb RS RDb
RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
D1
D0
0
1
1
0
0
0
0
N6
N5
N4
N6
0
0
N5
0
0
N4
0
0
N3
0
0
N2
0
0
N1
0
0
N0
0
1
N value
Inhibited
2
:
:
:
:
0
0
1
0
0
0
0
128
- 66 -
NJU6823
ꢁ N-line Inversion Timing (1/129 duty cycle ratio)
N-line inversion OFF
1st line
3rd line
128th line
1st line
2nd line
129th line
CL
FLM
FR
N-line inversion ON
N-line control
1st line
3rd line
N line
2nd line
2nd line
1st line
CL
FR
(32-7) Display control (1)
The “Display control (1)” instruction is used to control display conditions by setting the “Display ON/OFF”,
“All pixels ON/OFF”, ”Display mode” and “Common direction” registers.
WRb
CSb RS RDb
RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
SHIFT
MON
ALLON ON/OFF
0
1
1
0
0
0
0
ꢁ ON/OFF register
ON/OFF=0 : Display OFF (All COM/SEG output Vss level.)
ON/OFF=1 : Display ON
ꢁ All ON register
The “All pixels ON/OFF” register is used to turn on all pixels without changing the display data of
the DDRAM. The setting for the “All pixels ON/OFF” register has a priority over the “Reverse display
ON/OFF” register.
ALLON=0
ALLON=1
: Normal
: All pixels turn on.
ꢁ MON register
MON=0
MON=1
: Gradation mode
: B&W mode
ꢁ SHIFT register
SHIFT=0
SHIFT=1
: COM0 → COM127
: COM127 → COM0
- 67 -
NJU6823
(32-8) Display control (2)
The “Display control (2)” instruction is used to control display conditions by setting the “Segment
direction”, “SWAP mode ON/OFF”, “N-line inversion ON/OFF” and “Reverse display ON/OFF” registers.
WRb
CSb RS RDb
RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
D2
D1
D0
REV
NLIN
SWAP
REF
0
1
1
0
0
0
0
ꢁ REF register
The “REF” register is used to reverse the assignment between segment drivers and column
address, and it is possible to reduce restrictions for placement of the LSI on the LCD modules. For
more information, see (10) “The relation among the DDRAM column address, display data and
segment drivers”.
ꢁ SWAP register
The “SWAP” register is used to reverse the arrangement of the display data in the DDRAM.
SWAP=0
SWAP=1
: SWAP mode OFF
: SWAP mode ON
(Normal)
SWAP=”0”
SWAP=”1”
Write data
D7 D6 D5 D4 D3 D2 D1 D0
D7 d6 d5 d4 d3 d2 d1 d0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
RAM data
d0 d1 d2 d3 d4 d5 d6 d7
D7 D6 D5 D4 D3 D2 D1 D0
Read data
ꢁ NLIN register
The “NLIN” is used to enable or disable the N-line inversion.
NLIN=0
NLIN=1
: N-line inversion OFF
: N-line inversion ON
(The FR signal toggles by the flame.)
(The FR signal toggles once every N frames.)
ꢁ REV register
The “REV” register is used to enable or disable the reverse display mode that reverses the polarity
of display data without changing display data of the DDRAM.
REV=0
REV=1
: Reverse display mode OFF
: Reverse display mode ON
REV
Display
Normal
DDRAM data → Display data
0
1
0
1
0
1
1
0
0
1
Reverse
- 68 -
NJU6823
(32-9) Increment control
The “Increment control” instruction is used for the increment mode. In using the auto-increment mode,
DDRAM address automatically increments (+1) whenever the DDRAM is accessed by the “Display data
write” or “Display data read” instruction. Therefore, once “Display data write” or “Display data read”
instruction is established, it is possible to continuously access to the DDRAM without the “column address”
and “row address” instructions. The settings for the “AIM”, “AXI” and “AYI” registers are listed in the
following tables.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
0
WIN AIM AYI AXI
ꢁ AIM, AYI and AXI registers
AIM
0
1
Increment mode
Auto-increment for both of the display data read and write operations
Auto-increment for the display write operation (Read modify write)
Note
1
2
Note 1) It is effective for usual operations accessing successive addresses.
Note 2) It is effective for the read-modify-write operation.
AYI
0
AXI
0
Increment mode
Note
No auto-increment
1
2
3
0
1
Auto-increment for the column address
Auto-increment for the row address
Auto-increment for the column address and row
address
1
0
1
1
4
Note 1) Auto-increment is disabled regardless of the “AIM” register.
Note 2) Auto-increment of the column address is enabled in accordance with the “AIM” register.
MAXH
00H
MAXH in the 8-bit data bus mode
: FFH
MAXH in the 16-bit data bus mode : 7FH
Note 3) Auto-increment of the row address is enabled in accordance with the “AIM” register.
7FH
00H
Note 4) Auto-increment of the column address and the row address are enabled. The row address
increments whenever the column address reaches to the MAXH.
MaxH
00H
7FH
00H
column address
row address
MAXH in the 8-bit data bus mode
: FFH
MAXH in the 16-bit data bus mode : 7FH
- 69 -
NJU6823
ꢁ WIN register
The “WIN” register is used to access to the DDRAM for the window display area, where the start point is
determined by the “column address” and “row address” instructions, and the end point by the “Window
end column address “and ”Window end row address” instructions. The setting sequence for the window
display area is listed as follows. For more detail, see (7) “Window addressing mode”.
WIN=0 :Window addressing mode OFF
WIN=1 :Window addressing mode ON
1. Set WIN=1, AXI=1, and AYI=1 by “Increment control” instruction.
2. Set the start point by the “column address” and “row address” instructions
3. Set the end point by the “Window end column address” and “Window end row address” instructions
4. Enable to access to the DDRAM in the window addressing mode
START
END
END
START
Address
Address
Address
Address
column address
row address
- 70 -
NJU6823
(32-10) Power control
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
D2
D1
D0
AMPON HALT DCON
ACL
0
1
1
0
0
0
0
ꢁ ACL register
The “ACL” register is used to initialize the internal power supply circuits.
ACL=0
ACL=1
: Initialization OFF (Normal)
: Initialization ON
When the data of the “ACL register” is read out by the “Instruction register read” instruction, the
read-out data is “1” during the initialization and “0” after the initialization. This initialization is
performed by using the signal produced by 2 clocks on the OSC1. For this reason, the wait time for 2
clocks of the OSC1 is necessary until next instruction.
ꢁ DCON register
The “DCON” register is used to enable or disable the voltage booster.
DCON=0
DCON=1
: Voltage booster OFF
: Voltage booster ON
ꢁ HALT register
The “HALT” register is used to enable or disable the power save mode. It is possible to reduce
operating current down to stand-by level. The internal status in the power save mode is listed below.
HALT=0
HALT=1
: Power save OFF (Normal)
: Power save ON
Internal status in the power save mode
• The oscillation circuits and internal power supply circuits are halted.
• All segment and common drivers output VSS level.
• The clock input into the OSC1 is inhibited.
• The display data in the DDRAM is maintained.
• The operational modes before the power save mode are maintained.
• The V1 to V4 and VLCD are in the high impedance.
As a power save ON sequence, the “Display OFF” must be executed first, next the “Power save
ON” instruction, and then all common and segment drivers output the VSS level. And as power save
OFF sequence, the “Power save OFF” instruction is executed first, next the “Display ON” instruction.
If the “Power save OFF” instruction is executed in the display ON status, unexpected pixels may
instantly turn on.
ꢁ AMPON register
The “AMPON” register is used to enable or disable the voltage followers, voltage regulator and EVR.
AMPON=0 : The voltage followers, voltage regulator and the EVR OFF
AMPON=1 : The voltage followers, voltage regulator and the EVR ON
- 71 -
NJU6823
(32-11) Duty cycle ratio
The “Duty cycle ratio” instruction is used to select LCD duty cycle ratio for the partial display function.
The partial display function specifies some parts of display area on a LCD panel in the condition of lower
duty cycle ratio, lower LCD bias ratio, lower boost level and lower LCD driving voltage. Therefore, it is
possible to optimize the LSI’s conditions with extremely low power consumption.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
0
0
0
DS3 DS2 DS1 DS0
Duty cycle ratio
Row way
displays
DS3
DS2
DS1
DS0
DSE=0
1/129
1/121
1/113
1/105
1/97
DSE=1
1/128
1/120
1/112
1/104
1/96
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
128 commons
120 commons
112 commons
104 commons
96 commons
88 commons
80 commons
72 commons
64 commons
56 commons
48 commons
40 commons
32 commons
24 commons
16 commons
1/89
1/88
1/81
1/80
1/73
1/72
1/65
1/64
1/56
1/57
1/48
1/49
1/41
1/40
1/33
1/32
1/25
1/24
1/17
1/16
Inhibited
The duty cycle ratio is controlled by the “DS3 to DS0” registers of the “Duty cycle ratio” instruction and the “DSE”
register of the “Display Clock / Duty-1” instruction.
DSE=”0”
DSE=”1”
: The number of commons + 1
(Duty cycle ratio in the default setting)
: The number of commons (Duty-1)
When the “DSE” is “0”, all common drivers output non-selective levels in period of last common.
And the segment drivers output the same data for the last line as the data for previous line: For
instance they output the same data for the 128th and 129th lines when the duty cycle ratio is set to
1/129. For the setting of the “DSE” register, see (32-17) “Display clock / Duty-1”.
(32-12) Boost level
The “Boost level” is used to select the multiple of the voltage booster for the partial display function.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
D1
D0
0
1
1
0
0
0
0
VU2 VU1 VU0
VU2 VU1
VU0
0
Boost level
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1-time (No boost)
2-time
1
0
3-time
1
4-time
0
5-time
1
6-time
0
Inhibited
Inhibited
1
- 72 -
NJU6823
(32-13) LCD bias ratio
The “LCD bias ratio” is used to select the LCD bias ratio for the partial display function.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
1
D4
0
D3
*
D2
B2
D1
B1
D0
B0
0
1
1
0
0
0
0
B2
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
LCD bias ratio
1/9
1/8
1/7
1/6
1/5
1/10
1/11
1/12
(32-14) RE flag
The “RE flag” registers are used to determine the contents for the RE registers (RE2, RE1 and RE0) and
it is possible to access to the instruction registers.
The data in the “TST0” register must be “0”, and it is used maker tests only.
CSb RS RDb WRb RE2 RE1 RE0
0/1 0/1 0/1
D7
1
D6
1
D5
1
D4
1
D3
D2
D1
D0
0
1
1
0
TST0 RE2 RE1 RE0
- 73 -
NJU6823
(32-15) Gradation palette A, B and C
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
PA03
/
PA02
/
PA01
/
PA00/
0
1
1
0
0
0
1
PA83
PA82
PA81
PA80
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA04
/
0
1
1
0
0
0
1
PA84
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
PA13
/
PA12
/
PA11/ PA10/
0
1
1
0
0
0
1
PA93
PA92
PA91
PA90
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PA14
/
0
1
1
0
0
0
1
PA94
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
PA23
D2
PA22
D1
PA21
D0
PA20/
/
/
/
0
1
1
0
0
0
1
PA103 PA102 PA101 PA100
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA24
/
0
1
1
0
0
0
1
PA104
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
PA33
D2
PA32
D1
PA31
D0
PA30/
/
/
/
0
1
1
0
0
0
1
PA113 PA112 PA111 PA110
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PA34
/
0
1
1
0
0
0
1
PA114
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
PA43
D2
PA42
D1
PA41
D0
PA40/
/
/
/
0
1
1
0
0
0
1
PA123 PA122 PA121 PA120
- 74 -
NJU6823
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA44
/
0
1
1
0
0
0
1
PA124
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
PA53
D2
PA52
D1
PA51
D0
PA50/
/
/
/
0
1
1
0
0
0
1
PA133 PA132 PA131 PA130
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PA54
/
0
1
1
0
0
0
1
PA134
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
PA63
D2
PA62
D1
PA61
D0
PA60/
/
/
/
0
1
1
0
0
0
1
PA143 PA142 PA141 PA140
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA64
/
0
1
1
0
0
0
1
PA144
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
PA73
D2
PA72
D1
PA71
D0
PA70/
/
/
/
0
1
1
0
0
1
0
PA153 PA152 PA151 PA150
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PA74
/
0
1
1
0
0
1
0
PA154
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
PB03
/
PB02
/
PB01
/
PB00/
0
1
1
0
0
1
0
PB83
PB82
PB81
PB80
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PB04
/
0
1
1
0
0
1
0
PB84
- 75 -
NJU6823
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
PB13
/
PB12
/
PB11/ PB10/
0
1
1
0
0
1
0
PB93
PB92
PB91
PB90
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PB14
/
0
1
1
0
0
1
0
PB94
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
PB23
D2
PB22
D1
PB21
D0
PB20/
/
/
/
0
1
1
0
0
1
0
PB103 PB102 PB101 PB100
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PB24
/
0
1
1
0
0
1
0
PB104
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
PB33
D2
PB32
D1
PB31
D0
PB30/
/
/
/
0
1
1
0
0
1
0
PB113 PB112 PB111 PB110
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PB34
/
0
1
1
0
0
1
0
PB114
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
PB43
D2
PB42
D1
PB41
D0
PB40/
/
/
/
0
1
1
0
0
1
0
PB123 PB122 PB121 PB120
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PB44
/
0
1
1
0
0
1
0
PB124
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
PB53
D2
PB52
D1
PB51
D0
PB50/
/
/
/
0
1
1
0
0
1
0
PB133 PB132 PB131 PB130
- 76 -
NJU6823
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PB54
/
0
1
1
0
0
1
0
PB134
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
PB63
D2
PB62
D1
PB61
D0
PB60/
/
/
/
0
1
1
0
0
1
1
PB143 PB142 PB141 PB140
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PB64
/
0
1
1
0
0
1
1
PB144
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
PB73
D2
PB72
D1
PB71
D0
PB70/
/
/
/
0
1
1
0
0
1
1
PB153 PB152 PB151 PB150
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PB74
/
0
1
1
0
0
1
1
PB154
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
PC03/ PC02/ PC01/ PC00/
0
1
1
0
0
1
1
PC83
PC82
PC81
PC80
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC04/
PC84
0
1
1
0
0
1
1
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
PC13/ PC12/ PC11/ PC10/
0
1
1
0
0
1
1
PC93
PC92
PC91
PC90
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PC14/
PC94
0
1
1
0
0
1
1
- 77 -
NJU6823
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
PC23/ PC22/ PC21/ PC20/
PC103 PC102 PC101 PC100
0
1
1
0
0
1
1
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC24/
PC104
0
1
1
0
0
1
1
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
PC33/ PC32/ PC31/ PC30/
PC113 PC112 PC111 PC110
0
1
1
0
0
1
1
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PC34/
PC114
0
1
1
0
0
1
1
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
PC43/ PC42/ PC41/ PC40/
PC123 PC122 PC121 PC120
0
1
1
0
0
1
1
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC44/
PC124
0
1
1
0
0
1
1
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
PC53/ PC52/ PC51/ PC50/
PC133 PC132 PC131 PC130
0
1
1
0
1
0
0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC54/
PC134
0
1
1
0
1
0
0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
PC63/ PC62/ PC61/ PC60/
PC143 PC142 PC141 PC140
0
1
1
0
1
0
0
- 78 -
NJU6823
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
*
D1
*
D0
PC64/
PC144
0
1
1
0
1
0
0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
PC73/ PC72/ PC71/ PC70/
PC153 PC152 PC151 PC150
0
1
1
0
1
0
0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
*
D1
*
D0
PC74/
PC154
0
1
1
0
1
0
0
Gradation Palette Table (Variable gradation mode, PWM=”0” and MON=”0”)
(Palette Aj, Palette Bj, Palette Cj, (j=0 to 15))
Gradation
Level
Gradation
Palette Value
0 0 0 0 0
0 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
Note
Palette Value
Note
Level
16/31
Gradation Palette 0
Initial Value
0/31
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Gradation Palette 8
Initial Value
1/31
17/31
18/31
19/31
20/31
21/31
22/31
23/31
24/31
25/31
26/31
27/31
28/31
29/31
30/31
31/31
2/31
Gradation Palette 1
Initial Value
Gradation Palette 9
Initial Value
3/31
4/31
Gradation Palette2
Initial Value
Gradation Palette 10
Initial Value
5/31
6/31
Gradation Palette 3
Initial Value
Gradation Palette 11
Initial Value
7/31
8/31
Gradation Palette 4
Initial Value
Gradation Palette 12
Initial Value
9/31
10/31
11/31
12/31
13/31
14/31
15/31
Gradation Palette 5
Initial Value
Gradation Palette 13
Initial Value
Gradation Palette 6
Initial Value
Gradation Palette 14
Initial Value
Gradation Palette 7
Initial Value
Gradation Palette 15
Initial Value
- 79 -
NJU6823
(32-16) Initial COM line
The “Initial COM line” instruction is used to specify the common driver that starts scanning the display
data. The line address, corresponding to the initial COM line, is specified by the “Initial display line”
instruction.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
0
SC3 SC2 SC1 SC0
SC3
0
SC2 SC1 SC0
Initial COM line (SHIFT=0)
COM0
Initial COM line (SHIFT=1)
COM127
COM123
COM119
COM111
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
COM4
0
COM8
0
COM16
0
COM24
COM103
COM95
0
COM32
0
COM40
COM87
0
COM48
COM79
1
COM56
COM71
1
COM64
COM63
1
COM72
COM55
1
COM80
COM47
1
COM88
COM39
1
COM96
COM31
1
COM104
COM112
COM23
1
COM15
SHIFT=0: Positive scan direction
SHIFT=1: Negative scan direction
(for instance, COM0 → COM127
)
(for instance, COM127 → COM0)
(32-17) Display clock / Duty-1
The “Display clock / Duty-1” instruction is used to enable or disable the display clocks (CL, FLM, FR, and CLK),
and to control ON/OFF of the “Duty-1”. For more detail about the “Duty-1”, see (32-11) “Duty cycle ratio”.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
*
D1
D0
SON
0
1
1
0
1
0
0
DSE
SON=0:
SON=1:
CL, FLM, FR, and CLK outputs level “0”.
CL, FLM, FR, and CLK outputs are active.
DSE=0:
DSE=1:
Duty -1 OFF
Duty -1 ON
- 80 -
NJU6823
(32-18) Gradation mode control
The “Gradation mode control” is used to select display mode as follows.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
D2
D1
D0
PWM C256
0
1
1
0
1
0
0
FDC1 FDC2
ꢁ PWM register
PWM=0:
Variable gradation mode
(Variable 16-gradation levels out of 32-gradation level of the gradation palette)
Fixed gradation mode
PWM=1:
(Fixed 8-gradation levels)
ꢁ C256 register
C256=0
C256=1
256-color mode OFF (4,096-color in the default setting)
256-color mode ON
ꢁ FDC1 and FDC2 register
FDC1
FDC2
Boost Clock
0
0
1
1
0
1
0
1
×1
×2
×4
×1/2
- 81 -
NJU6823
(32-19)Data bus length
The “Data bus length” instruction is used to select the 8- or 16- bit data bus length and determine the
internal or external oscillation. In the 16-bit data bus mode, instruction data must be 16-bit (D15 to D0) as
well as display data. However, for the access to the instruction registers, the lower 8-bit data (D7 to D0) of
the 16-bit data is valid. For the access to the DDRAM, all of the 16-bit data (D15 to D0) is valid.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
D2
D1
D0
0
1
1
0
1
0
0
HSW ABS CKS WLS
ꢁ HSW register
HSW =0:
HSW=1:
High Speed access mode OFF
High Speed access mode ON (only in the 8-bit data bus length)
ꢁ ABS register
ABS=0:
ABS=1:
ABS mode OFF (normal)
ABS mode ON
ꢁ WLS register
WLS=0:
WLS =1:
8-bit data bus length
16-bit data bus length
ꢁ CKS register
CKS =0:
Internal oscillation
(The OSC1 terminal must be fixd “1” or “0”.)
External oscillation
CKS =1:
(By the external clock into the OSC1 or external resister between the OSC1 and
OSC2. OSC2 should be open when clock is inputted from OSC1.)
- 82 -
NJU6823
(32-20) EVR control
The “EVR control” instruction is used to fine-tune the LCD driving voltage (VLCD) so that it is possible to
optimize the contrast level for a LCD panel.
This instruction must be programmed by upper 3-bit data first, next lower 4-bit data. And it becomes
enabled when the lower 4-bit data is programmed, so that it can prevent unexpected high voltage for the
VLCD from being generated.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
0
DV3 DV2 DV1 DV0
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
1
D3
*
D2
D1
D0
0
1
1
0
1
0
0
DV6 DV5 DV4
DV6 DV5 DV4 DV3 DV2 DV1 DV0
VLCD
0
0
0
0
0
0
0
0
:
0
0
0
0
0
1
Low
:
:
:
:
1
1
1
1
1
1
1
High
The formula of the VLCD is shown below.
VLCD [V] = 0.5 x VREG + M (VREG – 0.5 x VREG) / 127
V
BA = VEE x 0.9
VBA
VREF
VREG
N
: Output voltage of the reference voltage generator
: Input voltage of the voltage regulator
: Output voltage of the voltage regulator
: Register value for the voltage booster
: Register value for the EVR
VREG = VREF x N
M
- 83 -
NJU6823
(32-21) Frequency control
The “Frequency control” instruction is used to control the frame frequency for a LCD panel.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
1
D3
*
D2
D1
D0
0
1
1
0
1
0
0
Rf2
Rf1
Rf0
Rfx register (x=0, 1, 2)
The “Rfx” register is used to determine the feed back resister value for the internal oscillator and it is
possible to adjust the frame frequency for the LCD modules.
Rf 2 Rf 1 Rf 0
Feedback resistor value
Reference value
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0.8 x reference value
0.9 x reference value
1.1 x reference value
1.2 x reference value
0.7 x reference value
1.3 x reference value
Inhibited
(32-22) Discharge ON/OFF
Discharge circuit is used to discharge the electric charge of the capacitors on the V1 to V4 and the VLCD
terminals. The “Discharge ON/OFF” instruction is usually required just after the internal power supply is turned
off by setting “0” into the “DCON” and “AMPON” registers, or just after the external power supply is turned off.
During the discharge operation, the internal or external power supply must not be turned on.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
1
D4
0
D3
*
D2
*
D1
D0
0
1
1
0
1
0
0
DIS2 DIS
DIS=0:
DIS=1:
Discharge OFF
Discharge ON
(Capacitors on the VLCD, V1, V2, V3 and V4)
(Capacitors on the VLCD, V1, V2, V3 and V4)
DIS2=0:
DIS2=1:
Discharge OFF
Discharge ON
(Resistance between VOUT and VEE)
(Resistance between VOUT and VEE)
Note ) VOUT and VEE are internally connected with the resistor (100kΩ typical) in the power-ON
.
- 84 -
NJU6823
(32-23) Instruction register address
The “Instruction register address” is used to specify the instruction register address, so that it is possible
to read out the contents of the instruction registers in combination with the “Instruction register read”
instruction.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
1
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
0
RA3 RA2 RA1 RA0
(32-24) Instruction register read
The “Instruction register read” instruction is used to read out the contents of the instruction register in
combination with the “Instruction register address” instruction.
CSb RS RDb WRb RE2 RE1 RE0
0/1 0/1 0/1
D7
*
D6
*
D5
*
D4
*
D3
D2
D1
D0
0
1
0
1
Internal register data read
(32-25) Window end column address
The “Window end column address” is used to specify the column address for the window end point. The
lower 4-bit data is required to be programmed first and then the upper 4-bit data can be programmed.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
1
EX3 EX2 EX1 EX0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
0
D4
1
D3
D2
D1
D0
0
1
1
0
1
0
1
EX7 EX6 EX5 EX4
(32-26) Window end row address set
The “Window end row address” is used to specify the row address for the window end point. The lower
4-bit data is required to be programmed first and then the upper 4-bit data can be programmed.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
1
EY3 EY2 EY1 EY0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
0
D5
1
D4
1
D3
*
D2
D1
D0
0
1
1
0
1
0
1
EY6 EY5 EY4
- 85 -
NJU6823
(32-27) Initial reverse line
The “Initial reverse line” instruction is used to specify the initial reverse line address for the reverse line
display. Lower 4-bit data must be programmed first, next upper 3-bit data. It is programmed in between
00H and 7FH and the line address beyond 7FH is inhibited. The address relation: LSi < LEi (i=7 to 0) must
be maintained in the reverse line display.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
1
LS3 LS2 LS1 LS0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
0
D4
1
D3
*
D2
D1
D0
0
1
1
0
1
0
1
LS6 LS5 LS4
(32-28) Last reverse line
The “Last reverse line” instruction is used to specify the last reverse line address for the reverse line
display. Lower 4-bit must be programmed first, next upper 3-bit data. It is programmed in between 00H and
7FH and the line address beyond 7FH is inhibited. The address relation: LSi < LEi (i=7 to 0) must be
maintained in the reverse line display.
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
0
D3
D2
D1
D0
0
1
1
0
1
0
1
LE3 LE2 LE1 LE0
CSb RS RDb WRb RE2 RE1 RE0
D7
0
D6
1
D5
1
D4
1
D3
*
D2
D1
D0
0
1
1
0
1
0
1
LE6 LE5 LE4
(32-29) Reverse line display ON/OFF
The “Reverse line display ON/OFF” is used to enable or disable the reverse line display for the blink
operation and determine the reverse line display mode.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
0
D3
*
D2
*
D1
D0
0
1
1
0
1
0
1
BT LREV
ꢁ LREV register
The “LREV” register is used to enable or disable the reverse line display.
LREV =0:
LREV =1:
Reverse line display OFF (Normal)
Reverse line display ON
- 86 -
NJU6823
ꢁ BT register
The “BT” register is used to determine the reverse line display mode in the reverse line display ON
(LREV=1) status.
BT =0:
BT =1:
Normal reverse line display
Blink once every 32 frames
Display examples in the LREV=”1” and BT=”1”
ꢂꢀꢀꢀꢂ
ꢀꢂꢂꢂꢀ
ꢀꢂꢂꢂꢂ
ꢂꢀꢀꢀꢂ
ꢂꢂꢂꢂꢀ
ꢀꢂꢂꢂꢀ
ꢂꢀꢀꢀꢂ
ꢂꢂꢂꢂꢂ
ꢀꢂꢂꢂꢀ
ꢂꢀꢀꢀꢂ
ꢂꢀꢀꢀꢀ
ꢀꢂꢂꢂꢀ
ꢀꢀꢀꢀꢂ
ꢂꢀꢀꢀꢂ
ꢀꢂꢂꢂꢀ
ꢀꢀꢀꢀꢀ
Blink once every 32 frames
NJRC
LCD DRIVER
Low Power and
Low Voltage
Blink once every 32 frames
NJRC
←Initial reverse line address
←Last reverse line address
LCD DRIVER
Low Power and
Low Voltage
- 87 -
NJU6823
(32-30) Gradation Palette setting control
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
0
D4
1
D3
*
D2
*
D1
D0
0
1
1
0
1
0
1
DMY PS
ꢁ PS register
PS=0: Lower 8 Gradation setting
PS=1: Upper 8 Gradation setting
ꢁ DMY register
Although segment drivers in normal condition output LCD driving voltage corresponding to data in
Display data RAM, Icon segment driver output LCD driving voltage corresponding to registers. The 24
bits register corresponds to SEGSA0 ~ SEGSA1, SEGSB0 ~ SEGSB1, SEGSC0 ~ SEGSC1.
DMY=0: Normal RAM access
DMY =1: Icon segment driver RAM access
- 88 -
NJU6823
(32-31) PWM control
The “PWM control” is used to determine the PWM type for segment waveforms, where the type can be
specified for each of the SEGAi, SEGBi and SEGCi (i=0-127) drivers.
CSb RS RDb WRb RE2 RE1 RE0
D7
1
D6
0
D5
1
D4
0
D3
D2
D1
D0
PWMS PWMA PWMB PWMC
0
1
1
0
1
0
1
ꢁ PWMS register
PWMS=0: Type 1
PWMS=1: Type 2
ꢁ PWMA, B and C registers
The “PWMA, PWMB and PWMC” registers are used to select the type 1-O or type 1-E.
PWMZ=0 (Z=A, B and C): Type 1-O
PWMZ=1 (Z=A, B and C): Type 1-E
PWM type1 (PWMS=”0”)
Odd line
Even line
“H”
“L”
CL
VLCD
V2
→
←
Type-O
Type-E
SEG
VLCD
V2
→
←
PWM type2 (PWMS=”1”)
“H”
CL
“L”
VLCD
V2
SEG
→
→
- 89 -
NJU6823
(33)The relationship between Common drivers and row addresses
Row address assignment of common drivers is programmed by the “ SHIFT ” register of the “ Display control
(1) ” , “ Duty cycle ratio ”, “ Internal display line ” and “ Initial COM line ” instructions.
ꢁ
ꢁ
When initial display line is “0”
If the “ SHIFT “ is “ 0 “, the scan direction is normal. When the “ LA0 to LA6 ” registers of the “ Initial
display line “instruction is “ 0 “, the “ MY “ corresponding to the initial COM line is “ 0 “ and is increasing
during display.
When initial display line is not “0”
If the “ SHIFT “ is “ 1 “, the scan direction is inversed. When the “ LA0 to LA6 ” registers of the “ Initial
display line “instruction is not “ 0 “, the “ MY “ corresponding to the initial COM line is this setting value and
is increasing during display.
The following are examples of setting the start-line 0 or 5 at 1/129, 1/128, or 1/17 duty.
- 90 -
NJU6823
(33-1) Initial display line “0”, 1/129 duty cycle (Common forward scan, DSE=”0”)
SHIFT=”0”(Common forward scan), DS3, 2
,
,
0=”0000”, LA6….LA0=”00000000”(Initial display line 0)
1
SC3
SC2
SC1
SC0
0000
0
0001
124
0010
120
0011
112
0100
104
0101
96
0110
88
0111
80
1000
72
1001
64
1010
56
1011
48
1100
40
1101
32
1110
24
1111
16
COM0
COM1
COM2
COM3
127
0
COM4
COM5
COM6
COM7
127
0
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
COM89
COM90
COM91
COM92
COM93
COM94
COM95
COM96
:
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
COM103
COM104
:
127
0
COM111
COM112
:
127
0
COM125
COM126
COM127
127
127
123
127
119
127
111
127
103
127
95
127
87
127
79
127
71
127
63
127
55
127
47
127
39
127
31
127
23
127
15
127
(129th COM period) *1
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 129th COM period is not selected.
- 91 -
NJU6823
(33-2) Initial display line “0”, 1/17 duty cycle (Common backward scan, DSE=”0”)
SHIFT=”0”(Common backward scan), DS3, 2, , 0=”1110”, LA6….LA0=”00000000”(Initial display line 0)
1
SC3
SC2
SC1
SC0
0000
0
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
:
0
0
15
0
15
15
0
15
0
15
0
15
0
15
0
15
0
15
0
15
0
15
0
COM95
COM96
:
15
0
COM103
COM104
:
15
0
COM111
COM112
:
15
0
COM119
:
15
15
COM127
15
15
(17th COM period) *1
15
15
15
15
15
15
15
15
15
15
15
15
15
15
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 17th COM period is not selected.
- 92 -
NJU6823
(33-3) Initial display line “0”, 1/129 duty cycle (Common backward scan, DSE=”0”)
SHIFT=”1”(Common backward scan), DS3, 2
,
,
0=”0000”, LA6….LA0=”00000000”(Initial display line 0)
1
SC3
SC2
SC1
SC0
0000
127
0001
123
0010
119
0011
111
0100
103
0101
95
0110
87
0111
79
1000
71
1001
63
1010
55
1011
47
1100
39
1101
31
1110
23
1111
15
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
:
COM15
COM16
:
0
127
COM23
COM24
:
0
127
COM31
COM32
:
0
127
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
COM89
COM90
COM91
COM92
COM93
COM94
COM95
COM96
COM97
COM98
COM99
COM100
COM101
COM102
COM103
COM104
COM105
COM106
COM107
COM108
COM109
COM110
COM111
COM112
COM113
COM114
COM115
COM116
COM117
COM118
COM119
COM120
COM121
COM122
COM123
COM124
COM125
COM126
COM127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
124
127
120
127
112
127
104
127
96
127
88
127
80
127
72
127
64
127
56
127
48
127
40
127
32
127
24
127
16
127
(129th COM period) *1
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 129th COM period is not selected.
- 93 -
NJU6823
(33-4) Initial display line “5”, 1/129 duty cycle (Common forward scan, DSE=”0”)
SHIFT=”0”(Common forward scan), DS3, 2
,
,
0=”0000”, LA6….LA0=”00000101”(Initial display line 5)
1
SC3
SC2
SC1
SC0
0000
5
0001
1
0010
0011
117
0100
109
0101
101
0110
93
0111
85
1000
77
1001
69
1010
61
1011
53
1100
45
1101
37
1110
29
1111
21
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
:
125
126
127
0
5
5
127
0
5
127
0
5
127
0
5
127
0
5
127
0
5
127
0
5
127
0
5
127
0
5
127
0
COM80
COM81
COM82
COM83
:
COM88
COM89
COM90
COM91
:
COM96
COM97
COM98
COM99
:
COM104
COM105
COM106
COM107
:
5
127
0
5
127
0
5
127
0
5
127
0
COM112
:
5
COM122
COM123
COM124
COM125
COM126
COM127
127
0
:
127
0
127
4
127
124
127
116
127
108
127
100
127
92
127
84
127
76
127
68
127
60
127
52
127
44
127
38
127
28
127
20
127
(129th COM period) *1
DS: Duty cycle ratio, SC: Initial COM line, LA: Initial display line
*1 : 129th COM period is not selected.
- 94 -
NJU6823
(33-5) Initial display line “0”, 1/128 duty cycle (Common forward scan, DSE=”1”)
SHIFT=”0”(Common forward scan), DS3, 2
,
,
0=”0000”, LA6….LA0=”00000000”(Initial display line 0) DSE=”1”
1
SC3
SC2
SC1
SC0
0000
0
0001
124
0010
120
0011
112
0100
104
0101
96
0110
88
0111
80
1000
72
1001
64
1010
56
1011
48
1100
40
1101
32
1110
24
1111
16
COM0
COM1
COM2
COM3
127
0
COM4
COM5
COM6
COM7
127
0
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COM80
COM81
COM82
COM83
COM84
COM85
COM86
COM87
COM88
COM89
COM90
COM91
COM92
COM93
COM94
COM95
COM96
:
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
127
0
COM103
COM104
:
127
0
COM111
COM112
:
COM125
COM126
COM127
127
0
127
123
119
111
79
71
63
55
47
39
31
23
15
DS: Duty cycle ratio, SC: Initial COM line, LA: Initi1a0l3 displ9a5y line87
- 95 -
NJU6823
ꢀ ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage (1)
Supply Voltage (2)
Supply Voltage (3)
Supply Voltage (4)
Supply Voltage (5)
Supply Voltage (6)
Input Voltage
SYMBOL
VDD
CONDITION
TERMINAL
VDD
RATING
-0.3 to +4.0
UNIT
V
VEE
VEE
-0.3 to +4.0
V
VOUT
VOUT
-0.3 to +19.0
-0.3 to +19.0
-0.3 to +19.0
-0.3 to VLCD + 0.3
-0.3 to VDD + 0.3
-45 to +125
V
VSS=0V
VREG
VREG
V
Ta = +25°C
VLCD
VLCD
V
V1, V2, V3, V4
VI
V1, V2, V3, V4
*1
V
V
Storage Temperature
Tstg
°C
Note 1) D0 to D15, CSb, RS, RDb, WRb, OSC1, RESb, TEST1, TEST2, terminals.
Note 2) To stabilize the voltage booster operation, decoupling capacitors must be connected between the
VDD and VSS pins and between the VEE and VSSH pins.
ꢀ
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply Voltage
SYMBOL
VDD1
TERMINAL
VDD
MIN
1.7
2.4
2.4
5
TYP
MAX
3.3
UNIT
V
NOTE
*1
VDD2
3.3
V
*2
VEE
VEE
VLCD
VOUT
VREG
VREF
3.3
V
*3
*4
VLCD
18.0
18.0
OUT × 0.9
3.3
V
VOUT
VREG
VREF
V
Operating Voltage
V
V
2.1
-30
V
*5
Operating
Topr
85
°C
Temperature
Note1) Applies to the condition when the reference voltage generator is not used.
Note2) Applies to the condition when the reference voltage generator is used.
Note3) Applies to the condition when the voltage booster is used.
Note4) The following relationship among the supply voltages must be maintained.
VSS<V4<V3<V2<V1<VLCD<VOUT
Note5) The relationship: VREF<VEE must be maintained.
- 96 -
NJU6823
ꢀ DC CHARACTERISTICS 1
VSS = 0V, VDD = +1.7 to +3.3V, Ta = -30 to +85°C
SYM
PARAMETER
BOL
CONDITION
MIN
TYP
MAX
UNIT NOTE
VIH
VIL
VOH1
VOL1
VOH2
VOL2
ILI
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Input leakage current
0.8 VDD
0
VDD
V
V
*1
*1
*2
*2
*3
*3
*4
*5
0.2VDD
IOH = -0.4mA
VDD - 0.4
V
IOL = 0.4mA
0.4
V
IOH = -0.1mA
IOL = 0.1mA
VI = VSS or VDD
VI = VSS or VDD
VDD - 0.4
V
0.4
10
10
2
4
15
710
160
22.9
V
-10
-10
µA
µA
ILO
Output leakage current
VLCD = 10V
VLCD = 6V
VDD = 3V
1
2
RON1
Driver ON-resistance
*6
|∆VON| = 0.5V
kΩ
µA
ISTB
*7
CSb=VDD, Ta=25°C
Stand-by current
fOSC1
fOSC2
fOSC3
fr1
fr2
fr3
490
110
15.9
600
135.5
19.4
575
135
19.6
*8
*9
*10
VDD = 3V
Internal oscillation
Frequency
kHz
Ta = 25°C
Rf=12kΩ
Rf=62kΩ
Rf=470kΩ
External oscillation
Frequency
kHz
V
*11
*12
N-time booster (N=2 to 6)
Voltage converter
output voltage
(N x VEE
)
VOUT
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
VBA
x 0.95
RL = 500kΩ (VOUT - VSS
)
VDD = 3V, 6-time booster
Whole ON pattern
Supply current (1)
Supply current (2)
Supply current (3)
Supply current (4)
Supply current (5)
Supply current (6)
VBA Operating voltage
760
930
1140
1400
780
VDD = 3V, 6-time booster
Checker pattern
VDD = 3V, 5-time booster
Whole ON pattern
520
*13
µA
VDD = 3V, 5-time booster
Checker pattern
650
980
VDD = 3V, 4-time booster
Whole ON pattern
360
540
VDD = 3V, 4-time booster
Checker pattern
450
680
(0.9 VEE
)
(0.9 VEE
)
VEE = 2.4 to 3.3V
VEE = 2.4 to 3.3V
0.9 VEE
V
V
*14
*15
x 0.98
x 1.02
(VREF x N)
x 0.97
(VREF x N)
x 1.03
VREG
(VREF x N)
VREG Operating voltage
VREF = 0.9 x VEE
N-time booster (N=2 to 6)
V2
V3
VD12
VD34
VD24
-100
-100
-30
-30
-30
0
0
0
0
0
+100
+100
+30
+30
+30
Output Voltage
mV
*16
- 97 -
NJU6823
ꢀ CLOCK and FRAME FREQUENCY
Display duty cycle ratio (1/D) <DSE=0>
1/73 to 1/41 1/33 to 1/25
PARAMETER SYMBOL
NOTE
FLM
Display mode
1/128 to 1/81
fOSC / (62xD)
1/17
16 Gradation mode
fOSC / (62xDx2) fOSC / (62xDx4) fOSC / (62xDx8)
fOSC / (14xDx2) fOSC / (14xDx4) fOSC / (14xDx8)
Internal
fOSC
Simplified
f
OSC / (14xD)
OSC / (2xD)
fCK / (62xD)
CK / (14xD)
CK / (2xD)
clock
8 gradation mode
B&W mode
f
fOSC / (2xDx2)
fCK / (62xDx2)
fCK / (14xDx2)
fCK / (2xDx2)
fOSC / (2xDx4)
fCK / (62xDx4)
fCK / (14xDx4)
fCK / (2xDx4)
fOSC / (2xDx8)
fCK / (62xDx8)
fCK / (14xDx8)
fCK / (2xDx8)
16 Gradation mode
External
fCK
Simplified
f
clock
8 gradation mode
B&W mode
f
- 98 -
NJU6823
APPLIED TERMINALS and CONDITIONS
Note 1)
Note 2)
Note 3)
Note 4)
Note 5)
D0-D15, CSb, RS, RDb, WRb, P/S, SEL68, RESb
D0-D15
CL, FLM, FR, CLK
CSb, RS, SEL68, RDb, WRb, P/S, RESb, OSC1
D0-D15 in the high impedance
Note 6)
SEGA0-SEGA127, SEGB0-SEGB127, SEGC0-SEGC127, COM0-COM127 and
SEGSA0-SEGSA1, SEGSB0-SEGSB1, SEGSC0-SEGSC1
- Defines the resistance between the COM/SEG terminals and the power supply terminals (VLCD
,
V1, V2, V3 and V4) at the condition of 0.5V deference and 1/9 LCD bias ratio.
Note 7)
Note 8)
VDD
- The oscillator is halted, CSb=”1” (disabled), No-load onto the segment and common drivers
OSC
- Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the variable gradation
mode.
Note 9)
OSC
- Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the fixed gradation mode.
Note 10)
OSC
- Defines the internal oscillation frequency at (Rf2, Rf1, Rf0)=(0,0,0) in the Black & White mode.
Note 11)
Note 12)
VDD=3V, Ta=25°C
VOUT
- Applies to the condition when the internal voltage booster, the internal oscillator and the
internal power circuits are used.
- VEE=2.4V to 3.3V, EVR= (1,1,1,1,1,1,1), 1/5 to 1/12 LCD bias, 1/129 duty cycle, No-load on
COM/SEG drivers.
- RL=500KΩ between the VOUT and the VSS, CA1=CA2=1.0uF, CA3=0.1uF, DCON=”1”,
AMPON=”1”
Note 13)
VDD
- Applies to the condition using the internal oscillator and internal power circuits, no access
between the LSI and MPU.
- EVR= (1,1,1,1,1,1,1), All pixels turned-on or checkerboard display in gradation mode. No-load
on the COM/SEG drivers.
- VDD=VEE, VREF=0.9VEE, CA1=CA2=1.0uF, CA3=0.1uF, DCON=”1”, AMPON=”1”, NLIN=”0”, 1/129
Duty cycle, Ta=25°C
Note 14)
Note 15)
VBA
- Applies to the condition that VBA=VREF and voltage booster N= 1. DCON=”0”, VOUT=13.5V input.
VREG
- VEE=2.4V to 3.3V, VREF=0.9VEE, VOUT=18V, 1/5 to 1/12 LCD bias ratio, 1/129 duty cycle,
EVR=(1,1,1,1,1,1,1)
- Checkerboard display, No-load on the COM/SEG drivers, the voltage booster N=2 to 6,
V1A1, V1A2, V4A1, V4A2 = “0”. CA1=CA2=1.0uF, CA3=0.1uF, DCON=”0”, AMPON=”1”, NLIN=”0”
VLCD, V1, V2, V3, V4
Note 16)
- VEE=3.0V, VREF=0.9VEE, VOUT=15V, 1/5 to 1/12 LCD Bias, EVR= (1,1,1,1,1,1,1), Display OFF,
No-load on the COM/SEG drivers, voltage booster N=5, V1A1, V1A2, V4A1, V4A2 = “0”.
CA1=CA2=1.0uF, CA3=0.1uF, DCON=”0”, AMPON=”1”
VLCD
(1)
(2)
VD12: (1)-(2)
VD34: (3)-(4)
VD24: (2)-(4)
V1
V2
V3
V4
VSS
(3)
(4)
- 99 -
NJU6823
ꢀ AC CHARACTERISTICS
•
Write operation (80-type MPU)
tAS8
tAH8
CSb
RS
WRb
tWRLW8
tWRHW8
tDS8
tDH8
D0 to D15
tCYC8
MIN.
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
PARAMETER
SYMBOL CONDITION
MAX.
UNIT
TERMINAL
Address hold time
tAH8
0
ns
CSb
Address setup time
tAS8
0
ns
RS
System cycle time
tCYC8
90
35
35
ns
ns
ns
Enable ”L” level pulse width
Enable ”H” level pulse width
tWRLW8
WRb
tWRHW8
Data setup time
Data hold time
tDS8
tDH8
30
5
ns
ns
D0 to D15
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
tAH8
0
ns
CSb
Address setup time
tAS8
0
ns
RS
System cycle time
tCYC8
160
70
ns
ns
ns
Enable ”L” level pulse width
Enable ”H” level pulse width
tWRLW8
WRb
tWRHW8
70
Data setup time
Data hold time
tDS8
tDH8
40
5
ns
ns
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
tAH8
0
ns
CSb
Address setup time
tAS8
0
ns
RS
System cycle time
tCYC8
180
80
ns
ns
ns
Enable ”L” level pulse width
Enable ”H” level pulse width
tWRLW8
WRb
tWRHW8
80
Data setup time
tDS8
70
ns
ns
D0 to D15
Data hold time
tDH8
10
Note) Each timing is specified based on 20% and 80% of VDD.
- 100 -
NJU6823
•
Read operation (80-type MPU)
tAS8
tAH8
CSb
RS
tWRLR8
RDb
tWRHR8
tRDH8
D0 to D15
tRDD8
tCYC8
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
tAH8
0
ns
CSb
Address setup time
tAS8
0
ns
RS
System cycle time
tCYC8
tWRLR8
tWRHR8
180
80
ns
ns
ns
Enable ”L” level pulse width
Enable ”H” level pulse width
RDb
80
Read Data delay time
Read Data hold time
TRDD8
TRDH8
60
ns
ns
CL=15pF
D0 to D15
0
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
tAH8
0
ns
CSb
Address setup time
tAS8
0
ns
RS
System cycle time
tCYC8
tWRLR8
tWRHR8
180
80
ns
ns
ns
Enable ”L” level pulse width
Enable ”H” level pulse width
RDb
80
Read Data delay time
Read Data hold time
TRDD8
60
ns
ns
CL=15pF
TRDH8
D0 to D15
0
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
tAH8
0
ns
CSb
Address setup time
tAS8
0
ns
RS
System cycle time
tCYC8
tWRLR8
tWRHR8
250
120
120
ns
ns
ns
Enable ”L” level pulse width
Enable ”H” level pulse width
RDb
Read Data delay time
tRDD8
110
ns
ns
CL=15pF
tRDH8
D0 to D15
Read Data hold time
0
Note) Each timing is specified based on 20% and 80% of VDD.
- 101
NJU6823
•
Write operation (68-type MPU)
tAS6
tAH6
CSb
RS
R/W
tELW6
tEHW6
E
tDS6
tDH6
D0 to D15
tCYC6
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
tAH6
0
ns
CSb
Address setup time
tAS6
0
ns
RS
System cycle time
tCYC6
tELW6
tEHW6
90
35
35
ns
ns
ns
Enable ”L” level pulse width
Enable ”H” level pulse width
E
Data setup time
Data hold time
tDS6
tDH6
40
5
ns
ns
D0 to D15
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
tAH6
0
ns
CSb
Address setup time
tAS6
0
ns
RS
System cycle time
tCYC6
tELW6
tEHW6
160
70
ns
ns
ns
Enable ”L” level pulse width
Enable ”H” level pulse width
E
70
Data setup time
Data hold time
tDS6
tDH6
50
5
ns
ns
D0 to D15
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
tAH6
0
ns
CSb
Address setup time
tAS6
0
ns
RS
System cycle time
tCYC6
tELW6
tEHW6
180
80
ns
ns
ns
Enable ”L” level pulse width
Enable ”H” level pulse width
E
80
Data setup time
tDS6
70
ns
ns
D0 to D15
Data hold time
tDH6
10
Note) Each timing is specified based on 20% and 80% of VDD.
- 102 -
NJU6823
•
Read operation (68-type MPU)
tAS6
tAH6
CSb
RS
R/W
(WRb)
tELR6
tEHR6
E
(RDb)
tRDH6
D0 to D15
tRDD6
tCYC6
MIN.
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
CONDITION
MAX.
UNIT
TERMINAL
Address hold time
tAH6
0
ns
CSb
RS
Address setup time
tAS6
0
ns
System cycle time
tCYC6
tELR6
tEHR6
180
80
ns
ns
ns
Enable ”L” level pulse width
Enable ”H” level pulse width
E
80
Read Data delay time
Read Data hold time
tRDD6
tRDH6
ns
ns
70
CL=15pF
D0 to D15
0
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
tAH6
0
ns
CSb
Address setup time
tAS6
0
ns
RS
System cycle time
tCYC6
tELR6
tEHR6
180
80
ns
ns
ns
Enable ”L” level pulse width
Enable ”H” level pulse width
E
80
Read Data delay time
Read Data hold time
tRDD6
tRDH6
ns
ns
70
CL=15pF
D0 to D15
0
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
PARAMETER
SYMBOL
CONDITION
MIN.
MAX.
UNIT
TERMINAL
Address hold time
tAH6
0
ns
CSb
Address setup time
tAS6
0
ns
RS
System cycle time
tCYC6
tELR6
tEHR6
250
120
120
ns
ns
ns
Enable ”L” level pulse width
Enable ”H” level pulse width
E
Read Data delay time
tRDD6
ns
ns
110
CL=15pF
D0 to D15
0
Read Data hold time
tRDH6
Note) Each timing is specified based on 20% and 80% of VDD.
- 103
NJU6823
•
Serial interface
tCSH
tCSS
CSb
RS
tASS
tAHS
tSLW
tSHW
SCL
tCYCS
tDSS
tDHS
SDA
(VDD=2.5 to 3.3V, Ta=-30 to +85°C)
UNIT
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
TERMINAL
Serial clock cycle
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
50
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
SCL
RS
SDA
Data hold time
CSb – SCL time
CSb hold time
tCSS
20
ns
CSb
tCSH
20
ns
(VDD=2.2 to 2.5V, Ta=-30 to +85°C)
UNIT
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
TERMINAL
Serial clock cycle
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
50
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
SCL
RS
SDA
Data hold time
CSb – SCL time
CSb hold time
tCSS
20
ns
CSb
tCSH
20
ns
(VDD=1.7 to 2.2V, Ta=-30 to +85°C)
UNIT
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
TERMINAL
Serial clock cycle
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
80
35
35
35
35
35
35
ns
ns
ns
ns
ns
ns
ns
SCL ”H” level pulse width
SCL ”L” level pulse width
Address setup time
Address hold time
Data setup time
SCL
RS
SDA
Data hold time
CSb – SCL time
tCSS
35
ns
CSb
tCSH
35
ns
CSb hold time
Note) Each timing is specified based on 20% and 80% of VDD.
- 104 -
NJU6823
•
Display control timing
CLK
tDCL
CL
tDFLM
tDFLM
FLM
tFR
FR
Output timing
PARAMETER
FLM delay time
FR delay time
CL delay time
(VDD=2.4 to 3.3V, Ta=-30 to +85°C)
SYMBOL CONDITION
tDFLM CL=15pF
MIN.
MAX.
500
UNIT
ns
ns
TERMINAL
FLM
0
0
0
tFR
500
200
FR
tDCL
ns
CL
Output timing
(VDD=1.7 to 2.4V, Ta=-30 to +85°C)
PARAMETER
SYMBOL CONDITION
tDFLM CL=15pF
MIN.
MAX.
1000
1000
200
UNIT
ns
TERMINAL
FLM
FLM delay time
FR delay time
CL delay time
0
0
0
tFR
ns
FR
tDCL
ns
CL
Note) Each timing is specified based on 20% and 80% of VDD.
- 105
NJU6823
•
Input clock timing
tCKLW
tCKHW
OSC1
(VDD=1.7 to 3.3V, Ta=-30 to +85°C)
UNIT
PARAMETER
SYMBOL CONDITION
MIN.
MAX.
1.02
1.02
4.55
4.55
31.4
31.4
TERMINAL
OSC1
OSC1 “H” level pulse width (1)
OSC1 “L” level pulse width (1)
OSC1 “H” level pulse width (2)
OSC1 “L” level pulse width (2)
OSC1 “H” level pulse width (3)
OSC1 “L” level pulse width (3)
tCKHW1
tCKLW1
tCKHW2
tCKLW2
tCKHW3
tCKLW3
0.70
0.70
3.13
3.13
21.8
21.8
µs
µs
µs
µs
µs
µs
1
OSC1
2
OSC1
3
Note) Each timing is specified based on 20% and 80% of VDD.
Note 1) Applied to the variable gradation mode / MON=”0”,PWM=”0”
Note 2) Applied to the fixed gradation mode / MON=”0”,PWM=”1”
Note 3) Applied to the B&W mode / MON=”1”
- 106 -
NJU6823
•
Reset input timing
RESb
tRW
tR
Internal circuit
status
During reset
End of reset
(VDD=2.4 to 3.3V, Ta=-30 to +85°C)
UNIT
PARAMETER
SYMBOL CONDITION
MIN.
10.0
MAX.
Terminal
Reset time
tR
1.0
µs
µs
RESb “L” level pulse width
tRW
RESb
(VDD=1.7 to 2.4V, Ta=-30 to +85°C)
UNIT
PARAMETER
Reset time
SYMBOL CONDITION
MIN.
10.0
MAX.
Terminal
tR
1.5
µs
µs
RESb “L” level pulse width
tRW
RESb
Note) Each timing is specified based on 20% and 80% of VDD.
- 107
NJU6823
•
Typical characteristic
PARAMETER
Basic delay time of gate
SYMBOL
Ta=+25°C, VSS=0V, VDD=3.0V
MIN
TYP
10
MAX
UNIT
ns
•
Input output terminal type
(a) Input circuit
VDD
Terminals:
CSb, RS, RDb, WRb, SEL68,
P/S, RESb
I
Input signal
VSS(0V)
(b) Output circuit
Terminals:
FLM, CL, FR, CLK
VDD
Output control signal
Output signal
O
VSS(0V)
(c) Input/Output circuit
VDD
Terminals:
D0 to D15
Input signal
VSS(0V)
VSS(0V)
Input control signal
VDD
Output control signal
Output signal
VSS(0V)
- 108 -
NJU6823
(d) Display output circuit
VLCD
VLCD
VLCD
V1/V2
Output control
signal 1
Output control signal 2
Output control signal 4
O
Output control
signal 3
VSS(0V)
V3/V4
VSS(0V)
VSS(0V)
Terminals:
SEGA0 to SEGA127
SEGB0 to SEGB127
SEGC0 to SEGC127
COM0 to COM127
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NJU6823
ꢀ APPLICATION CIRCUIT EXAMPLES
(1) MPU Connections
80-type MPU interface
1.7V to 3.3V
VCC
VDD
0
RS
A1 to A7
(80-type MPU)
IORQb
Decoder
8
7
CSb
D0 to D7
D0 to D7
RDb
WRb
RDb
WRb
RESb
RESb
VSS
GND
RESET
68-type MPU interface
1.7V to 3.3V
VCC
VDD
0
RS
A1 to A15
(68-type MPU)
Decoder
8
15
CSb
D0 to D7
E
D0 to D7
R/W
RESb
RESb
VSS
GND
RESET
Serial interface
1.7V to 3.3V
VCC
VDD
0
1 7
RS
Decoder
RESET
7
CSb
PORT1
PORT2
RESb
SCL
RESb
VSS
GND
- 110 -
NJU6823
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 111
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