UT61L12816 [ETC]
ASYNCHRONOUS STATIC RAM- High Speed ; 异步静态RAM-高速\n
| 型号： | UT61L12816 |
| 厂家： | 
ETC |
| 描述： | ASYNCHRONOUS STATIC RAM- High Speed
|
| 文件： | 总8页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UTRON
UT61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
REVISION HISTORY
REVISION
DESCRIPTION
Date
Preliminary Rev. 0.1 Original.
Oct.25,2002
May.20,2003
Rev. 1.0
1. Revised Standby current : 10/2mA(max)ꢀ0.5mA(typ.)
2. Delete ICC1, ICC2
3. Revised ISB : 30mAꢀ3mA, ISB1:10mAꢀ2mA,
4. Add ISB & ISB1 (typ.) : 1mA & 2mA
5. Add Overshoot : VIH ≤ +6.0V for t ≤ tRC /2.
Undershoot : VIL ≤ -2.0V for t ≤ tRC /2.
6. Revised Data retention IDR (max) : 3mAꢀ1Ma
7. Add order information for lead free product
UTRON TECHNOLOGY INC.
P80081
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
1
UTRON
UT61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
FEATURES
GENERAL DESCRIPTION
The UT61L12816 is a 2,087,152-bit high speed
CMOS static random access memory organized
as 131,072 words by 16 bits. It is fabricated using
high performance and high reliability CMOS
technology.
ꢁ Fast access time : 10/12/15ns
ꢁ CMOS Low operating power
Operating current :
260/240/220 mA (Icc max.)
Standby current : 0.5 mA (typ.)
ꢁ Single 3.0V~3.6V power supply
ꢁ Operating temperature :
The UT61L12816 operates from a single 3.0V ~
3.6V power supply and all inputs and outputs are
fully TTL compatible.
℃
℃
Commercial : 0 ~70
ꢁ All TTL compatible inputs and outputs
ꢁ Fully static operation
ꢁ Three state outputs
It is designed to allow lower and upper byte
、
LB UB
。
)
access by data byte control (
ꢁData retention voltage : 2V (min.)
ꢁ Data byte control :
(I/O1~I/O8)
LB
(I/O9~I/O16)
UB
II
ꢁ Package : 44-pin 400mil TSOP-
FUNCTIONAL BLOCK DIAGRAM
×
128K 16
MEMORY
ARRAY
A0-A16
DECODER
Vcc
Vss
I/O1-I/O8
Lower Byte
I/O DATA
CIRCUIT
COLUMN I/O
I/O9-I/O16
Upper Byte
CE
OE
WE
LB
CONTROL
CIRCUIT
UB
UTRON TECHNOLOGY INC.
P80081
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
UTRON
UT61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
PIN CONFIGURATION
PIN DESCRIPTION
SYMBOL
A0 - A16
I/O1 - I/O16
DESCRIPTION
Address Inputs
A5
A6
A4
A3
A2
A1
A0
1
44
2
3
43
42
A7
OE
UB
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Lower-Byte Control
4
41
40
39
5
6
CE
WE
OE
LB
LB
CE
7
8
9
I/O16
I/O1
38
37
I/O15
I/O2
I/O3
I/O4
Vcc
Vss
I/O5
I/O6
36
35
34
I/O14
I/O13
Vss
10
11
Upper-Byte Control
Power Supply
Ground
UB
VCC
VSS
NC
12
13
Vcc
33
32
I/O12
I/O11
14
15
31
No Connection
I/O10
I/O9
I/O7
I/O8
WE
30
29
16
17
28
27
NC
A8
18
A16
A15
A14
A13
A12
19
20
26
25
A9
A10
A11
21
22
24
23
NC
TSOP II
TRUTH TABLE
I/O OPERATION
SUPPLY
CURRENT
MODE
OE
UB
CE
WE LB
I/O1-I/O8
High – Z
High – Z
High – Z
High – Z
DOUT
I/O9-I/O16
H
X
L
L
L
L
L
L
L
L
X
X
H
H
L
L
L
X
X
X
X
X
H
H
H
H
H
L
X
H
L
X
L
H
L
L
X
H
X
L
H
L
L
H
L
High – Z
High – Z
High – Z
High – Z
High – Z
DOUT
Standby
ISB, ISB1
Output Disable
ICC
ICC
Read
Write
High – Z
DOUT
DOUT
DIN
High – Z
DIN
High – Z
DIN
L
L
H
L
ICC
L
DIN
Note: H = VIH, L=VIL, X = Don't care.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80081
3
UTRON
UT61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
VTERM
TA
RATING
-0.5 to 4.6
0 to 70
-65 to 150
1
UNIT
V
℃
Terminal Voltage with Respect to VSS
Operating Temperature
Storage Temperature
℃
TSTG
Power Dissipation
PD
W
mA
℃
DC Output Current
IOUT
50
Soldering Temperature (under 10 secs)
Tsolder
260
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect
device reliability.
℃
(TA = 0 to 70
℃
)
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Power Voltage
Input High Voltage
SYMBOL TEST CONDITION
MIN. TYP. MAX. UNIT
Vcc
3.0
2.0
-0.3
- 1
- 1
2.4
-
3.3
-
-
3.6
VCC+0.3
0.8
1
V
V
V
*1
VIH
VIL
*2
Input Low Voltage
-
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
ILI
≦
≦
A
µ
VSS VIN VCC
-
ILO
≦
≦
1
-
A
µ
VSS VI/O VCC; Output Disabled
VOH
VOL
IOH= -4mA
IOL= 8mA
-
-
-
V
V
mA
mA
mA
mA
0.4
260
240
220
3
-10
-12
-15
Cycle time=min, 100%duty,
Operating Power
Supply Current
ICC
ISB
-
-
1
I/O=0mA,
=V
IL
CE
Standby Current (TTL)
-
-
=VIH, other pins =VIL or VIH
CE
CE
=V -0.2V, other pins at 0.2V or
CC
0.5
2
mA
Standby Current (CMOS) ISB1
Vcc-0.2V
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 8ns.
2. Undershoot : Vss-3.0v for pulse width less than 8ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON TECHNOLOGY INC.
P80081
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
4
UTRON
UT61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
℃
CAPACITANCE (TA=25 , f=1.0MHz)
PARAMETER
Input Capacitance
SYMBOL
MIN.
-
-
MAX
6
8
UNIT
pF
pF
CIN
CI/O
Input/Output Capacitance
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
3ns
1.5V
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
CL = 30pF, IOH/IOL = -4mA / 8mA
℃
(TA =0 to 70
℃
AC ELECTRICAL CHARACTERISTICS
)
(1) READ CYCLE
UT61L12816-15
UT61L12816-10 UT61L12816-12
PARAMETER
SYMBOL
UNIT
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
tRC
10
-
-
10
10
5
12
-
-
12
12
6
15
-
-
15
15
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
Chip Enable Access Time
tACE
tOE
-
-
-
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
-
-
-
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
3
0
-
-
3
0
-
-
3
0
-
-
-
-
-
5
6
7
-
5
-
6
-
7
3
-
-
3
-
-
3
-
-
,
Access Time
tBA
5
6
7
LB UB
,
to High-Z Output
to Low-Z Output
tBHZ*
tBLZ*
-
5
-
-
6
-
-
7
-
ns
ns
LB UB
,
0
0
0
LB UB
(2) WRITE CYCLE
UT61L12816-12 UT61L12816-15
UT61L12816-10
PARAMETER
SYMBOL
UNIT
MIN.
10
8
MAX.
MIN.
12
9
MAX.
MIN.
15
10
10
0
MAX.
Write Cycle Time
tWC
tAW
tCW
tAS
-
-
-
-
-
-
-
-
-
5
-
-
-
-
-
-
-
-
-
-
6
-
-
-
-
-
-
-
-
-
-
7
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
8
9
0
0
Write Pulse Width
tWP
tWR
tDW
tDH
8
9
10
0
Write Recovery Time
0
0
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
6
7
8
0
0
0
tOW*
tWHZ*
tBW
3
3
3
-
-
-
,
Valid to End of Write
8
9
10
LB UB
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
P80081
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
5
UTRON
UT61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
(1,2)
tRC
Address
tAA
tOH
tOH
Previous data valid
Dout
Data Valid
READ CYCLE 2 (
and
Controlled)
OE
(1,3,4,5)
CE
tRC
Address
CE
tAA
tACE
tBA
LB , UB
OE
tBHZ
tBLZ
tCHZ
tOE
tCLZ
tOLZ
tOHZ
tOH
Dout
High-Z
High-Z
Data Valid
Notes :
1.
is high for read cycle.
WE
2.Device is continuously selected
=low,
=low,
CE
or
LB UB
=low.
or
OE
3.Address must be valid prior to or coincident with
=low,
=low transition; otherwise tAA is the limiting parameter.
±
CE
LB UB
4.tCLZ, tBLZ, tOLZ, tCHZ, tBHZ and tOHZ are specified with CL=5pF. Transition is measured 500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ, tBHZ is less than tBLZ, tOHZ is less than tOLZ
.
UTRON TECHNOLOGY INC.
P80081
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
6
UTRON
UT61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
WRITE CYCLE 1 (
Controlled)
(1,2,3,5,6)
WE
tWC
Address
CE
tAW
tCW
tAS
tWP
tWR
WE
tBW
LB , UB
tWHZ
(4)
tOW
tDH
High-Z
Dout
Din
(4)
tDW
Data Valid
WRITE CYCLE 2 (
Controlled)
(1,2,5,6)
CE
tWC
Address
tAW
CE
tWR
tAS
tCW
tWP
WE
tBW
LB , UB
tWHZ
High-Z
(4)
Dout
Din
tDW
tDH
Data Valid
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80081
7
UTRON
UT61L12816
128K X 16 BIT HIGH SPEED CMOS SRAM
Rev. 1.0
WRITE CYCLE 3 (
,
Controlled)
(1,2,5,6)
LB UB
tWC
Address
tAW
CE
tAS
tCW
tWR
tWP
WE
LB , UB
Dout
tBW
tWHZ
High-Z
tDW
tDH
Din
Data Valid
Notes :
1.
,
,
,
must be high during all address transitions.
WE CE LB UB
2.A write occurs during the overlap of a low
, low
,
or
=low.
CE
OE
WE LB UB
3.During a
controlled write cycle with
low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to
WE
be placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the low transition occurs simultaneously with or after low transition, the outputs remain in a high impedance
,
,
CE LB UB
state.
WE
±
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
UTRON TECHNOLOGY INC.
P80081
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
8
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