MB39A136PFT-E1_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS04-27262-4E

ASSP for Power Management Applications

(General-Purpose DC/DC Converter)

2ch PFM/PWM DC/DC converter IC

with synchronous rectification

MB39A136

■ DESCRIPTION

MB39A136 is 2ch step-down DC/DC converter IC of the current mode N-ch/N-ch synchronous rectification

method. It contains the enhanced protection features, and supports the symmetrical-phase method and the

ceramic capacitor. MB39A136 realizes rapid response, high efficiency, and low ripple voltage, and its high-

frequency operation enables the miniaturization of inductors and I/O capacitors.

■ FEATURES

• High efficiency

• For frequency setting by external resistor

• Error Amp threshold voltage

• Minimum output voltage value

: 100 kHz to 1 MHz

: 0.7 V 1.0%

: 0.7 V

• Wide range of power-supply voltage

: 4.5 V to 25 V

• PFM/PWM auto switching mode and fixed PWM mode selectable

• Supports Symmetrical-Phase method

• With built-in over voltage protection function

• With built-in under voltage protection function

• With built-in over current protection function

• With built-in over-temperature protection function

• With built-in soft start/stop circuit without load dependence

• With built-in synchronous rectification type output steps for N-ch MOS FET

• Standby current

• Small package

: 0 [μA] Typ

: TSSOP-24

■ APPLICATION

• Digital TV

• Photocopiers

• Surveillance cameras

• Set-top boxes (STB)

• DVD players, DVD recorders

• Projectors

• IP phones

• Vending machine

• Consoles and other non-portable devices

2013.1

MB39A136

■ PIN ASSIGNMENT

(TOP VIEW)

CTL1

CS1

1

2

24

23

22

21

20

19

18

17

16

15

14

13

CB1

DRVH1

LX1

FB1

3

COMP1

ILIM1

RT

4

DRVL1

VCC

5

6

VB

VREF

CTL2

ILIM2

COMP2

FB2

7

GND

DRVL2

LX2

8

9

10

11

12

DRVH2

CB2

CS2

MODE

(FPT-24P-M09)

2

DS04-27262-4E

MB39A136

■ PIN DESCRIPTION

Pin No.

Symbol

CTL1

CS1

I/O

Description

1

2

I

CH1 control pin.

CH1 soft-start time setting capacitor connection pin.

CH1 Error amplifier inverted input pin.

CH1 error amplifier output pin.

3

FB1

I

4

COMP1

ILIM1

RT

O

I

5

CH1 over current detection level setting voltage input pin.

Oscillation frequency setting resistor connection pin.

Reference voltage output pin.

6

⎯

O

I

7

VREF

CTL2

ILIM2

COMP2

FB2

8

CH2 control pin.

9

I

CH2 over current detection level setting voltage input pin.

CH2 error amplifier output pin.

10

11

12

O

I

CH2 Error amplifier inverted input pin.

CH2 soft-start time setting capacitor connection pin.

CS2

I

PFM/PWM switch pin. (CH1 and CH2 commonness) It becomes fixed

PWM operation with the VREF connection, and it becomes PFM/PWM

operation with the GND connection.

13

MODE

I

14

15

16

17

18

19

20

21

22

23

24

CB2

DRVH2

LX2

⎯

O

CH2 connection pin for boot strap capacitor.

CH2 output pin for external high-side FET gate drive.

CH2 inductor and external high-side FET source connection pin.

CH2 output pin for external low-side FET gate drive.

Ground pin.

⎯

O

DRVL2

GND

⎯

O

VB

Bias voltage output pin.

VCC

⎯

O

Power supply pin for reference voltage and control circuit.

CH1 output pin for external low-side FET gate drive.

CH1 inductor and external high-side FET source connection pin.

CH1 output pin for external high-side FET gate drive.

CH1 connection pin for boot strap capacitor.

DRVL1

LX1

⎯

O

DRVH1

CB1

⎯

DS04-27262-4E

3

MB39A136

■ BLOCK DIAGRAM

MODE

RT

VCC

13

6

20

<CH1>

<Soft-Start,

Soft-Stop>

VREF

Clock

generator

ctl1

VB

Bias

Reg.

5.5

μA

/uvp_out

19

24

+

pfm1

CS1

/otp_out

−

pfm2

2

/uvlo

ovp_out

2.0 V

70 kΩ

ch.1

ch.2

COMP1

FB1

CB1

180° out of phase

4

3

Hi-side

Drive

DRVH1

LX1

23

22

−

+

RS-FF

R Q

Drive

Logic

+

S

intref

VB

CLK

ILIM1

DRVL1

5

21

Lo-side

Drive

Level

Converter

Vs

−

+

−

+

−

+

intref

x 1.15 V

intref

x 0.7 V

ovp1

uvp1

<UVLO>

ovp_out

uvp_out

VB

ovp1

ovp2

50 μs

S Q

R

UVLO

delay

uvlo

VREF

UVLO

uvp1

uvp2

512/f^OSC

delay

S Q

R

H:UVLO

release

otp_out

OTP

CB2

<CH2>

CS2

14

12

The configuration of a control circuit is the same as that of CH1.

DRVH2

LX2

15

16

COMP2

FB2

10

11

DRVL2

17

VB

ctl1, ctl2

ILIM2

9

ON/OFF

CTL1

CTL2

(3.3 V)

1

8

intref

7

18

GND

VREF

4

DS04-27262-4E

MB39A136

■ ABSOLUTE MAXIMUM RATINGS

Rating

Parameter

Symbol

Conditions

VCC pin

Unit

Min

⎯

Max

27

Power-supply voltage

CB pin input voltage

LX pin input voltage

V^VCC

V^CB

V

CB1, CB2 pins

LX1, LX2 pins

⎯

32

V^LX

27

Voltage between CB and LX

Control input voltage

V^CBLX

V^I

7

CTL1, CTL2 pins

FB1, FB2 pins

ILIM1, ILIM2 pins

CS1, CS2 pins

MODE pin

27

V^FB

VVREF + 0.3

VVB + 0.3

V^ILIM

V^CSx

V^MODE

Input voltage

DC DRVL1, DRVL2 pins,

DRVH1, DRVH2 pins

Output current

I^OUT

⎯

60

mA

Power dissipation

P^D

Ta ≤ + 25 °C

⎯

1644

mW

Storage temperature

T^STG

⎯

− 55

+ 150

°C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

DS04-27262-4E

5

MB39A136

■ RECOMMENDED OPERATING CONDITIONS

Value

Typ

⎯

Parameter

Symbol

Conditions

Unit

Min

Max

Power supply voltage

V^VCC

V^CB

⎯

4.5

25.0

V

CB pin

input voltage

⎯

30

Reference voltage

output current

I^VREF

⎯

− 100

⎯

μA

Bias output current

I^VB

V^I

⎯

CTL1, CTL2 pins

FB1, FB2 pins

ILIM1, ILIM2 pins

CS1, CS2 pins

MODE pin

− 1

0

⎯

mA

V

CTL pin input voltage

25

V^FB

0

VVREF

1.94

VVREF

V

V^ILIM

V^CS

V^MODE

0.3

0

V

Input voltage

V

0

V

DRVH1, DRVH2 pins

DRVL1, DRVL2 pins

Duty ≤ 5% (t = 1/f^OSC× Duty)

Peak output current

I^OUT

− 1200

⎯

+ 1200

mA

Operation frequency

range

f^OSC

⎯

100

500

1000

kHz

Timing resistor

R^RT

C^CS

C^CB

RT pin

⎯

0.0075

⎯

47

0.0180

0.1

⎯

kΩ

μF

Soft start capacitor

CB pin capacitor

CS1, CS2 pins

CB1, CB2 pins

1.0

Reference voltage

output capacitor

C^VREF

C^VB

Ta

VREF pin

VB pin

⎯

0.1

2.2

1.0

10

μF

°C

Bias voltage output

capacitor

Operating ambient

temperature

− 30

+ 25

+ 85

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

onthedatasheet.Usersconsideringapplicationoutsidethelistedconditionsareadvisedtocontact

their representatives beforehand.

6

DS04-27262-4E

MB39A136

■ ELECTRICAL CHARACTERISTICS

(Ta = + 25 °C, VCC pin = 15 V, CTL pin = 5 V, VREF pin = 0 A, VB pin = 0A)

Value

No.

Parameter

Output voltage

Symbol

Conditions

Unit

Min

Typ

Max

V^VREF

7

⎯

3.24

3.30

3.36

V

VREF

LINE

Input stability

Load stability

7

VCC pin = 4.5 V to 25 V

⎯

1

10

mV

Reference

Voltage

Block

VREF

LOAD

VREF pin = 0 A to

− 100 μA

mV

[REF]

Short-circuit out-

put current

VREF

IOS

7

VREF pin = 0 V

⎯

− 14.5 − 10.0 − 7.5 mA

Output voltage

V^VB

19

4.85

5.00

10

5.15

100

V

VB

LINE

Input stability

VCC pin = 6 V to 25 V

⎯

mV

Bias Voltage

Block

[VB Reg.]

VB

LOAD

Load stability

19

VB pin = 0 A to − 1 mA

VB pin = 0 V

⎯

10

100

mV

Short-circuit out-

put current

VB

IOS

− 200 − 140 − 100 mA

V^TLH1

V^THL1

V^H1

19

7

VB pin

4.0

3.4

⎯

4.2

3.6

4.4

3.8

⎯

V

Threshold voltage

Hysteresis width

VB pin

Under volt-

age Lockout

Protection

Circuit Block

[UVLO]

VB pin

0.6*

2.9

V^TLH2

V^THL2

V^H2

VREF pin

2.7

2.5

⎯

3.1

2.9

⎯

Threshold

voltage

7

2.7

Hysteresis width

Charge current

7

0.2*

CTL1, CTL2 pins = 5 V,

CS1, CS2 pins = 0 V

I^CS

2, 12

− 7.9 − 5.5 − 4.2

μA

Soft-start

end voltage

Soft-start /

Soft-stop

Block

[Soft-Start,

Soft-Stop]

V^CS

2, 12 CTL1, CTL2 pins = 5 V

2.2

49

2.4

70

2.6

91

V

Electrical dis-

charge resistance

at soft-stop

CTL1, CTL2 pins = 0 V,

2, 12

R^DISCG

kΩ

CS1, CS2 pins = 0.5 V

Soft-stop

end voltage

V^DISCG

f^OSC

2, 12 CTL1, CTL2 pins = 0 V

⎯

0.1*

500

⎯

V

Oscillation

frequency

6

RT pin = 47 kΩ

450

550

kHz

Oscillation

Clock

Generator

Block

frequency when

under voltage is

detected

f^SHORT

df/dT

⎯

62.5

3*

⎯

kHz

[OSC]

Frequency

Temperature

variation

6

Ta = − 30 °C to + 85 °C

⎯

%

(Continued)

DS04-27262-4E

7

MB39A136

(Ta = + 25 °C, VCC pin = 15 V, CTL pin = 5 V, VREF pin = 0 A, VB pin = 0 A)

Value

Typ

0.693 0.700 0.707

No.

Parameter

Symbol

Conditions

Unit

Min

Max

EV^TH

EV^THT

I^FB

3, 11

⎯

V

Threshold

voltage

3, 11 Ta = − 30 °C to + 85 °C 0.689* 0.700* 0.711*

Input current

3, 11 FB1, FB2 pins = 0 V

− 0.1

0

+ 0.1 μA

FB1, FB2 pins = 0 V,

4, 10 COMP1, COMP2 pins =

1 V

I^SOURCE

− 390 − 300 − 210 μA

Error Amp

Block

[Error Amp1,

Error Amp2]

Output current

FB1, FB2 pins =

VREF pin,

COMP1, COMP2 pins =

1 V

I^SINK

4, 10

8.4

12.0

16.8 mA

Output clamp

voltage

FB1, FB2 pins = 0 V,

4, 10

V^ILIM

I^ILIM

1.35

1.50

0

1.65

V

ILIM1, ILIM2 pins = 1.5 V

ILIM pin

input current

FB1, FB2 pins = 0 V,

5, 9

− 1

+ 1

μA

ILIM1, ILIM2 pins = 1.5 V

Over-voltage

detecting

voltage

Over-voltage

Protection

Circuit Block

[OVP Comp.]

V^OVP

3, 11 FB1, FB2 pins

0.776 0.805 0.835

V

μs

V

Over-voltage

detection time

t^OVP

3, 11

⎯

49

70

91

Under-voltage

detecting

voltage

Under-voltage

Protection

Circuit Block

[UVP Comp.]

V^UVP

3, 11 FB1, FB2 pins

0.450 0.490 0.531

512/

Under-voltage

detection time

t^UVP

3, 11

⎯

s

f^OSC

Over-tempera-

T^OTPH

⎯

Junction temperature

+ 160*

°C

ture Protection Detection

Circuit Block

[OTP]

temperature

T^OTPL

⎯

Junction temperature

⎯

+ 135*

⎯

°C

Synchronous

rectification stop

voltage

V^THLX

V^PFM

V^PWM

I^MODE

22, 16 LX1, LX2 pins

13 MODE pin

⎯

0

0*

⎯

0

⎯

1.4

mV

V

PFM/PWM

mode condition

PFM Control

Circuit Block

(MODE)

Fixed PWM

mode

condition

13 MODE pin

2.2

− 1

VVREF

V

MODE pin input

current

13 MODE pin = 0 V

+ 1

μA

(Continued)

8

DS04-27262-4E

MB39A136

(Ta = + 25 °C, VCC pin = 15 V, CTL pin = 5 V, VREF pin = 0 A, VB pin = 0 A)

Value

No.

Parameter

Symbol

Conditions

Unit

Min

Typ

Max

DRVH1, DRVH2 pins =

− 100 mA

R^ON_MH

R^ON_ML

R^ON_SH

R^ON_SL

23, 15

⎯

4

7

Ω

High-side

output

on-resistance

DRVH1, DRVH2 pins =

100 mA

23, 15

21, 17

⎯

1.0

4

3.5

7

DRVL1, DRVL2 pins =

− 100 mA

Low-side

output

on-resistance

DRVL1, DRVL2 pins =

100 mA

0.75

1.70

LX1, LX2 pins = 0 V,

CB1, CB2 pins = 5 V

Output source

current

23, 15, DRVH1, DRVH2 pins,

21, 17 DRVL1, DRVL2 pins =

2.5 V

I^SOURCE

⎯

− 0.5*

⎯

A

Duty ≤ 5%

Output Block

[DRV]

LX1, LX2 pins = 0 V,

CB1, CB2 pins = 5 V

23, 15 DRVH1, DRVH2 pins =

2.5 V

⎯

0.9*

1.2*

⎯

A

Duty ≤ 5%

Output sink

current

I^SINK

LX1, LX2 pins = 0 V,

CB1, CB2 pins = 5 V

21, 17 DRVL1, DRVL2 pins =

2.5 V

Duty ≤ 5%

Minimum on

time

COMP1, COMP2 pins =

t^ON

D^MAX

t^D

23, 15

1 V

⎯

75

⎯

250*

80

⎯

ns

%

Maximum

on-duty

23, 15 FB1, FB2 pins = 0 V

23, 21, LX1, LX2 pins = 0 V,

15, 17 CB1, CB2 pins = 5 V

Dead time

60

ns

Maximum

current sense

voltage

V^RANGE

22, 16 VCC pin − LX1, LX2 pins

⎯

5.4

⎯

220*

6.8

⎯

8.2

⎯

mV

V/V

mV

Voltage

conversion

gain

A^LV

22, 16

⎯

Level

Converter

Block

Offset voltage

at voltage

conversion

V^IO

300

[LVCNV]

Slope

compensation SLOPE 22, 16

inclination

⎯

2*

⎯

V/V

LX pin

input current

I^LX

22, 16 LX1, LX2 pins = VCC pin 320

420

600

μA

(Continued)

DS04-27262-4E

9

MB39A136

(Continued)

(Ta = + 25 °C, VCC pin = 15 V, CTL pin = 5 V, VREF pin = 0 A, VB pin = 0 A)

Value

No.

Parameter

Symbol

Conditions

Unit

Min

2

Typ

⎯

Max

25

ON condition

OFF condition

Control Block Hysteresis

[CTL1, CTL2] width

V^ON

1, 8 CTL1, CTL2 pins

V

V^OFF

0

⎯

0.8

V^H

1, 8 CTL1, CTL2 pins

⎯

0.4*

⎯

V

I^CTLH

I^CTLL

1, 8 CTL1, CTL2 pins = 5 V

1, 8 CTL1, CTL2 pins = 0 V

⎯

25

0

40

1

μA

Input current

Standby

current

I^CCS

20

CTL1, CTL2 pins = 0 V

⎯

0

10

μA

General

LX1, LX2 pins = 0 V,

FB1, FB2 pins = 1.0 V,

MODE pin = VREF pin

Power-supply

current

I^CC

20

⎯

3.3

4.7

mA

* : This value is not be specified. This should be used as a reference to support designing the circuits.

10

DS04-27262-4E

MB39A136

■ TYPICAL CHARACTERISTICS

• Typical data

Power dissipation

Power dissipation vs. Operating ambient temperature

2000

1800

1600

1400

1200

1000

800

1644

600

400

200

0

−50

−25

0

+25

+50

+75

+100

+125

Operating ambient temperature Ta ( °C)

VREF bias voltage vs.

Error Amp threshold voltage vs.

Operating ambient temperature

3.36

3.34

3.32

3.3

0.71

0.705

0.7

CH1

CH2

3.28

3.26

3.24

VCC = 15 V

fosc = 500 kHz

VCC = 15 V

fosc = 500 kHz

0.695

0.69

-40

-20

0

+20

+40

+60

+80 +100

-40

-20

0

+20 +40 +60

+80 +100

Operating ambient temperature Ta ( °C)

(Continued)

DS04-27262-4E

11

MB39A136

(Continued)

Oscillation frequency vs.

Operating ambient temperature

Dead time vs.

Operating ambient temperature

90

80

70

60

50

40

30

505

500

495

490

485

480

475

VCC = 15 V

fosc = 500 kHz

tD2

tD1

-40

-20

0

+20 +40 +60 +80 +100

-40

-20

0

+20

+40

+60

+80 +100

Operating ambient temperature Ta ( °C)

Operating ambient temperature Ta( °C)

t^D1: period from DRVL off to DRVH on

t^D2: period from DRVH off to DRVL on

Oscillation frequency vs. Timing resistor value

VB bias voltage vs. VB bias output current

1000

6

5.5

VCC = 6 V

VCC = 15 V

Ta = + 25°C

5

4.5

VCC = 5 V

4

3.5

3

VCC = 4.5 V

fosc = 500 kHz

Ta = + 25°C

2.5

2

100

-0.025 -0.02 -0.015 -0.01 -0.005

0

10

100

1000

Timing resistor value RRT (kΩ)

VB bias output current IVB (A)

Maximum duty cycle vs.

Power supply voltage

Maximum duty cycle vs.

Operating ambient temperature

80

79

78

77

76

75

80

79

78

77

76

75

VCC = 15 V

fosc = 500 kHz

Ta = + 25°C

CH2

CH1

CH2

CH1

0

10

20

30

-40

-20

0

+20 +40 +60 +80 +100

Power supply voltage VVCC (V)

Operating ambient temperature Ta ( °C)

12

DS04-27262-4E

MB39A136

■ FUNCTION DESCRIPTION

1. Current Mode

It uses the current waveform from the switching (Q1) as a control waveform to control the output voltage, as

described below:

1 : The clock (CK) from the internal clock generator (OSC) sets RS-FF and turns on the high-side FET.

2 : Turning on the high-side FET causes the inductor current (IL) rise. Generate Vs that converts this current

into the voltage.

3 : The current comparator (I Comp.) compares this Vs with the output (COMP) from the error amplifier

(Error Amp) that is negative-feedback from the output voltage (Vo).

4 : When I Comp. detects that Vs exceeds COMP, it resets RS-FF and turns off high-side FET.

5 : The clock (CK) from the clock generator (OSC) turns on the high-side FET again.

Thus, switching is repeated.

Operate so that the FB electrical potential may become INTREF electrical potential, and stabilize the output

voltage as a feedback control.

VIN

DRVH

Q1

FB

−

+

RS-FF

−

Current

Sense

R

Drive

Logic

COMP

Q

+

IL

VO

S

INTREF

CK

DRVL

Q2

OSC

Vs

Rs

1

4

5

OSC(CK)

IL

3

COMP

Vs

2

t

off

DRVH

t

on

DS04-27262-4E

13

MB39A136

(1) Reference Voltage Block (REF)

The reference voltage circuit (REF) generates a temperature-compensated reference voltage (3.3 [V] Typ)

using the voltage supplied from the VCC pin. The voltage is used as the reference voltage for the IC's internal

circuit. The reference voltage can be used to supply a load current of up to 100 μA to an external device

through the VREF pin.

(2) Bias Voltage Block (VB Reg.)

Bias Voltage Block (VB Reg.) generates the reference voltage used for IC’s internal circuit, using the voltage

supplied from the VCC pin. The reference voltage is a temperature-compensated stable voltage (5 [V] Typ)

to supply a current of up to 100 mA through the VB pin.

(3) Under Voltage Lockout Protection Circuit Block (UVLO)

The circuit protects against IC malfunction and system destruction/deterioration in a transitional state or a

momentary drop when a bias voltage (VB) or an internal reference voltage (VREF) starts. It detects a voltage

drop at the VB pin or the VREF pin and stops IC operation. When voltages at the VB pin and the VREF pin

exceed the threshold voltage of the under voltage lockout protection circuit, the system is restored.

(4) Soft-start/Soft-stop Block (Soft-Start, Soft-Stop)

Soft-start

It protects a rush current or an output voltage (V^Ox) from overshooting at the output start. Since the lamp

voltage generated by charging the capacitor connecting to the CSx pin is used for the reference voltage of

the error amplifier (Error Amp), it can set the soft-start time independent of a load of the output (V^Ox). When

the IC starts with “H” level of the CTLx pin, the capacitor at the CSx pin (CS) starts to be charged at 5.5 μA.

The output voltage (V^Ox) during the soft-start period rises in proportion to the voltage at the CSx pin generated

by charging the capacitor at the CSx pin.

During the soft-start with 0.8 V > voltage at CS1 and CS2 pins, operations are as follows:

• Fixed PWM operation only (fixed PWM even if MODE pin is set to “L”)

• Over-voltage protection function and under-voltage protection function are invalid.

Soft-stop

It discharges electrical charges stored in a smoothing capacitor at output stop. Setting the CTLx pin to “L”

level starts the soft-stop function independent of a load of output (Vox). Since the capacitor connecting to

the CSx pin starts to discharge through the IC-built-in soft-stop discharging resistance (70 [kΩ] Typ) when

the CTLx pin sets at “L” level enters its lamp voltage into the error amplifier (Error Amp), the soft-stop time

can be set independent of a load of output (V^Ox). When discharging causes the voltage at the CSx pin to

drop below 100 mV (Typ), the IC shuts down and changes to the stand-by state. In addition, the soft-stop

function operates after the under-voltage protection circuit block (UVP Comp.) is latched or after the over-

temperature protection circuit block (OTP) detects over-temperature.

During the soft-stop with, 0.8 V > voltage at CS1 and CS2 pins, operations are as follows:

• Fixed PWM operation only (fixed PWM even if MODE pin is set to “L”)

• Over-voltage protection function and under-voltage protection function are invalid.

(5) Clock Generator Block (OSC)

The clock generator has the built-in oscillation frequency setting capacitor and generates a clock that

180°phase shifted from each channel by connecting the oscillation frequency setting resistor to the RT pin

(Symmetrical-Phase method).

14

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MB39A136

(6-1) Error Amp Block (Error Amp1, Error Amp2)

The error amplifiers (Error Amp1 and Error Amp2) detect the output voltage from the DC/DC converter and

output to the current comparators (I Comp.1 and I Comp.2). The output voltage setting resistor externally

connected to FB1 and FB2 pins allows an arbitrary output voltage to be set.

In addition, since an external resistor and an external capacitor serially connected between COMP1 and

FB1 pins and between COMP2 and FB2 pins allow an arbitrary loop gain to be set, it is possible for the

system to compensate a phase stably.

(6-2) Over Current Detection (Protection) Block (ILIM)

It is the current detection circuit to restrict an output current (I^OX). The over current detection block (ILIM)

compares an output waveform of the level converter of each channel (see “(12) Level Converter Block

(LVCNV)”) with the ILIMx pin voltage in every cycle. As a load resistance (R^OX) drops, a load current (IOX)

increases. Therefore, theoutputwaveformofthelevelconverterexceedstheILIMpinvoltageofeachchannel.

At this time, the output current can be restricted by turning off FET on the high-side and suppressing a peak

value of the inductor current.

As a result, the output voltage (V^OX) should drop.

Furthermore, if the output voltage drops and the electrical potential at the FBx pin drops below 0.3 V, the

oscillation frequency (f^OSC) drops to 1/8.

(7) Over-voltage Protection Circuit Block (OVP Comp.)

The circuit protects a device connecting to the output when the output voltage (V^Ox) rises.

It compares 1.15 times (Typ) of the internal reference voltage (INTREF) (0.7 V) that is non-inverting-entered

into the error amplifier with the feedback voltage that is inverting-entered into the error amplifier and if it

detects the state where the latter is higher than the former by 50 μs (Typ). It stops the voltage output by

setting the RS latch, setting the DRVHx pin to “L” level, setting the DRVLx pin to “H” level, turning off the

high-side FETs, and turning on the low-side FETs.

The conditions below cancel the protection function:

• Setting CTL1 and CTL2 to “L”.

• Setting the power supply voltage below the UVLO threshold voltage (V^THL1and VTHL2).

(8) Under-voltage Protection Circuit Block (UVP Comp.)

It protects a device connecting to the output by stopping the output when the output voltage (V^OX) drops.

It compares 0.7 times (Typ) of the internal reference voltage (INTREF) (0.7 V) that is non-inverting-entered

into the error amplifier with the feedback voltage that is inverting-entered into the error amplifier and if it

detects the state where the latter is lower than the former by 512/fosc [s](Typ), it stops the voltage output for

both channels by setting the RS latch.

The conditions below cancel the protection function:

• Setting CTL1 and CTL2 to “L”.

• Setting the power supply voltage below the UVLO threshold voltage (V^THL1and VTHL2).

(9) Over temperature Protection Circuit Block (OTP)

The circuit protects an IC from heat-destruction. If the temperature at the joint part reaches +160 °C, the

circuit stops the voltage output for both channels by discharging the capacitor connecting to the CSx pin

through the soft-stop discharging resistance (70 [kΩ] Typ) in the IC.

In addition, if the temperature at the joint part drops to +135 °C, the output restarts again through the soft-

start function.

Make sure to design the DC/DC power supply system so that the over temperature protection does not start

frequently.

DS04-27262-4E

15

MB39A136

(10) PFM Control Circuit Block (MODE)

It sets the control mode of the IC and makes control at automatic PFM/PWM switching.

MODE pin connection

Control mode

Features

Automatic PFM/PWM

switching

“L” (GND)

Highly-efficient at light load

Stable oscillation frequency

Stable switching ripple voltage

Excellent in rapid load change characteristic at

heavy load to light load

“H” (VREF)

Fixed PWM

Automatic PFM/PWM switching mode operation

It compares the LX1 pin and the LX2 pin voltages with GND electrical potential at Di Comp. In the comparison,

the negative voltage at the LX pin causes the low-side FET to set on, positive voltage causes it to set off (Di

Comp. method) . As a result, the method restricts the back flow of the inductor current at a light load and

makes the switching of the inductor current discontinuous (DCM) . Such an operation allows the oscillation

frequency to drop, resulting in high efficiency at a light load.

(11) Output Block (DRV)

The output circuit is configured in CMOS type for both of the high-side and the low-side, allowing the external

N-ch MOS FET to drive.

(12) Level Converter Block (LVCNV)

Thecircuitdetectsandconvertsthecurrentwhenthehigh-sideFETturnson. Itconvertsthevoltagewaveform

between drain side (VCC pin voltage) and the source side (LX1 and LX2 pin voltage) on the high-side FET

into the voltage waveform for GND reference.

Note: x : Each channel number

(13) Control Block (CTL1, CTL2)

The circuit controls on/off of the output from the IC.

Control function table

DC/DC converter

(V^O1)

DC/DC converter

(VO2)

CTL1

CTL2

Remarks

L

H

L

OFF

ON

OFF

ON

Standby

⎯

H

OFF

ON

H

ON

16

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MB39A136

■ PROTECTION FUNCTION TABLE

The following table shows the state of each pin when each protection function operates.

Output of each pin after detection

DC/DC output

dropping opera-

tion

Detection

Protection Function

condition

VREF

VB

DRVHx

DRVLx

Under Voltage Lock Out

Protection

(UVLO)

VB < 3.6 V

VREF < 2.7 V

Self-discharge by

load

< 2.7 V

< 3.6 V

L

Electricaldischarge

by soft-stop func-

tion

Under Voltage Protection

(UVP)

FBx < 0.49 V

3.3 V

5 V

L

Over Voltage Protection

(OVP)

FBx > 0.805 V

H

0 V clamping

The output voltage

is dropping to keep

constant output cur-

rent.

Over Current Protection

(ILIM)

COMPx > ILIMx

3.3 V

5V

switching switching

Over Temperature

Protection

(OTP)

Tj > + 160 °C

3.3 V

5 V

L

Electricaldischarge

by soft-stop func-

tion

CONTROL

(CTL)

CTLx : H→L

(CSx > 0.1 V)

Note: x is the each channel number

DS04-27262-4E

17

MB39A136

■ I/O PIN EQUIVALENT CIRCUIT DIAGRAM

VREF pin

CTL1, CTL2 pins

VB

VCC

CTL1,CTL2

VREF

ESD protection element

GND

VB pin

CS1, CS2 pins

VCC

VREF

VB

CS1,CS2

GND

FB1, FB2 pins

COMP1, COMP2 pins

VREF

FB1,FB2

COMP1,

COMP2

GND

(Continued)

18

DS04-27262-4E

MB39A136

(Continued)

ILM1, ILM2 pins

RT pin

VREF

VB

ILIM1,ILIM2

RT

GND

MODE pin

CB1, CB2, DRVH1, DRVH2, LX1, LX2 pins

CB1,CB2

VREF

MODE

GND

VREF

DRVH1,

DRVH2

LX1,LX2

DRVL1, DRVL2 pins

GND

VB

DRVL1,DRVL2

GND

DS04-27262-4E

19

MB39A136

■ EXAMPLE APPLICATION CIRCUIT

R21

VREF

MODE

V

IN

C13

RT

VCC

(4.5 V to 25 V)

13

6

20

MB39A136

VB

19

24

CS1

C7

<CH1>

2

A

D2

VO1

Q1

L1

COMP1

CB1

4

3

C5

R8-1

R8-2

R23

C9

DRVH1

LX1

FB1

23

22

R9

R11

R12

Q1

C2-1

C2-2

C2-3

ILIM1

DRVL1

5

21

C1

C14

B

D2

VO2

Q2

L2

CB2

CS2

14

<CH2>

12

C6

B

C8

DRVH2

LX2

15

16

COMP2

R25

10

11

C11

R14-1

R14-2

FB2

Q2

C4-1

C4-2

C4-3

DRVL2

17

R15

C3-1

C3-2

R17

ILIM2

R18

9

1 CTL1

8

CTL2

7

18

GND

VREF

C15

20

DS04-27262-4E

MB39A136

■ PARTS LIST

Compo-

nent

Item

Specification

Vendor

Package

Parts Name

Remark

VDS = 30 V,

ID = 8 A,

Dual type

(2 elements)

Q1

N-ch FET

RENESAS

SO-8

μPA2755

Ron = 21 mΩ

VDS = 30 V,

ID = 8 A,

Ron = 21 mΩ

Dual type

(2 elements)

Q2

RENESAS

SO-8

VF = 0.35 V

at IF = 0.2 A

D2

L1

Diode

ON Semi SOT-323 BAT54AWT1

Dual type

1.5 μH

(6.2 mΩ, 8.9 A)

Inductor

TDK

⎯

VLF10040T-1R5N

3.3 μH

L2

Inductor

TDK

⎯

VLF10045T-3R3N

C3225JC1E226M

(9.7 mΩ, 6.9 A)

C1

Ceramic capacitor

22 μF (25 V)

3225

C2-1

C2-2

C2-3

Ceramic capacitor

22 μF (10 V)

TDK

3216

C3216JB1A226M

3 capacitors

in parallel

C3-1

C3-2

Ceramic capacitor

22 μF (25 V)

TDK

3225

C3225JC1E226M 2 capacitors

C3225JC1E226M in parallel

C4-1

C4-2

C4-3

Ceramic capacitor

22 μF (10 V)

TDK

3216

C3216JB1A226M

3 capacitors

C3216JB1A226M

in parallel

C3216JB1A226M

C5

C6

Ceramic capacitor

0.1 μF (50 V)

TDK

1608

C1608JB1H104K

C1608JB1H223K

C1608CH1H821J

C1608CH1H102J

C1608JB1H103K

C1608JB1C225K

C1608JB1H104K

C7

Ceramic capacitor 0.022 μF (50 V)

C8

C9

Ceramic capacitor

820 pF (50 V)

1000 pF (50 V)

0.01 μF (50 V)

2.2 μF (16 V)

0.1 μF (50 V)

C11

C13

C14

C15

R8-1

R8-2

1.6 kΩ

9.1 kΩ

SSM

1608

RR0816P162D

RR0816P912D

2 capacitors

in series

Resistor

R9

Resistor

15 kΩ

56 kΩ

47 kΩ

SSM

1608

RR0816P153D

RR0816P563D

RR0816P473D

R11

R12

R14-1

R14-2

1.8 kΩ

39 kΩ

SSM

1608

RR0816P182D

RR0816P393D

2 capacitors

in series

Resistor

R15

11 kΩ

SSM

1608

RR0816P113D

(Continued)

DS04-27262-4E

21

MB39A136

(Continued)

Compo-

Item

Specification

Vendor

Package

Parts Name

Remark

nent

R17

R18

R21

R23

R25

Resistor

56 kΩ

82 kΩ

22 kΩ

56 kΩ

SSM

1608

RR0816P563D

RR0816P823D

RR0816P223D

RR0816P563D

RENESAS : Renesas Electronics Corporation

ON Semi : ON Semiconductor

TDK

SSM

: TDK Corporation

: SUSUMU Co.,Ltd.

22

DS04-27262-4E

MB39A136

■ APPLICATION NOTE

Setting method for PFM/PWM and fixed PWM modes

For the setting method for each mode, see“■ FUNCTION DESCRIPTION (10) PFM Control Circuit Block

(MODE)”.

Cautions at PFM/PWM mode

If a load current drops rapidly because of rapid load change and others, it tends to take a lot of time to restore

overshooting of an output voltage.

As a result, the over-voltage protection may operate.

In this case, solution are possible by the addition of the load resistance of value to be able to restore the

output voltage in the over-voltage detection time.

Setting method of output voltage

Set it by adjusting the output voltage setting zero-power resistance ratio.

R1 + R2

V^O=

× 0.7

R2

V^O

: Output setting voltage [V]

R1, R2 : Output setting resistor value [Ω]

VO

R1

FB1

FB2

R2

Make sure that the setting does not exceed the maximum on-duty.

Calculate the on-duty by the following formula:

V^O+ RON_Sync × IOMAX

D^MAX_Min=

VIN − RON_Main × IOMAX + RON_Sync × IOMAX

DMAX_Min : Minimum value of the maximum on-duty cycle

V^IN

V^O

: Power supply voltage of switching system [V]

: Output setting voltage [V]

R^ON_Main: High-side FET ON resistance [Ω]

R^ON_Sync: Low-side FET ON resistance [Ω]

I^OMAX

: Maximum load current[A]

DS04-27262-4E

23

MB39A136

Oscillation frequency setting method

Set it by adjusting the RT pin resistor value.

1.09

12

f^OSC=

9

R^RT× 40 × 10 − + 300 × 10 −

RRT

: RT resistor value [Ω]

: Oscillation frequency [Hz]

f^OSC

The oscillation frequency must set for on-time (t^ON) to become 300ns or more.

Calculate the on-time by the following formula.

V^O

t^ON=

VIN × fOSC

tON

V^IN

V^O

: On-time [s]

: Power supply voltage of switching system [V]

: Output setting voltage [V]

: Oscillation frequency [Hz]

f^OSC

24

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Setting method of soft-start time

Calculate the soft-start time by the following formula.

t^S= 1.4 × 10⁵× CCS

ts

: Soft-start time[s] (Time to becoming output 100%)

: CS pin capacitor value [F]

C^CS

Calculate delay time until the soft-start beginning by the following formula.

t^d1= 30 × CVB + 290 × CVREF + 1.455 × 10⁴× CCS

t^d1

: Delay time including VB voltage and VREF voltage starts [s]

C^CS

C^VB

C^VREF

: CS pin capacitor value [F]

: VB pin capacitor value [F]

: VREF pin capacitor value [F] (0.1 [μF] Typ)

Calculate delay time for starting while one channel has already started (UVLO released : VB, VREF output

before) by the following formula.

t^d2= 1.455 × 10⁴× CCS

t^d2

: Delay time for starting while one channel has already started [s]

C^CS

: CS pin capacitor value [F]

Calculate the discharge time at the soft-stop by the following formula.

t^dis= 1.44 × 10⁵× CCS

t^dis

: Discharge time [s]

C^CS

: CS pin capacitor value [F]

In addition, calculate the delay time to the discharge starting by the following formula.

t^d3= 7.87 × 10⁴× CCS

t^d3

: Delay time until discharge start [s]

C^CS

: CS pin capacitor value [F]

ts

t

dis

CTL1

CTL2

VO1

VO2

t

d2

td1

td3

DS04-27262-4E

25

MB39A136

• Simultaneous operation of plural channels

Soft-start/soft-stop operation according to the same timing as two channels can be achieved by even con-

necting it as shown in the figure below at the power supply on/off.

<Connection example 1> When you adjust the soft-start time

Make the CS capacitor common. Connect CTL1 and CTL2.

Note: In this case, the soft-start time (ts), the discharge time (tdis), and the delay time (td1, td2, td3) decrease

in the half value of compared with when CS capacitor is connected to each channel.

DC/DC 1 : Vo = 1.2 V setting

CS1

V

< DC/DC 2 >

1.8 V

< DC/DC 1 >

Vo

MB39A136

1.2 V

CTL

CTL1

CTL2

CTL

CS2

CS

capacitor

t

DC/DC 2 : Vo = 1.8 V setting

26

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Setting method of over current detection value

It is possible to set over-current detection value (I^LIM) by adjusting the over-current detection setting resistor

value ratio.

Calculate the over current detection setting resistor value by the following formula.

3.3 × R2

R1 + R2

− 0.3

9

V^IN− VO

V^O

× (200 × 10 −

I^LIM=

+

)

−

6.8 × R^ON

L

2 × fOSC × VIN

200 × 10³≥ R1 + R2 ≥ 30 × 10³

ILIM

: Over current detection value [A]

R1, R2 : I^LIMsetting resistor value [Ω]*

L

: Inductor value [H]

V^IN

V^O

f^OSC

R^ON

: Power supply voltage of switching system [V]

: Output setting voltage [V]

: Oscillation frequency [Hz]

: High-side FET ON resistance [Ω]

*

Since the over current detection value depends on the on-resistance of FET, the over current detection

setting resistor value ratio should be adjusted in consideration of the temperature characteristics of the on-

resistance. When the temperature at the FET joint part rises by + 100 °C, the on-resistance of FET increases

to about 1.5 times.

Inductor current

VREF

Over-current

detection value

I

LIM

R1

R2

I

O

ILIM*

Time

0

*

If the over current detection function is not used, connect the ILIM pin (ILIM1 and ILIM2) to the VREF pin.

DS04-27262-4E

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MB39A136

Selection of smoothing inductor

The inductor value selects the value that the ripple current peak-to-peak value becomes 50% or less of the

maximum load current as a rough standard. Calculate the inductor value in this case by the following formula.

V^IN− VO

LOR × IOMAX

V^O

L ≥

×

VIN × fOSC

L

: Inductor value [H]

I^OMAX

LOR

V^IN

: Maximum load current [A]

: Ripple current peak-to-peak value of Maximum load current ratio (=0.5)

: Power supply voltage of switching system [V]

: Output setting voltage [V]

V^O

f^OSC

: Oscillation frequency [Hz]

An inductor ripple current value limited on the principle of operation is necessary for this device. However,

when it uses the high-side FET of the low Ron resistance, the switching ripple voltage become small, and

the inductor ripple current value may become insufficient. This should be solved by the oscillation frequency

or reducing the inductor value.

Select the one of the inductor value that meets a requirement listed below.

V^IN− VO

ΔVRON

V^O

L ≤

×

× RON

VIN × fOSC

L

: Inductor value [H]

V^IN

V^O

: Power supply voltage of switching system [V]

: Output setting voltage [V]

f^OSC

ΔV^RON

R^ON

: Oscillation frequency [Hz]

: Ripple voltage [V] (20 mV or more is recommended)

: High-side FET ON resistance [Ω]

It is necessary to calculate the maximum current value that flows to the inductor to judge whether the electric

current that flows to the inductor is a rated value or less. Calculate the maximum current value of the inductor

by the following formula.

ΔIL

2

V^IN− VO

V^O

IL^MAX≥ IoMAX +

, ΔIL =

×

L

VIN × fOSC

ILMAX

Io^MAX

ΔIL

L

: Maximum current value of inductor [A]

: Maximum load current [A]

: Ripple current peak-to-peak value of inductor [A]

: Inductor value [H]

V^IN

V^O

: Power supply voltage of switching system [V]

: Output setting voltage [V]

f^OSC

: Oscillation frequency [Hz]

Inductor current

ILMAX

IoMAX

ΔIL

t

0

28

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MB39A136

Selection of SWFET

The switching ripple voltage generated between drain and sources on high-side FET is necessary for this

device operation. Select the one of the SWFET of on-resistance that satisfies the following formula.

ΔV^RON_Main

ΔIL

V^RONMAX

ΔIL

RON_Main ≥

, RON_Main ≤

I^LIM+

2

R^ON_Main

ΔIL

: High-side FET ON resistance [Ω]

: Ripple current peak-to-peak value of inductor [A]

ΔV^RON_Main: High-side FET ripple voltage [V] (20mV or more is recommended)

I^LIM

: Over current detection value [A]

V^RONMAX

: Maximum current sense voltage [V] (240mV or less is recommended)

Select FET ratings with a margin enough for the input voltage and the load current. Ratings with the over-

current detection setting value or more are recommended.

Calculate a necessary rated value of high-side FET and low-side FET by the following formula.

ΔIL

2

I^D> IoMAX +

I^D

: Rated drain current [A]

Io^MAX

ΔIL

: Maximum load current [A]

: Ripple current peak-to-peak value of inductor [A]

V^DS> VIN

V^DS

V^IN

: Rated voltage between drain and source [V]

: Power supply voltage of switching system [V]

VGS > VB

V^GS

V^B

: Rated voltage between gate and source [V]

: VB voltage [V]

Moreover, it is necessary to calculate the loss of SWFET to judge whether a permissible loss of SWFET is

a rated value or less. Calculate the loss on high-side FET by the following formula.

P^MainFET= PRON_Main + PSW_Main

P^MainFET

P^RON_Main: High-side FET conduction loss [W]

P^SW_Main: High-side FET SW loss [W]

: High-side FET loss [W]

DS04-27262-4E

29

MB39A136

High-side FET conduction loss

V^O

2

P^RON_Main= IoMAX ×

× RON_Main

VIN

PRON_Main : High-side FET conduction loss [W]

I^OMAX

V^IN

: Maximum load current [A]

: Power supply voltage of switching system [V]

: Output voltage [V]

V^O

R^ON_Main

: High-side FET ON resistance [Ω]

High-side FET SW loss

V^IN× fOSC × (Ibtm × tr + Itop × tf)

P^SW_Main=

2

P^SW_Main: High-side FET SW loss [W]

V^IN

f^OSC

I^btm

I^top

tr

: Power supply voltage of switching system [V]

: Oscillation frequency [Hz]

: Ripple current bottom value of inductor [A]

: Ripple current top value of inductor [A]

: Turn-on time on high-side FET [s]

: Turn-off time on high-side FET[s]

tf

Calculate the I^btm, the Itop, the tr and the tf simply by the following formula.

ΔIL

2

I^btm= IOMAX −

ΔIL

2

I^top= IOMAX +

Q^gd× 4

5 − V^gs(on)

Q^gd× 1

Vgs (on)

t^r=

t^f=

I^OMAX

ΔIL

Q^gd

: Maximum load current [A]

: Ripple current peak-to-peak value of inductor [A]

: Quantity of charge between gate and drain on high-side FET [C]

V^gs(on) : Voltage between gate and source in Qgd on high-side FET [V]

30

DS04-27262-4E

MB39A136

Calculate the loss on low-side FET by the following formula.

V^O

2

PSyncFET = PRon_Sync* = IoMAX × (1 −

) × Ron_Sync

VIN

PSyncFET : Low-side FET loss [W]

P^Ron_Sync: Low-side FET conduction loss [W]

I^OMAX

V^IN

: Maximum load current [A]

: Power supply voltage of switching system [V]

: Output voltage [V]

V^O

R^on_Sync: Low-side FET on-resistance [Ω]

* : The transition voltage of the voltage between drain and source on low-side FET is generally small, and the

switching loss is omitted here for the small one as it is possible to disregard it.

The gate drive power of SWFET is supplied by LDO in IC, therefore all SWFET allowable maximum total

charge (QgTotalMax) of 2ch is determined by the following formula.

0.095

QgTotalMax ≤

f^OSC

QgTotalMax : SWFET allowable maximum total charge [C]

f^OSC

: Oscillation frequency [Hz]

Selection of fly-back diode

When the conversion efficiency is valued, the improved property of the conversion efficiency is possible by

the addition of the fly-back diode. Thought it is usually unnecessary. The effect is achieved in the condition

where the oscillation frequency is high or output voltage is lower. Select schottky barrier diode (SBD) that

the forward current is as small as possible. In this DC/DC control IC, the period for the electric current flows

to fly back diode is limited to synchronous rectification period (60 ns × 2) because of using the synchronous

rectification method. Therefore, select the one that the electric current of fly back diode doesn't exceed

ratings of forward current surge peak (IFSM).Calculate the forward current surge peak ratings of fly back

diode by the following formula.

ΔIL

2

I^FSM≥ IoMAX +

I^FSM

: Forward current surge peak ratings of fly back diode [A]

: Maximum load current [A]

Io^MAX

ΔIL

: Ripple current peak-to-peak value of inductor [A]

Calculate ratings of the fly-back diode by the following formula:

V^R_Fly> VIN

V^R_Fly

V^IN

: Reverse voltage of fly-back diode direct current [V]

: Power supply voltage of switching system [V]

DS04-27262-4E

31

MB39A136

Selection of output capacitor

This device supports a small ceramic capacitor of the ESR. The ceramic capacitor that is low ESR is an

ideal to reduce the ripple voltage compared with other capacitor. Use the tantalum capacitor and the polymer

capacitor of the low ESR when a mass capacitor is needed as the ceramic capacitor can not support. To

the output voltage, the ripple voltage by the switching operation of DC/DC is generated. Discuss the lower

bound of output capacitor value according to an allowable ripple voltage. Calculate the output ripple voltage

from the following formula.

1

ΔV^O= (

+ ESR) × ΔIL

2π × f^OSC× CO

ΔVO

: Switching ripple voltage [V]

ESR

ΔIL

C^O

: Series resistance component of output capacitor [Ω]

: Ripple current peak-to-peak value of inductor [A]

: Output capacitor value [F]

f^OSC

: Oscillation frequency [Hz]

Notes: • The ripple voltage can be reduced by raising the oscillation frequency and the inductor value besides

capacitor.

• Capacitor has frequency characteristic, the temperature characteristic, and the electrode bias char-

acteristic, etc. The effective capacitor value might become extremely small depending on the condition.

Note the effective capacitor value in the condition.

Calculate ratings of the output capacitor by the following formula:

V^CO> VO

V^CO

V^O

: Withstand voltage of the output capacitor [V]

: Output voltage [V]

Note: Select the capacitor rating with withstand voltage allowing a margin enough for the output voltage.

In addition, use the allowable ripple current with an enough margin, if it has a rating.

Calculate an allowable ripple current of the output capacitor by the following formula:

ΔIL

Irms ≥

2√3

Irms

: Allowable ripple current (effective value) [A]

ΔIL

: Ripple current peak-to-peak value of inductor [A]

32

DS04-27262-4E

MB39A136

Selection of input capacitor

Select the input capacitor whose ESR is as small as possible. The ceramic capacitor is an ideal. Use the

tantalum capacitor and the polymer capacitor of the low ESR when a mass capacitor is needed as the

ceramic capacitor can not support. To the power supply voltage, the ripple voltage by the switching operation

of DC/DC is generated. Discuss the lower bound of input capacitor according to an allowable ripple voltage.

Calculate the ripple voltage of the power supply from the following formula.

I^OMAX

C^IN

V^O

ΔIL

2

ΔV^IN=

×

+ ESR × (IOMAX +

)

VIN × fOSC

ΔV^IN

I^OMAX

C^IN

: Switching system power supply ripple voltage peak-to-peak value [V]

: Maximum load current value [A]

: Input capacitor value [F]

V^IN

: Power supply voltage of switching system [V]

: Output setting voltage [V]

V^O

f^OSC

ESR

ΔIL

: Oscillation frequency [Hz]

: Series resistance component of input capacitor [Ω]

: Ripple current peak-to-peak value of inductor [A]

Notes: • The ripple voltage of the power supply can be reduced by raising the oscillation frequency besides

capacitor.

• Capacitor has frequency characteristic, the temperature characteristic, and the electrode bias char-

acteristic, etc. The effective capacitor value might become extremely small depending on the condition.

Note the effective capacitor value in the condition.

Calculate ratings of the input capacitor by the following formula:

V^CIN> VIN

V^CIN

V^IN

: Withstand voltage of the input capacitor [V]

: Power supply voltage of switching system [V]

Note: Select the capacitor rating with withstand voltage with margin enough for the input voltage.

In addition, use the allowable ripple current with an enough margin, if it has a rating.

Calculate an allowable ripple current by the following formula:

√V^O× (VIN − VO)

Irms ≥ I^OMAX×

V^IN

Irms

I^OMAX

V^IN

: Allowable ripple current (effective value) [A]

: Maximum load current value [A]

: Power supply voltage of switching system [V]

: Output voltage [V]

V^O

DS04-27262-4E

33

MB39A136

Selection of boot strap diode

Select Schottky barrier diode (SBD), that forward current is as small as possible. The electric current that

drives the gate of high-side FET flows to SBD of the bootstrap circuit. Calculate the mean current by the

following formula. Select it so as not to exceed the electric current ratings.

I^D≥ Qg × fOSC

ID

: Forward current [A]

Q^g

f^OSC

: Total quantity of charge of gate on high-side FET [C]

: Oscillation frequency [Hz]

Calculate ratings of the boot strap diode by the following formula:

V^R_BOOT> VIN

V^R_BOOT: Reverse voltage of boot strap diode direct current [V]

V^IN

: Power supply voltage of switching system [V]

Selection of boot strap capacitor

To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. Therefore, a

minimum value as a target is assumed the capacitor which can store electric charge 10 times that of the Qg

on high-side FET. And select the boot strap capacitor.

Qg

C^BOOT≥ 10 ×

V^B

CBOOT

Qg

: Boot strap capacitor [F]

: Amount of gate charge on high-side FET [C]

: VB voltage [V]

V^B

Calculate ratings of the boot strap capacitor by the following formula:

V^CBOOT> VB

V^CBOOT

V^B

: Withstand voltage of the boot strap capacitor [V]

: VB voltage [V]

34

DS04-27262-4E

MB39A136

Design of phase compensation circuit

Assume the phase compensation circuit of 1pole-1zero to be a standard in this device.

1pole-1zero phase compensation circuit

VO

Rc

Cc

R1

R2

-

To I Comp.

FB

+

COMP

Error

Amp

INTREF

As for crossover frequency (f^CO) that shows the band width of the control loop of DC/DC. The higher it is, the

more excellent the rapid response becomes, however, the possibility of causing the oscillation due to phase

margin shortage increases. Though this crossover frequency (f^CO) can be arbitrarily set, make 1/10 of the

oscillation frequencies (fosc) a standard, and set it to the upper limit. Moreover, set the phase margin at least

to 30 °C, and 45 °C or more if possible as a reference.

Set the constants of Rc and Cc of the phase compensation circuit using the following formula as a target.

(V^IN− VO) ALVCNV × RON_Main × fCO × 2π × CO × VO

R^C=

CC =

× R1

V^IN× fOSC × L × IOMAX

C^O× VO

RC × IOMAX

RC

C^C

V^IN

V^O

: Phase compensation resistor value [Ω]

: Phase compensation capacitor value [F]

: Power supply voltage of switching system [V]

: Output setting voltage [V]

f^OSC

I^OMAX

L

: Oscillation frequency [Hz]

: Maximum load current value [A]

: Inductor value [H]

C^O

: Output capacitor value [F]

R^ON_Main: High-side FET ON resistance[Ω]

R1

: Output setting resistor value [Ω]

A^LVCNV

: Level converter voltage gain [V/V]

On-duty ≤ 50% : A^LVCNV= 6.8

On-duty > 50% : A^LVCNV= 13.6

f^CO

: Cross-over frequency (arbitrary setting) [Hz]

DS04-27262-4E

35

MB39A136

VB pin capacitor

2.2 μF is assumed to be a standard, and when Qg of SWFET used is large, it is necessary to adjust it. To

drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. Therefore, a

minimum value as a target is assumed the capacitor, which can store electric charge 100 times that of the

Qg of the SWFET. And select it.

Qg

CVB ≥ 100 ×

V^B

CVB

Qg

V^B

: VB pin capacitor value [F]

: Total amount of gate charge of 2 ch respectively: high-side FET and low-side FET

[C]

: VB voltage [V]

Calculate ratings of the VB pin capacitor by the following formula:

V^CVB> VB

V^CVB: Withstand voltage of the VB pin capacitor [V]

V^B

: VB voltage [V]

36

DS04-27262-4E

MB39A136

VB regulator

In the condition for which the potential difference between VCC and VB is insufficient, the decrease in the

voltage of VB happens because of power output on-resistance and load current (mean current of all external

FET gate driving current and load current of internal IC) of the VB regulator. Stop the switching operation

when the voltage of VB decreases and it reaches threshold voltage (V^THL1) of the under voltage lockout

protection circuit. Therefore, set oscillation frequency or external FET or I/O potential difference of the VB

regulator using the following formula as a target when you use this IC.

V^CC≥ VB (VTHL1) + (Qg × fOSC + ICC) × RVB

V^CC

: Power supply voltage [V] (VIN)

: Threshold voltage of VB under-voltage lockout protection circuit [V]

(3.8 [V] Max )

VB (VTHL1)

: Total amount of gate charge of 2 ch respectively: high-side FET and low-side FET

[C]

Qg

f^OSC

I^CC

: Oscillation frequency [Hz]

: Power supply current [A] (4.7 × 10⁻³[A]=: Load current of VB (LDO) )

R^VB

: VB output on-resistance [Ω] (100 Ω (The reference value at VCC = 4.5 V) )

If the I/O potential difference is small, the problem can be solved by connecting the VB pin and the VCC pin.

The conditions of the input voltage range are as follows:

V^INinput voltage ranges:

25 V

4.5 V

6.0 V

(1) For 4.5 V < VIN < 6.0 V

(1)

(3)

→ Connect VB pin to VCC.

(2) When the input voltage range steps over 6.0 V

→ Normal use (VCC to VB not connected)

(3) For 6.0 V ≤ V^IN

→ Normal use (VCC to VB not connected)

(2)

Note that if the I/O potential difference is not enough when used, use the actual machine to check carefully

the operations at the normal operation, start operation, and stop operation. In particular, care is needed

when the input voltage range over 6 V.

DS04-27262-4E

37

MB39A136

Power dissipation and the thermal design

As for this IC, considerations of the power dissipation and thermal design are not necessary in most cases

because of its high efficiency. However, they are necessary for the use at the conditions of a high power

supply voltage, a high oscillation frequency, high load, and the high temperature.

Calculate IC internal loss (P^IC) by the following formula.

P^IC= VCC × (ICC + Qg × fOSC)

P^IC

V^CC

I^CC

: IC internal loss [W]

: Power supply voltage (VIN) [V]

: Power supply current [A] (4.7 [mA] Max)

: All SWFET total quantity of charge for ch 2 [C] (Total with Vgs = 5 V)

: Oscillation frequency[Hz]

Qg

f^OSC

Calculate junction temperature (Tj) by the following formula.

Tj = Ta + θja × P^IC

Tj

: Junction temperature [ °C] (+150 [ °C] Max)

: Ambient temperature [ °C]

: TSSOP-24 Package thermal resistance (76 °C/W)

: IC internal loss [W]

Ta

θja

P^IC

Handling of the pins when using a single channel

Although this device is a 2-channel DC/DC converter control IC, it is also able to be used as a 1-channel

DC/DC converter by handling the pins of the unused channel as shown in the following diagram.

“Open”

CBx

FBx

COMPx

DRVHx

DRVLx

CSx

CTLx

LXx

ILIMx

Note: x is the unused channel number.

38

DS04-27262-4E

MB39A136

Board layout

Consider the points listed below and do the layout design.

• Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor con-

nected with the VCC and VB pins, and GND pin of the switching system parts with switching system GND

(PGND). Connect other GND connection pins with control system GND (AGND), and separate each GND,

and try not to pass the heavy current path through the control system GND (AGND) as much as possible.

In that case, connect control system GND (AGND) and switching system GND (PGND) right under IC.

• Connect the switching system parts as much as possible on the surface. Avoid the connection through the

through-hole as much as possible.

• As for GND pins of the switching system parts, provide the through hole at the proximal place, and connect

it with GND of internal layer.

• Pay the most attention to the loop composed of input capacitor (C^IN), SWFET, and fly-back diode (SBD).

Consider making the current loop as small as possible.

• Place the boot strap capacitor (C^BOOT1, CBOOT2) proximal to CBx and LXx pins of IC as much as possible.

• This device monitors the voltage between drain and source on high-side FET as voltage between VCC

and LX pins. Place the input capacitor (C^IN) and the high-side FET of each CH proximally as much as

possible. Draw out the wiring to VCC pin from the proximal place to the input capacitor of CH1 and CH2.

As for the net of the LXx pin, draw it out from the proximal place to the source pin on high-side FET.

Moreover, a large electric current flows momentary in the net of the LXx pin. Wire the linewidth of about

0.8mm to be a standard, as short as possible.

• Large electric current flows momentary in the net of DRVHx and DRVLx pins connected with the gate of

SWFET. Wire the linewidth of about 0.8mm to be a standard, as short as possible.

• By-pass capacitor (C^VCC, CVREF, CVB) connected with VREF, VCC, and VB, and the resistor (RRT) connected

with the RT pin should be placed close to the pin as much as possible. Also connect the GND pin of the

by-pass capacitor with GND of internal layer in the proximal through-hole.

• Consider the net connected with RT, FBx, and the COMPx pins to keep away from a Switching system

parts as much as possible because it is sensitive to the noise. Moreover, place the output voltage setting

resistor and the phase compensation circuit element connected with this net close to the IC as much as

possible, and try to make the net as short as possible. In addition, for the internal layer right under the

installing part, provide the control system GND (AGND) of few ripple and few spike noises, or provide the

ground plane of the power supply voltage as much as possible.

Switching system parts : Input capacitor (C^IN), SWFET, Fly-back diode (SBD), Inductor (L),

Output capacitor (C^O)

Note: x : Each channel number

Layout example of switching components

To the VCC pin Through-hole

High-side FET High-side FET

Layout example of IC

C

BOOT1

1pin

CVCC

A

GND

V

IN

Through-hole

R

RT

CIN

To the LX2

CIN

To the LX1 pin

P

GND

VB

Low-side

FET

Low-side FET

PGND

C

CVREF

SBD (option)

CO

CBOOT2

L

P

GND

AGND

Vo1 Vo2

AGND and PGND are connected right under IC.

Output voltage

Vo1 feedback

Output voltage

Vo2 feedback

Internal

Surface

layer

DS04-27262-4E

39

MB39A136

■ REFERENCE DATA

CH1 Conversion Efficiency

Conversion Efficiency vs. Load Current

CH2 Conversion Efficiency

Conversion Efficiency vs. Load Current

100

CH2

95

CH1

95

90

85

80

75

70

65

60

VIN = 12 V

V

IN = 12 V

1 = 1.2 V

V

O

2 = 3.3 V

V

O

90

85

80

75

70

65

60

fosc = 300 kHz

Ta = + 25°C

fosc = 300 kHz

Ta = + 25°C

PFM/PWM

Fixed PWM

0.01

0.1

1

10

0.01

0.1

1

10

Load Current IO1(A)

Load Current I 2 (A)

O

CH1 Load Regulation

Output Voltage vs. Load Current

CH2 Load Regulation

Output Voltage vs. Load Current

1.30

1.28

1.26

1.24

1.22

1.20

1.18

1.16

1.14

1.12

1.10

3.60

3.50

3.40

3.30

3.20

3.10

3.00

V

IN = 12 V

1 = 1.2 V

V

IN = 12 V

2 = 3.3 V

V

O

V

O

MODE = VREF

fosc = 300 kHz

Ta = + 25°C

MODE = VREF

fosc = 300 kHz

Ta = + 25°C

0

1

2

3

4

5

0

1

2

3

4

5

Load Current IO1(A)

Load Current I

O

2 (A)

(Continued)

40

DS04-27262-4E

MB39A136

(Continued)

CH1

CH2

Load Sudden Change Waveform

I_O1 : 1 A/div

I_O2 : 1 A/div

2 A

0 A

100 s/div

μ

100 s/div

μ

V_O1 : 200 mV/div (1.2 V offset)

V_O2 : 200 mV/div (3.3 V offset)

V^IN= 12 V, VO1 = 1.2 V

I^O1 = 0←→2 A, fOSC = 300 kHz, Ta = + 25 °C

V^IN= 12 V, VO2 = 3.3 V

I^O2 = 0←→2 A, fOSC = 300 kHz, Ta = + 25 °C

CTL Startup Waveform

CTL Stop Waveform

CTL1, 2 : 5 V/div

V_O2: 1 V/div

V_O1: 1 V/div

1 ms/div

V^IN= 12 V, fOSC = 300 kHz, Ta = + 25 °C, Soft-start setting time = 3.0 ms

V^O1 = 1.2 V, IO1 = 5 A (0.24 Ω) , VO2 = 3.3 V, IO2 = 5 A (0.66 Ω)

Normal operation → Over current protection → Under voltage protection operation waveform

V_O1 : 0.5 V/div

V^IN= 12 V

V^O1 = 1.2 V

1

f^OSC= 300 kHz

Ta = + 25 °C

CS1 : 2 V/div

2

LX1 : 10 V/div

I_O1 : 10 A/div

3

4

500 s/div

μ

Normal operation

Over current

Under voltage

protection operation

DS04-27262-4E

41

MB39A136

■ USAGE PRECAUTION

1. Do not configure the IC over the maximum ratings.

If the IC is used over the maximum ratings, the LSI may be permanently damaged.

It is preferable for the device to be normally operated within the recommended usage conditions. Usage

outside of these conditions can have an adverse effect on the reliability of the LSI.

2. Use the device within the recommended operating conditions.

TherecommendedvaluesguaranteethenormalLSIoperationundertherecommendedoperatingconditions.

The electrical ratings are guaranteed when the device is used within the recommended operating conditions

and under the conditions stated for each item.

3. Printed circuit board ground lines should be set up with consideration for common

impedance.

4. Take appropriate measures against static electricity.

• Containers for semiconductor materials should have anti-static protection or be made of conductive ma-

terial.

• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.

• Work platforms, tools, and instruments should be properly grounded.

• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ in series between body and

ground.

5. Do not apply negative voltages.

The use of negative voltages below − 0.3 V may make the parasitic transistor activated, and can cause

malfunctions.

42

DS04-27262-4E

MB39A136

■ ORDERING INFORMATION

Part number

Package

Remarks

24-pin plastic TSSOP

(FPT-24P-M09)

MB39A136PFT

■ EV BOARD ORDERING INFORMATION

Part number

EV board version No.

Remarks

MB39A136EVB-01

MB39A136EVB-01 Rev2.0

TSSOP-24

DS04-27262-4E

43

MB39A136

■ RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION

The LSI products of FUJITSU SEMICONDUCTOR with “E1” are compliant with RoHS Directive, and has

observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB),

and polybrominated diphenyl ethers (PBDE). A product whose part number has trailing characters “E1” is

RoHS compliant.

■ MARKING FORMAT (Lead Free version)

39A136

XXXX

E1

XXX

Lead Free version

INDEX

44

DS04-27262-4E

MB39A136

■ LABELING SAMPLE (Lead free version)

Lead-free mark

JEITA logo JEDEC logo

MB123456P - 789 - GE1

(3N) 1MB123456P-789-GE1 1000

G

Pb

(3N)2 1561190005 107210

QC PASS

PCS

1,000

MB123456P - 789 - GE1

ASSEMBLED IN JAPAN

2006/03/01

MB123456P - 789 - GE1

1/1

1561190005

0605 - Z01A 1000

“ASSEMBLED IN CHINA” is printed on the label

of a product assembled in China.

The part number of a lead-free product has

the trailing characters “E1”.

DS04-27262-4E

45

MB39A136

■ MB39A136PFT

RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL

[FUJITSU SEMICONDUCTOR Recommended Mounting Conditions]

Item

Condition

IR (infrared reflow) , Manual soldering (partial heating method)

2 times

Mounting Method

Mounting times

Please use it within two years after

Before opening

Manufacture.

From opening to the 2nd

Less than 8 days

reflow

Storage period

When the storage period after

opening was exceeded

Please process within 8 days

after baking (125 °C, 24h)

Storage conditions

5 °C to 30 °C, 70%RH or less (the lowest possible humidity)

[Mounting Conditions]

(1) IR (infrared reflow)

260°C

255°C

Main heating

170 °C

to

190 °C

(b)

(c)

(d)

(e)

RT

(a)

(d')

“H” level : 260 °C Max

(a) Temperature increase gradient : Average 1 °C/s to 4 °C/s

(b) Preliminary heating

: Temperature 170 °C to 190 °C, 60 s to 180 s

(c) Temperature increase gradient : Average 1 °C/s to 4 °C/s

(d) Peak temperature

(d’) Main heating

: Temperature 260 °C Max; 255 °C or more, 10 s or less

: Temperature 230 °C or more, 40 s or less

or

Temperature 225 °C or more, 60 s or less

or

Temperature 220 °C or more, 80 s or less

(e) Cooling

: Natural cooling or forced cooling

Note: Temperature : on the top of the package body

(2) Manual soldering (partial heating method)

Temperature at the tip of an soldering iron: 400 °C max

Time: Five seconds or below per pin

46

DS04-27262-4E

MB39A136

■ PACKAGE DIMENSIONS

24-pin plastic TSSOP

Lead pitch

0.50 mm

4.40 mm × 6.50 mm

Gullwing

Package width

package length

×

Lead shape

Sealing method

Mounting height

Weight

Plastic mold

1.20 mm MAX

0.08 g

(FPT-24P-M09)

24-pin plastic TSSOP

Note 1) Pins width and pins thickness include plating thickness.

Note 2) Pins width do not include tie bar cutting remainder.

Note 3) #: These dimensions do not include resin protrusion.

(FPT-24P-M09)

#

6.50±0.10(.256±.004)

0.145±0.045

(.0057±.0018)

24

13

BTM E-MARK

#

4.40±0.10 6.40±0.20

(.252±.008)

(.173±.004)

INDEX

Details of "A" part

1.10 ⁺^–0⁰^.^.¹¹⁵⁰

.043 ⁺–.^.0⁰0⁰6⁴

(Mounting height)

1

12

"A"

0.20 ⁺^–0⁰^.^.⁰⁰²⁷

.008 ⁺–.^.0⁰0⁰1³

0.50(.020)

M

0.13(.005)

0~8°

0.10±0.05

(.004±.002)

0.60±0.15

(.024±.006)

(Stand off)

0.10(.004)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

C

2007-2010 FUJITSU SEMICONDUCTOR LIMITED F24032S-c-2-5

Please check the latest package dimension at the following URL.

http://edevice.fujitsu.com/package/en-search/

DS04-27262-4E

47

MB39A136

■ MAJOR CHANGES IN THIS EDITION

A change on a page is indicated by a vertical line drawn on the left side of that page.

Page

Section

Change Results

■ ELECTRICAL CHARACTERISTICS

Revised the minimum value of “Maximum on-duty” in

9

“Output Block [DRV]”:

72 → 75

48

DS04-27262-4E

MB39A136

■ CONTENTS

page

- DESCRIPTION .................................................................................................................................................... 1

- FEATURES .......................................................................................................................................................... 1

- APPLICATION ..................................................................................................................................................... 1

- PIN ASSIGNMENT ............................................................................................................................................. 2

- PIN DESCRIPTION ............................................................................................................................................ 3

- BLOCK DIAGRAM .............................................................................................................................................. 4

- ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 5

- RECOMMENDED OPERATING CONDITIONS ............................................................................................ 6

- ELECTRICAL CHARACTERISTICS ................................................................................................................ 7

- TYPICAL CHARACTERISTICS ........................................................................................................................ 11

- FUNCTION DESCRIPTION .............................................................................................................................. 13

- PROTECTION FUNCTION TABLE .................................................................................................................. 17

- I/O PIN EQUIVALENT CIRCUIT DIAGRAM ................................................................................................... 18

- EXAMPLE APPLICATION CIRCUIT ................................................................................................................ 20

- PARTS LIST ......................................................................................................................................................... 21

- APPLICATION NOTE ......................................................................................................................................... 23

- REFERENCE DATA ........................................................................................................................................... 40

- USAGE PRECAUTION ...................................................................................................................................... 42

- ORDERING INFORMATION ............................................................................................................................. 43

- EV BOARD ORDERING INFORMATION ....................................................................................................... 43

- RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION ................................................... 44

- MARKING FORMAT (Lead Free version) ....................................................................................................... 44

- LABELING SAMPLE (Lead free version) ........................................................................................................ 45

- MB39A136PFT RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL ..................... 46

- PACKAGE DIMENSIONS .................................................................................................................................. 47

- MAJOR CHANGES IN THIS EDITION ............................................................................................................ 48

DS04-27262-4E

49

MB39A136

MEMO

50

DS04-27262-4E

MB39A136

MEMO

DS04-27262-4E

51

MB39A136

FUJITSU SEMICONDUCTOR LIMITED

Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,

Kohoku-ku Yokohama Kanagawa 222-0033, Japan

Tel: +81-45-415-5858

http://jp.fujitsu.com/fsl/en/

For further information please contact:

North and South America

Asia Pacific

FUJITSU SEMICONDUCTOR AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://us.fujitsu.com/micro/

FUJITSU SEMICONDUCTOR ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://sg.fujitsu.com/semiconductor/

Europe

FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.

30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District,

Shanghai 201204, China

Tel : +86-21-6146-3688 Fax : +86-21-6146-3660

http://cn.fujitsu.com/fss/

FUJITSU SEMICONDUCTOR EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/semiconductor/

Korea

FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.

2/F, Green 18 Building, Hong Kong Science Park,

Shatin, N.T., Hong Kong

Tel : +852-2736-3232 Fax : +852-2314-4207

http://cn.fujitsu.com/fsp/

FUJITSU SEMICONDUCTOR KOREA LTD.

902 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fsk/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does

not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any

third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right

by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or

other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect

to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in

nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in

weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-

ing in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-

current levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations

of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department


型号：	MB39A136PFT-E1
厂家：	FUJITSU
描述：	Switching Regulator/Controller, Current-mode, 1000kHz Switching Freq-Max, PDSO24 光电二极管
文件：	总52页 (文件大小：1898K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB39A136PFT-E1 [FUJITSU]

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