MB39A214APFT [FUJITSU]
Dual Switching Controller, Voltage-mode, 1.2A, 1000kHz Switching Freq-Max, CMOS, PDSO24, 4.40 X 6.50 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, PLASTIC, TSSOP-24;型号: | MB39A214APFT |
厂家: | FUJITSU |
描述: | Dual Switching Controller, Voltage-mode, 1.2A, 1000kHz Switching Freq-Max, CMOS, PDSO24, 4.40 X 6.50 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, PLASTIC, TSSOP-24 开关 光电二极管 |
文件: | 总56页 (文件大小:889K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS405-00007-2v0-E
ASSP for Power Management Applications
2ch DC/DC converter IC
with PFM/ PWM synchronous rectification
MB39A214A
DESCRIPTION
MB39A214A is a N-ch/ N-ch synchronous rectification type 2ch Buck DC/DC converter IC equipped with
a bottom detection comparator for low output voltage ripple. It supports low on-duty operation to allow
stable output of low voltages when there is a large difference between input and output voltages. It also
allows the high switching frequency setting, enabling the downsized peripheral circuits and low-cost
configuration. MB39A214A realizes ultra-rapid response and high efficiency with built-in enhanced
protection features. It is most suitable for the power supply for ASIC or FPGA core, input/output devices, or
memory.
FEATURES
High efficiency
Frequency setting by internal preset function : 310 kHz, 620 kHz, 1 MHz
High accuracy reference voltage
VIN Input voltage range
: ± 0.7% (Ta = + 25 °C)
: 6 V to 28 V
Output voltage setting range
: 0.7 V to 5.3 V
Possible to select the automatic PFM/PWM selection mode or PWM-fixed mode
PAF frequency limitation function (Prohibit Audio Frequency) : > 30 kHz (Min)
Built-in boost diode, external fly-back diode not required
Built-in discharge FET
Built-in over voltage protection function
Built-in under voltage protection function
Built-in over temperature protection function
Built-in over current limitation function
Soft-start circuit without load dependence
Current sense resistor not required
Built-in synchronous rectification type output steps for N-ch MOS FET
Standby current
Package
: 0 µA (Typ)
: TSSOP24 (4.4 mm6.5 mm1.2 mm [Max])
APPLICATIONS
Digital TV
Photocopiers
STB
BD, DVD players/recorders
Projectors
etc.
Copyright©2011-2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2012.8
MB39A214A
PIN ASSIGNMENT
(TOP VIEW)
BST1
EN1
1
24
23
22
21
20
19
18
17
16
15
14
13
DRVH1
LX1
2
VOUT1
FB1
3
DRVL1
PGND
ILIM1
VCC
4
CS1
5
GND
FREQ
CS2
6
7
VB
8
MODE
ILIM2
DRVL2
LX2
FB2
9
VOUT2
EN2
10
11
12
BST2
DRVH2
(FPT-24P-M09)
2
DS405-00007-2v0-E
MB39A214A
PIN DESCRIPTIONS
Pin No.
Pin Name
BST1
EN1
I/O
—
I
Description
1
2
3
4
5
6
CH1 boost capacitor connection pin.
CH1 enable pin.
VOUT1
FB1
I
CH1 input pin for DC/DC output voltage.
CH1 input pin for feedback voltage.
I
CS1
I
CH1 soft-start time setting capacitor connection pin.
Ground pin.
GND
—
Frequency switching signal input pin.
FREQ : GND Short
FREQ : Open
FREQ : VB Short
Switching frequency 310 kHz
Switching frequency 620 kHz
Switching frequency 1 MHz
7
FREQ
I
8
CS2
FB2
I
I
CH2 soft-start time setting capacitor connection pin.
CH2 input pin for feedback voltage.
9
10
11
12
13
14
15
16
VOUT2
EN2
I
CH2 input pin for DC/DC output voltage.
I
CH2 enable pin.
BST2
DRVH2
LX2
—
O
—
—
I
CH2 boost capacitor connection pin.
CH2 output pin for external high-side FET gate drive.
CH2 inductor and external high-side FET source connection pin.
CH2 output pin for external low-side FET gate drive.
CH2 over current detection level setting voltage input pin.
DC/DC control mode switching signal input pin.
DRVL2
ILIM2
MODE : GND Short
MODE : Open
MODE : VB Short
PFM/PWM
PFM/PWM, PAF
PWM fixed
17
MODE
I
18
19
20
21
22
23
24
VB
O
I
Internal circuit bias output pin.
VCC
Power input pin for control and output circuits.
CH1 over current detection level setting voltage input pin.
Ground pin for output circuit.
ILIM1
PGND
DRVL1
LX1
I
—
O
—
O
CH1 output pin for external low-side FET gate drive.
CH1 inductor and external high-side FET source connection pin.
CH1 output pin for external high-side FET gate drive.
DRVH1
3
DS405-00007-2v0-E
MB39A214A
BLOCK DIAGRAM
VIN
(6 V to 28 V)
VCC
VB
EN1
EN2
VB
5.2 V
VOUT1
<CH1>
/EN1
VOUT1
VCC
VB
t
ON
BST1
OTP
UVP
25 Ω
Generator
1 µA
VOUT1
<Error Comp.>
DRVH1
LX1
R
Q
S
FB1
CS1
DRVH
DRVL
DRV
Logic
Slope & Offset
VB
/EN1
/UVLO(OTP)
DRVL1
REF1
(0.7 V)
5 µA
<IR Comp.>
<ILIM Comp.>
ILIM1
×1.0
4 : 1
LX1
×1.0
PGND
<OVP Comp.>
OVP1
PGND
FREQ
OVP
UVP
OVP latch
(delay:15 µs)
REF1
× 1.15V
OVP2
<UVP Comp.>
UVP1
2 µA
UVPlatch
(delay:150 µs)
FREQ
Select
UVP2
REF1
× 0.7 V
450kΩ
EN1
EN
Logic
EN1
"H": Enable
2 µA
MODE
MODE
Select
UVLO
(VB)
OTP
450 kΩ
UVLO
"H": UVLO
release
Thermal
Protection
(0.7 V)
UVLO
(VREF)
REF1
REF2
VREF
2.5 V
to CH2
EN2
<CH2>
BST2
VOUT2
VOUT2
VOUT2
DRVH2
LX2
FB2
DRVL2
CS2
ILIM2
EN2
GND
4
DS405-00007-2v0-E
MB39A214A
ABSOLUTE MAXIMUM RATINGS
Rating
Unit
Parameter
Symbol
Condition
Min
− 0.3
− 0.3
− 1
Max
VCC pin input voltage
BST pin input voltage
LX pin input voltage
VVCC
VBST
VLX
VCC pin
+ 30
+ 36
+ 30
V
V
V
BST1, BST2 pins
LX1, LX2 pins
Voltage between
BST and LX
VBST-LX
—
− 0.3
+ 7
V
EN pin input voltage
VEN
VFB
EN1, EN2 pins
FB1, FB2 pins
VOUT1, VOUT2 pins
ILIM1, ILIM2 pins
CS1, CS2 pins
FREQ pin
− 0.3
− 0.3
− 0.3
− 0.3
− 0.3
− 0.3
− 0.3
+ 30
V
V
V
V
V
V
V
VB + 0.3
+ 7
VVOUT
VILIM
VCS
VB + 0.3
VB + 0.3
VB + 0.3
VB + 0.3
Input voltage
VFREQ
VMODE MODE pin
DRVH1, DRVH2 pins,
Output current
IOUT
—
60
mA
DRVL1, DRVL2 pins
Ta ≤ + 25°C
—
Power dissipation
PD
—
+ 1282
+ 125
mW
°C
Storage temperature
TSTG
− 55
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
5
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MB39A214A
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Condition
Unit
Min
6
Typ
—
—
—
—
—
—
—
—
Max
28
VCC pin input voltage
BST pin input voltage
EN pin input voltage
VVCC
VBST
VCC pin
V
V
V
V
V
V
V
V
BST1, BST2 pins
EN1, EN2 pins
FB1, FB2 pins
VOUT1, VOUT2 pins
ILIM1, ILIM2 pins
FREQ pin
—
0
34
VEN
28
VFB
0
VB
5.5
2
VVOUT
VILIM
VFREQ
VMODE
0
Input voltage
0
0
VB
VB
MODE pin
0
DRVH1, DRVH2 pins,
DRVL1, DRVL2 pins
Duty ≤ 5% (t = 1/fOSCDuty)
Peak output current
IOUT
Ta
− 1200
− 30
—
+ 1200
+ 85
mA
°C
Operating ambient
temperature
—
+ 25
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device
is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
6
DS405-00007-2v0-E
MB39A214A
ELECTRICAL CHARACTERISTICS
(Ta = +25°C, VCC = 12 V, EN1, EN2 = 5 V)
Value
Pin
No.
Parameter
Output voltage
Symbol
Condition
Unit
Min
5.04
—
Typ
5.20
10
Max
5.36
100
VVB
LINE
LOAD
18 VB = 0 A
V
Input stability
Load stability
18 VCC = 6 V to 28 V
mV
mV
Bias Voltage
Block
VB = 0 A to − 1 mA
18
—
10
100
[VB Reg.]
Short-circuit
output current
− 145 − 100 − 75
IOS
18 VB = 0 V
mA
Under
voltage
VTLH
VTHL
18 VB pin
18 VB pin
4.0
3.7
4.3
4.0
4.6
4.3
V
V
Threshold voltage
Lockout
Protection
Circuit Block
[UVLO]
Hysteresis width
Charge current
VH
18 VB pin
—
0.3*
—
V
− 1.5 −1.0 − 0.75 µA
ICS
RD
5,8 CS1, CS2 = 0 V
Soft-Start/
Discharge
Block
[Soft Start,
Discharge]
Electrical discharge
resistance
EN1, EN2 = 0 V,
3,10
Ω
V
—
—
25*
0.2*
538
400
263
200
163
125
136
103
77
—
—
VOUT1, VOUT2 ≥ 0.15 V
Discharge end
voltage
EN1, EN2 = 0 V,
VOUT1, VOUT2 pins
VVOVTH 3,10
FREQ pin GND connection
VCC = 12 V, VOUT1 = 1.5 V
tON11
24
13
24
13
24
13
24
13
24
13
24
13
430
320
210
160
130
100
—
646
480
316
240
196
150
191
145
108
82
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ON time
(Preset value 1)
FREQ pin GND connection
VCC = 12 V, VOUT2 = 1.5V
tON21
FREQ pin OPEN
VCC = 12 V, VOUT1 = 1.5 V
tON12
ON time
(Preset value 2)
FREQ pin OPEN
VCC = 12 V, VOUT2 = 1.5 V
tON22
FREQ pin VB connection
VCC = 12 V, VOUT1 = 1.5 V
tON13
ON time
(Preset value 3)
ON/OFF
Time
Generator
Block
[tON
Generator]
FREQ pin VB connection
VCC = 12 V, VOUT2 = 1.5 V
tON23
FREQ pin GND connection
VCC = 12 V, VOUT1 = 0V
tONMIN11
tONMIN21
tONMIN12
tONMIN22
tONMIN13
tONMIN23
Minimum
ON time
(Preset value 1)
FREQ pin GND connection
VCC = 12 V, VOUT2 = 0V
—
FREQ pin OPEN
VCC = 12 V, VOUT1 = 0V
—
Minimum
ON time
(Preset value 2)
FREQ pin OPEN
VCC = 12 V, VOUT2 = 0V
—
58
FREQ pin VB connection
VCC = 12V, VOUT1 = 0V
—
55
77
Minimum
ON time
(Preset value 3)
FREQ pin VB connection
VCC = 12 V, VOUT2 = 0V
—
—
43
61
ns
ns
Minimum OFF time tOFFMIN 24, 13
—
410
535
7
DS405-00007-2v0-E
MB39A214A
Value
Pin
No.
Parameter
Symbol
Condition
Unit
Min Typ Max
0.695 0.700 0.705
Ta = +25°C
FB1, FB2 = 0.7 V
Threshold voltage
Error
VTH
IFB
4, 9
4, 9
V
Comparison
Block
− 0.1
+0.1 µA
FB pin input current
0
VOUT pin input
[Error Comp.]
current
µA
IVO
3,10 VOUT1, VOUT2 = 1.5 V
PGND − LX1, LX2
21 to 23
—
6.0
8.6
Over current detection
offset voltage
− 30
− 6
—
+30
− 4
—
VOFFILIM
IILIM
0
mV
µA
Over Current
Detection
Block
21 to 14 ILIM1, ILIM2 = 500 mV
− 5
ILIM pin current
20,16 ILIM1, ILIM2 = 0 V
ILIM pin current
Temperature slope
ppm/
°C
[ILIM Comp.]
Ta = +25°C
TILIM
20,16
4, 9
4500*
Over-
voltage
Over-voltage
detecting voltage
VOVP
For REF1, REF2 voltage
110
115
120
%
Protection
Circuit Block
[OVP Comp.]
Hysteresis width
VHOVP
tOVP
4, 9
—
—
—
—
10
5*
15
—
20
%
µs
Detection delay time
Under-
voltage
Under-voltage
detecting voltage
VUVP
4, 9
For REF1, REF2 voltage
65
70
75
%
Protection
Circuit Block
[UVP Comp.]
Hysteresis width
VHUVP
tUVP
4, 9
—
—
—
—
—
100
—
10*
150
—
200
—
%
µs
°C
Detection delay time
Over-
TOTPH
—
150*
temperature
Protection
Circuit Block
[OTP]
Protection
temperature
°C
TOTPL
—
—
—
125*
—
DRVH1, DRVH2 =
− 100 mA
Ω
Ω
Ω
Ω
ROH
ROL
ROH
ROL
24,13
—
—
—
—
4
1
4
1
6
High-side output
on-resistance
24,13 DRVH1, DRVH2 = 100 mA
1.5
6
DRVL1, DRVL2 =
− 100 mA
22,15
Low-side output
on-resistance
22,15 DRVL1, DRVL2 = 100 mA
1.5
LX1, LX2 = 0 V,
24,13 BST1, BST2 = VB
22,15 DRVH1, DRVH2 = 2.5 V
Duty ≤ 5%
Output source
current
− 0.5*
0.9*
25
ISOURCE
—
—
15
35
—
—
35
65
A
A
Output Block
[DRV]
LX1, LX2 = 0 V,
24,13 BST1, BST2 = VB
22,15 DRVH1, DRVH2 = 2.5 V
Duty ≤ 5%
Output sink current
ISINK
LX1, LX2 = 0 V,
BST1, BST2 = VB
DRVL1, DRVL2-low to
ns
ns
DRVH1, DRVH2-on
24 to 22
13 to 15
Dead time
tD
LX1, LX2 = 0 V,
BST1, BST2 = VB
DRVH1, DRVH2-low to
DRVL1, DRVL2-on
50
8
DS405-00007-2v0-E
MB39A214A
Value
Unit
Pin
No.
Parameter
BST diode voltage
Symbol
Condition
Min
Typ Max
VF
1,12 IF = 10 mA
0.75
0.85
0.95
V
Output Block
[DRV]
LX1, LX2 = 0 V,
BST1, BST2 = 5.2 V
µA
Bias current
IBST
1,12
11
0
15
22
Preset value 1
conditions
FREQ pin:
GND connection
VFREQ1
VFREQ2
VFREQ3
VFREQ
7
7
7
7
—
—
—
0.9
0.2
1.2
V
V
V
V
Preset value 2
conditions
Switching
Frequency
Control Block
[FREQ]
FREQ pin: OPEN
0.6
2.4
0.63
Preset value 3
conditions
FREQ pin: VB connection
FREQ = OPEN
VB
1.17
FREQ pin
output voltage
PFM/PWM mode
conditions
PAF function
negate
MODE pin:
GND connection
VPFM1
17
0
—
0.2
V
PFM/PWM mode
conditions
PAF function
assert
PFM Control
Circuit Block
[MODE]
VPFM2
17 MODE pin : OPEN
0.6
4.6
—
—
1.2
V
V
PWM-fixed mode
conditions
VPWM
17 MODE pin : VB connection
VB
Ta = − 30°C to +85°C
PAF frequency
MODE pin voltage
ON condition
fPAF
VMODE
VON
VOFF
VH
—
30
0.63
2.64
—
45
0.9
—
—
1.17
—
kHz
V
17 MODE = OPEN
2, 11 EN1, EN2 pins
2, 11 EN1, EN2 pins
2, 11 EN1, EN2 pins
2, 11 EN1, EN2 = 5V
19 EN1, EN2 = 0V
LX1, LX2 = 0 V
V
OFF condition
Hysteresis width
Input current
—
0.66
—
V
Enable Block
[EN1 , EN2]
—
0.4*
15
V
µA
µA
IEN
11
22
Standby current
ICCS
—
0
10
Power supply
current during idle
period
BST1, BST2 :
19
µA
µA
ICC1
—
—
600
860
VB connection
Power Supply
Current
FB1, FB2 = 0.75 V
LX1, LX2 = 0V
Power supply
current during
operation
BST1, BST2 :
19
ICC2
1200 1700
VB connection
FB1, FB2 = 0.6 V
*: This parameter is not be specified. This should be used as a reference to support designing the circuits.
9
DS405-00007-2v0-E
MB39A214A
TYPICAL CHARACTERISTICS
Power dissipation vs. Operating ambient temperature
2000
1500
1282
1000
500
0
-50 -25 +0 +25 +50 +75 +100+125
Operating ambient temperature Ta (°C)
VB bias voltage vs. Operating ambient temperature
VB bias voltage vs. VB bias output current
Ta = +25 °C
5.4
5.3
5.2
5.1
5.0
5.40
5.36
5.32
5.28
5.24
5.20
5.16
VCC=12V
5.12
VCC=12V
5.08
5.04
5.00
IVB=0A
VCC=28V
VCC=6V
-40 -20
0
+20 +40 +60 +80 +100
-30 -25 -20 -15 -10
-5
0
Operating ambient temperature Ta (°C)
VB bias output current IVB (mA)
Error Comp. Threshold voltage vs.
Operating ambient temperature
ILIM pin current vs. Operating ambient temperature
-3.5
0.705
0.704
0.703
0.702
0.701
0.700
0.699
0.698
0.697
0.696
0.695
-4.0
-4.5
-5.0
-5.5
-6.0
-40 -20 0 +20 +40 +60 +80+100
-40 -20
0
+20 +40 +60 +80 +100
Operating ambient temperature Ta (°C)
Operating ambient temperature Ta (°C)
10
DS405-00007-2v0-E
MB39A214A
DRVH1 on time vs. Operating ambient temperature
DRVH2 on time vs. Operating ambient temperature
500
700
650
600
550
500
450
400
350
300
250
200
150
100
450
FREQ=GND
FREQ=GND
400
350
VCC=12V
VOUT2=1.5V
VCC=12V
VOUT1=1.5V
300
250
200
150
100
50
FREQ=OPEN
FREQ=OPEN
FREQ=VB
FREQ=VB
-40 -20
0
+20 +40 +60 +80 +100
-40 -20
0
+20 +40 +60 +80 +100
Operating ambient temperature Ta (°C)
Operating ambient temperature Ta (°C)
DRVH1 minimum on time vs. Input voltage
DRVH2 minimum on time vs. Input voltage
200
150
100
50
250
200
150
100
50
Ta = + 25°C
Ta = + 25°C
FREQ=GND
FREQ=GND
FREQ=OPEN
FREQ=OPEN
FREQ=VB
FREQ=VB
0
0
5
10
15
20
25
30
5
10
15
20
25
30
Input voltage VIN (V)
Input voltage VIN (V)
DRVH1 minimum on time vs.
DRVH2 minimum on time vs.
Operating ambient temperature
Operating ambient temperature
180
160
140
120
100
80
140
120
100
80
FREQ=GND
FREQ=GND
VCC=12V
VOUT1= 0 V
VCC=12V
VOUT2=0 V
FREQ=OPEN
FREQ=OPEN
60
40
60
FREQ=VB
FREQ=VB
20
40
-40 -20
0
+20 +40 +60 +80 +100
-40 -20
0
+20 +40 +60 +80 +100
Operating ambient temperature Ta (°C)
Operating ambient temperature Ta (°C)
11
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MB39A214A
Minimum off time vs.
Operating ambient temperature
Minimum off time vs. Input voltage
600
550
500
450
400
350
300
250
200
600
550
500
450
400
350
300
250
200
Ta = + 25°C
VCC=12V
5
10
15
20
25
30
-40 -20
0
+20 +40 +60 +80 +100
Input voltage VIN (V)
Operating ambient temperature Ta (°C)
Dead time vs. Operating ambient temperature
Bootstrap diode IF vs. VF
100
60
55
50
45
40
35
30
25
20
tD2
10
1
Ta =+ 85°C
Ta = - 30°C
LX=0V
0.1
VBST=VB
Ta =+25°C
0.01
tD1
0.001
0.2
0.4
0.6
0.8
1
1.2
-40 -20
0
+20 +40 +60 +80 +100
Operating ambient temperature Ta (°C)
VF voltage VF (V)
tD1 : Period from DRVL off to DRVH on
tD2 : Period from DRVH off to DRVL on
12
DS405-00007-2v0-E
MB39A214A
FUNCTION
Bottom detection comparator system for low output voltage ripple
The bottom detection comparator system for low output voltage ripple determines the ON time (tON) using
the input voltage (VIN) and output voltage (VOUT) to hold the ON state to a specified period. During the OFF
period, the reference voltage (INTREF) is compared with the feedback voltage (FB) using the error
comparator (Error Comp.). When the feedback voltage (FB) is below the reference voltage (INTREF) ,
RS-FF is set and the ON period starts again. Switching is repeated as described above. Error Comp. is used
to compare the reference voltage (INTREF) with the feedback voltage (FB) to control the off-duty condition
in order to stabilize the output voltage.
This system adds the inductor current slope detected during the synchronous rectification period (tOFF) to
the reference voltage (INTREF) , and generates an output voltage slope during the OFF period, which is
essential for the bottom detection comparator system, in the IC. This enables the stable control operations
under the low output voltage ripple conditions.
Circuit diagram
VOUT
VIN
Bias
Reg.
VIN
t
ON
generator
Hi-side
Drive
tON
RS-FF
R Q
<Error Comp.>
-
DRVH
RS out
IL
VOUT
FB
Drive
Logic
Bias
S
INTREF
+
Lo-side
Drive
+
-
DRVL
Slope
Detector
VREF
Waveforms
t
ON
DRVH
tOFF
I
L
FB
INTREF
t
13
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MB39A214A
(1) Bias Voltage Block (VB Reg.)
The 5.2 V (Typ) bias voltage is generated from the VCC pin voltage for the control, output, and boost
circuits. When either or both of the EN1 pin (pin 2) and EN2 pin (pin 11) are set to the “H” level, the
system is restored from the standby state to supply the bias voltage from the VB pin (pin 18).
(2) ON/OFF Time Generator Block (tON Generator)
This block contains a capacitor for timing setting and a resistor for timing setting and generates ON time
(tON) which depends on input voltage and output voltage. The switching frequency can be switched by
setting the FREQ pin (pin 7) to any one of GND connection, OPEN, and VB connection. ON time for each
CH is obtained from the following formula.
<FREQ pin : GND connection>
VVOUT1
tON1 (ns) =
4300 (fOSC1
230 kHz)
310 kHz)
VVIN
VVOUT2
VVIN
tON2 (ns) =
3200 (fOSC2
<FREQ pin : OPEN>
VVOUT1
tON1 (ns) =
2100 (fOSC1
1600 (fOSC2
460 kHz)
620 kHz)
VVIN
VVOUT2
tON2 (ns) =
VVIN
<FREQ pin : VB connection>
VVOUT1
tON1 (ns) =
1300 (fOSC1
750 kHz)
VVIN
VVOUT2
VVIN
tON2 (ns) =
1000 (fOSC2
1000 kHz)
The switching frequency of CH2 is set to 1.33 times that of CH1 to prevent the beat by the frequency
difference of channel to channel.
(3) Output Block (DRV1, DRV2)
The output circuit is configured in CMOS type for both of the high-side and the low-side. It provides the
0.5 A (Typ) source current and 0.9 A (Typ) sink current, drive the external N-ch MOS FET. The output
circuit of the high-side FET supplies the power from the boost circuit including the built-in boost diode. The
output circuit of the low-side FET supplies the power from the VB pin. This circuit monitors the gate
voltages of the high-side and low-side FETs. Until either FET is turned off, this circuit controls the ON
timing of another FET, preventing the shoot-through current. The sink ON resistance of the output circuit is
low 1 Ω (Typ), improve the self turn on margin of low-side FET.
14
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MB39A214A
(4) Starting sequence
When the EN1 pin (pin 2) or EN2 pin (pin 11) is set to the “H” level, the bias voltage is supplied from the
VB pin. If the voltage of the VB pin exceeds the UVLO threshold voltage, the DC/DC converter starts
operations and carries out the soft start. The soft start is a function used to prevent a rush current when the
power is started.
Activating the soft start initiates charging of the capacitor connected to the CS1 pin (pin 5) and CS2 pin (pin
8) and inputs the lamp voltage to the error comparator (Error Comp.) of each channel. The DC/DC
converter generates the output voltage according to that lamp voltage. This results in the soft start operation
that does not depend on the output load. The over voltage protection (OVP) and under voltage protection
(UVP) functions are disabled while the soft start is active.
<Timing chart>
UVLO release
EN1
VB
UVLO VTLH
CH1 soft start completed
1.6 V
0.805 V
CS1
DRVH1
DRVL1
INTREF
V
OUT1
EN2
CH2 soft start completed
1.6 V
0.805 V
INTREF
CS2
DRVH2
DRVL2
V
OUT2
15
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MB39A214A
(5) DC/DC converter stop sequence (Discharge, standby)
When the EN1 pin (pin 2) or EN2 pin (pin 11) is set to the “L” level, the output capacitor is discharged
using the discharge FET (RON
25 Ω) in the IC. If the voltage of the VOUT1 pin (pin 3) and VOUT2 pin
(pin 10) is below 0.2 V (Typ) by discharging the output capacitor, the IC stops discharge operation. Further,
if both the EN1 and EN2 pins are set to the “L” level, the IC also stops the output of the VB pin and enters
the standby state after detecting UVLO. The current of the VCC pin (IVCC) is then 10 µA (Max).
<Timing chart>
Standby
EN1
VB
UVLO VTHL
1.6 V
CS1
DRVH1
DRVL1
CH1 discharge FET ON
VOUT1
0.2 V
EN2
CS2
1.6 V
DRVH2
DRVL2
CH2 discharge FET ON
VOUT2
0.2 V
(6) Under Voltage Lockout Protection (UVLO)
The under voltage lockout protection (UVLO) protects ICs from malfunction and protects the system from
destruction/deterioration, according to the reasons mentioned below.
Transitional state when the bias voltage (VB) or the reference voltage (VREF) starts.
Momentary decrease
To prevent such a malfunction, this function detects a voltage drop of the VB pin (pin 18) using the
comparator (UVLO Comp.), and stops IC operations.
When the VB pin exceeds the threshold voltage of the under voltage lockout protection circuit, the system
is restored.
16
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MB39A214A
(7) Over Current Limitation (ILIM)
This function limits the output current when it has increased, and protects devices connected to the output.
This function detects the inductor current IL from the electromotive force of the low-side FET on-resistance
R
ON, and compares this voltage with the 1/5-time value of the voltage VILIM of the ILIM1 pin (pin 20) and
ILIM2 pin (pin 16) on a cyclically, using ILIM Comp. Until this voltage falls below the over current limit
value, the high-side FET is held in the off state. After the voltage has fallen below the limit value, the
high-side FET is placed into the on state. This limits the lower bound of the inductor current and also
restricts the over current. As a result, it becomes operation that the output voltage droops.
The over current limit value is set by connecting the resistor to the ILIM pin. The ILIM pin supplies the
constant current of 5 µA (Typ) . However, the current value has a temperature slope up to 4500 ppm/°C to
compensate the temperature dependence characteristics of the low-side FET on-resistance.
VILIM
ILIM detection value (RON × IL =
)
IL
5
(IOUT1
)
Keep the off state of the high-side FET
until the detection value is gained.
Output voltage setting value
VOUT
DRVH
DRVL
Over current limit operation
Normal operation
17
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MB39A214A
(8) Over Voltage Protection (OVP)
This function stops the output voltage when the output voltage has increased, and protects devices
connected to the output.
1. Using OVP Comp, this function makes a comparison between the voltage which is 1.15 times (Typ) of
the internal reference voltage INTREF1 and INTREF2 (0.7 V), and the feedback voltage for the FB1
pin (pin 4) and the FB2 pin (pin 9).
2. If the feedback voltage mentioned in 1 detects the higher state by 15µs (Typ) or more, the operations
below will be performed.
Set the RS latch.
Set the DRVH1 pin (pin 24) and the DRVH2 pin (pin 13) to the “L” level.
Set the DRVL1 pin (pin 22) and the DRVL2 pin (pin 15) to the “H” level.
These operations fix the high-side FET to the off state and the low-side FET to the on state for both
channels of the DC/DC converter, and stops switching (latch stop).The over-voltage protection state can be
cancelled by setting both the EN1pin (pin 2) and EN2 pin (pin 11) to the “L” level or reducing the VCC
power once until the bias voltage (VB) falls below VTHL of UVLO.
<Timing chart>
VOUT1
Output voltage
setting value
0 V
INTREF1.15
INTREF1.10
FB1
INTREF
0V
DRVH1
DRVL1
CS1
Output voltage
setting value
VOUT2
FB2
0 V
INTREF
0 V
DRVH2
DRVL2
CS2
EN1, EN2
Standby
UVLO VTHL
VB
15 µs
Less than 15 µs
Cancellation of over-voltage protection
state by EN = "L".
18
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MB39A214A
(9) Under Voltage Protection (UVP)
This function stops the output voltage when the output voltage has lowered, and protects devices connected
to the output.
1. Using UVP Comp, this function makes a comparison between the voltage which is 0.7 times (Typ) of
the internal reference voltage REF1, REF2 (0.7 V), and the feedback voltage for the FB1 pin (pin 4) and
the FB2 pin (pin 9).
2. If the feedback voltage mentioned in 1 detects the higher state by 150µs (Typ) or more, the operations
below will be performed.
Set the RS latch.
Set the DRVH1 pin (pin 24) and the DRVH2 pin (pin 13) to the “L” level.
Set the DRVL1 pin (pin 22) and the DRVL2 pin (pin 15) to the “L” level.
These operations fix the high-side FET to the off state and the low-side FET to the off state for both
channels of the DC/DC converter, and stops switching (latch stop). The discharge operation is then carried
out to discharge the output capacitor (The discharge operation continues until the state of the under-voltage
protection is released).
The under-voltage protection state can be cancelled by setting both the EN1 pin (pin 2) and EN2 pin (pin 11)
to the “L” level or reducing the VCC power once until the bias voltage (VB) falls below VTHL of UVLO.
<Timing chart>
Output voltage
setting value
V
OUT1
0 V
INTREF
INTREF 0.8
INTREF 0.7
0 V
FB1
DRVH1
DRVL1
CS1
Output voltage
setting value
V
OUT2
0 V
INTREF
FB2
0 V
DRVH2
DRVL2
CS2
EN1, EN2
Standby
UVLO VTHL
VB
150 µs
Less than 150 µs
Cancellation of over-voltage protection state by EN = "L".
19
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MB39A214A
(10) Over Temperature Protection (OTP)
The over-temperature protection circuit block (OTP) provides a function that prevents the IC from a thermal
destruction. If the junction temperature reaches + 150°C, the DRVH1 pin (pin 24) and DRVH2 pin (pin 13)
are set to the “L” level, and the DRVL1 pin (pin 22 ) and DRVL2 pin (pin 15) are set to the “L” level. This
fixes the high-side and low-side FETs to the off-state, of both channels in the DC/DC converter, causing
switching to be stopped. The discharge operation is then carried out to discharge the output capacitor (The
discharge operation continues until the state of the over-temperature protection is released). If the junction
temperature drops to + 125°C, the soft start is reactivated. (Restored automatically.)
(11) Operation mode
In the PWM-fixed mode, the system acts by the switching frequency specified with the FREQ pin
regardless of the load.
In the automatic PFM/PWM selection mode, the switching frequency is reduced at low load, for enhancing
the conversion efficiency characteristics. This function detects 0 A of the inductor current from the
electromotive force of the low-side FET ON resistance when the low-side FET ON state, and places the
low-side FET into the off state. This idle period continued until the output voltage decreased, this results the
switching frequency being reduced automatically depending on the load current when the inductor current
is below the critical current. The system acts by the switching frequency specified with the FREQ pin, when
the inductor current exceeds the critical current.
For Automatic PFM/PWM selection mode with PAF function, the switching frequency at low load is held to
30 kHz (Min) or more.
The operation mode can be switched by setting the MODE pin (pin 17) to any one of GND connection,
OPEN, and VB connection.
PWM-fixed mode
IOUTx
ILXx
0 A
VLXx
Inductor current in the opposite
direction
Automatic PFM/PWM selection mode
IOUTx
ILXx
0 A
V
LXx
Switching frequency reduced
X : Each channel number
20
DS405-00007-2v0-E
MB39A214A
Enable function table
EN1 pin
EN2 pin
DC/DC converter (CH1)
DC/DC converter (CH2)
L
H
L
L
L
OFF
ON
OFF
OFF
ON
H
H
OFF
ON
H
ON
DC/DC Control mode function table
MODE pin
DC/DC control
GND connection
OPEN
Automatic PFM/PWM selection mode
Automatic PFM/PWM selection mode with PAF function
PWM-fixed mode
VB connection
Switching frequency control function table
FREQ pin
GND connection
OPEN
Switching frequency
fOSC1
fOSC1
fOSC1
230 kHz, fOSC2
460 kHz, fOSC2
750 kHz, fOSC2
310 kHz
620 kHz
1000 kHz
VB connection
Protection function table
The following table shows the state of the VB pin (pin 18), the DRVH1 pin (pin 24), the DRVH2 pin (pin
13), the DRVL1 pin (pin 22), the DRVL2 pin (pin 15) when each protection function operates.
Output of each pin
after detection
Protection
function
DC/DC output
dropping operation
Detection condition
DRVH1, DRVL1,
DRVH2 DRVL2
VB
Under Voltage
Lockout Protection
(UVLO)
Natural electric
discharge
VB < 4.0 V
—
L
L
Over-current
limitation
(ILIM)
V
PGND - VLX1, VLX2
>
The voltage is dropped
by the constant current
5.2 V Switching Switching
VILIM1, VILIM2
Over Voltage
Protection
(OVP)
VFB1, VFB2 >
INTREF1, INTREF21.15 5.2 V
L
L
H
L
0 V clamping
(15 µs or higher)
Under Voltage
Protection
(UVP)
VFB1, VFB2 >
INTREF1, INTREF20.7
Electrical discharge by
discharge function
5.2 V
(150 µs or higher)
Over Temperature
Protection
(OTP)
Electrical discharge by
discharge function
Tj > + 150 °C
5.2 V
5.2 V
L
L
L
L
Enable
(EN)
Electrical discharge by
discharge function
EN1, EN2: H → L
(VOUT1, VOUT2 > 0.2 V)
21
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MB39A214A
I/O PIN EQUIVALENT CIRCUIT DIAGRAM
FB1, FB2 pins
VB
EN1, EN2 pins
VCC
ESD protection
element
EN1
EN2
FB1
FB2
ESD protection
element
GND
GND
FREQ pin
VB
MODE pin
VB
FRWQ
MODE
GND
GND
ILIM1, ILIM2 pins
VOUT1, VOUT2 pins
VB
VB
VOUT1
VOUT2
ILIM1
ILIM2
GND
GND
PGND
22
DS405-00007-2v0-E
MB39A214A
CS pin
VB
DRVL1, DRVL2 pins
VB
DRVL1
DRVL2
CS1
CS2
PGND
GND
DRVH1, DRVH2, BST1, BST2, LX1, LX2 pins
VB
VB pin
VCC
BST1
BST2
VB
DRVH1
DRVH2
GND
LX1
LX2
PGND
VCC pin
VCC
GND
PGND
23
DS405-00007-2v0-E
MB39A214A
EXAMPLE APPLICATION CIRCUIT
VIN
12 V
VIN
19
VCC
VB
3
4
VOUT1
FB1
PGND
18
VIN
1
BST1
DRVH1
LX1
2
5
EN1
CS1
EN1
Q1
Q1
5 6
3
24
23
22
20
4
2
ILIM1
1.0 V, 7 A
L1
VOUT1
PGND
+
7 8
1
17
7
MODE
FREQ
DRVL1
MB39A214A
10
VOUT2
VIN
12
13
14
15
21
BST2
Q3
Q3
5 6
3
DRVH2
LX2
9
4
2
FB2
1.8 V, 7 A
L2
VOUT2
PGND
11
8
EN2
EN2
+
7 8
1
CS2
DRVL2
PGND
16
ILIM2
6
GND
24
DS405-00007-2v0-E
MB39A214A
PART LIST
Component
Item
Specification
Vendor
Package
Part number
Remarks
V
V
DS = 30 V, ID = 6.3 A, 8.6 A,
DualType
(2elements)
FDS6982AS
Q1
Q3
N-ch FET
N-ch FET
FAIRCHILD
SOP8
RON = 23 mΩ, 13 mΩ
DS = 30 V, ID = 6.3 A, 8.6 A,
RON = 23 mΩ, 13 mΩ
DualType
(2elements)
FDS6982AS
FAIRCHILD
SOP8
1 µH (18 A)
L1
L2
Inductor
Inductor
NEC TOKIN
NEC TOKIN
-
-
MPC1055L1R0
MPLC1040L1R5
1.5 µH (12.4 A)
Ceramic
capacitor
10 µF (25 V)
C1-1
MURATA
3216
GRM31CB31E106K
Ceramic
capacitor
10 µF (25 V)
220 µF (2 V)
1000 pF (50 V)
C1-2
C2-1
C2-3
MURATA
SANYO
TDK
3216
D case
1608
GRM31CB31E106K
2TPLF220M6
POSCAP
Ceramic
capacitor
C1608JB1H102K
Ceramic
capacitor
10 µF (25 V)
C3-1
MURATA
3216
GRM31CB31E106K
Ceramic
capacitor
10 µF (25 V)
150 µF (6.3 V)
1000 pF (50 V)
C3-2
C4-1
C4-3
MURATA
SANYO
TDK
3216
D case
1608
GRM31CB31E106K
6TPL150MU
POSCAP
Ceramic
capacitor
C1608JB1H102K
Ceramic
capacitor
0.1 µF (50 V)
0.1 µF (50 V)
0.1 µF (50 V)
4.7 µF (16 V)
3300 pF (50 V)
3300 pF (50 V)
1500 pF (50 V)
1500 pF (50 V)
C5
C6
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
1608
1608
1608
1608
1608
1608
1608
1608
C1608JB1H104K
C1608JB1H104K
C1608JB1H104K
C1608JB1C475K
C1608JB1H332K
C1608JB1H332K
C1608JB1H152K
C1608JB1H152K
Ceramic
capacitor
Ceramic
capacitor
C7
Ceramic
capacitor
C8
Ceramic
capacitor
C12
C13
C14
C15
Ceramic
capacitor
Ceramic
capacitor
Ceramic
capacitor
1.5 kΩ
27 kΩ
68 kΩ
4.3 kΩ
56 kΩ
39 kΩ
150 kΩ
150 kΩ
1.8 Ω
R1-1
R1-2
R2
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
SSM
SSM
SSM
SSM
SSM
SSM
SSM
SSM
KOA
KOA
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
RR0816P152D
RR0816P273D
RR0816P683D
RR0816P432D
RR0816P563D
RR0816P393D
RR0816P154D
RR0816P154D
RK73H1JTTD1R8F
RK73H1JTTD1R0F
R3-1
R3-2
R4
R5
R6
R23
R24
1 Ω
25
DS405-00007-2v0-E
MB39A214A
FAIRCHILD : Fairchild Semiconductor Corporation
SANYO
: SANYO Electric Co., Ltd. / Panasonic
NEC TOKIN : NEC TOKIN Corporation
TDK
: TDK Corporation
MURATA
SSM
: Murata Manufacturing Co., Ltd.
: SUSUMU Co.,Ltd.
26
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MB39A214A
APPLICATION NOTE
1. Setting Operating Conditions
Setting output voltages
The output voltage can be set by adjusting the setting output voltage resistor ratio. Setting output voltage is
calculated by the following formula.
R1 + R2
R2
2.810-7
ΔVOUTx
VOUTx
=
) RON_Sync) +
(0.6946 + 0.2667ΔIL (1−
tOFF
2
VOUT
VIN − VOUT
(VIN − VOUTx
VINfOSC
)
, tOFF =
ΔVOUTx = ESR ΔIL, ΔIL =
L
V
IN fOSC
VOUTx
VIN
: Output setting voltage [V]
: Power supply voltage [V]
: Output ripple voltage value [V]
: Off time [s]
ΔVOUTX
tOFF
RON_Sync : ON resistance of low-side FET [Ω]
: Ripple current peak-to-peak value of inductor [A]
: Series resistance element of output capacitor [Ω]
: Inductor value [H]
ΔIL
ESR
L
fOSC
: Switching frequency [Hz]
VOUT
X
VOUTx
R1
R2
FBX
x: Each channel number
The total resistor value (R1+R2) of the setting output resistor should be selected up to 100 kΩ.
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MB39A214A
Minimum power supply voltage
The maximum on duty is limited by "the minimum off time (tOFFMIN) that an IC holds without fail as a fixed
value" and "the on time (tON) determined by the power voltage value and the output voltage setting value".
The ratio between the output voltage and the power voltage must be less than the maximum on duty.
The minimum power supply voltage that is required to sustain the output voltage can be calculated by the
following formula.
(VOUT + IOUT_MAX (RDC + RON_Main)) VOUT
VIN_MIN
=
VOUT − (VOUT + IOUT_MAX (RDC + RON_Sync)) tOFF_MIN fOSC 1.2
VIN_MIN : Power supply voltage [V]
VOUT : Output setting voltage [V]
IOUT_MAX : Maximum load current value [A]
RON_Main : ON resistance of high-side FET [Ω]
RON_Sync : ON resistance of low-side FET [Ω]
RDC
fOSC
: Series resistance of inductor [Ω]
: Switching frequency setting value [Hz]
tOFF_MIN : Minimum off time (Maximum value) [s]
(For the minimum off time, see “ON/OFF Time [Minimum OFF time ] ” in
“ELECTRICAL CHARACTERISTICS”.)
Use the smaller switching frequency setting in order to make the voltage output possible with the lower
power voltage.
Slope voltages
It is necessary to sustain the Slope voltage 15 mV or higher in order to obtain the stable switching cycle.
The Slope voltage can be calculated by the following formula.
(VIN − VOUT) VOUT RON_Sync
VSlope
=
L VIN fOSC
VSlope
: Slope voltage [V]
VIN
: Power supply voltage [V]
: Output setting voltage [V]
: Switching frequency [Hz]
VOUT
fOSC
RON_Sync : ON resistance of low-side FET [Ω]
: Inductor value [H]
L
28
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MB39A214A
Setting soft-start time
Calculate the soft-start time by the following formula.
ts = 7 105 CCS
ts
: Soft-start time [s] (time until output reaches 100%)
CCS : CS pin capacitor value [F]
Calculate the delay time until the soft-start activation by the following formula.
td = 43 CVB
td
: VB voltage delay time (at VIN = 12 V) [s]
CVB : VB pin capacitor value [F]
When activating the other in the state where a side channel has already been activated (UVLO release: VB
output already), the delay time is hardly generated.
t
s1
ts2
EN1
EN2
V
V
OUT1
td
OUT2
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MB39A214A
Setting switching frequency
The switching frequency is set at the FREQ pin. As for the setting process, see the switching frequency
control function table.
Setting over current limitation
The over current limitation value can be set by adjusting the over current limitation setting resistor value
connected to the ILIM pin.
Calculate the resistor value by the following formula.
ΔIL
2
RLIM = 106 RON_Sync (ILIM
−
)
RLIM
ILIM
: Over current limitation value setting resistor [Ω]
: Over current limitation value [A]
: Ripple current peak-to-peak value of inductor [A]
: ON resistance of low-side FET [Ω]
ΔIL
RON_Sync
ILIM
R
LIM
Inductor current
ILIM
ΔIL
Over current
limitation value
IOUT
0
Time
If the rate of inductor saturation current is small, the inductor value decreases and the ripple current of
inductor increase when the over-current flows. At that time there is a possibility that the limited output
current increases or is not limited, because the bottom of inductor current is detected. It is necessary to use
the inductor that has enough large rate of inductor saturation current to prevent the overlap current.
30
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MB39A214A
The over current limit value is affected by ILIM pin source current and over current detection offset voltage
in the IC except for the on resistance of the low-side FET and the inductor value. The variation of dropped
over current limit value caused by IC characteristics is calculated by the following formula.
2 10-7 RLIM + 0.03
ΔILIM
=
RON_Sync
: The variation of dropped over current limit value [A]
ΔILIM
RLIM
: Over current limitation value setting resistor [Ω]
RON_Sync : ON resistance of low-side FET [Ω]
Inductor current
Over current limit value
ILIM
ΔILIM
Dropped over current limit value due to
IC's characteristics
I
LIM
’
I
O
0
Time
The over current detection value needs to set a sufficient margin against the maximum load current.
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Power dissipation and the thermal design
IC's loss increases, if IC is used under the high power supply voltage, high switching frequency, high load
and high temperature. The IC internal loss can be calculated by the following formula.
PIC = VCC (ICC + QG_Total1 fOSC1 + QG_Total2 fOSC2)
PIC
: IC internal loss [W]
VCC
ICC
: Power supply voltage (VIN) [V]
: Power supply current [A] (2 mA Max)
QG_Total1 : Total quantity of charge for the high-side FET and the low-side FET of each CH1 [C]
QG_Total2 : Total quantity of charge for the high-side FET and the low-side FET of each CH2 [C]
fOSC1
fOSC2
: CH1 switching frequency [Hz]
: CH2 switching frequency [Hz]
Calculate junction temperature (Tj) by the following formula.
Tj = Ta + θja PIC
Tj
: Junction temperature [°C] (+ 125°C Max)
: Ambient temperature [°C]
Ta
: TSSOP-24P Package thermal resistance (+ 78°C /W)
θja
PIC : IC internal loss [W]
Handling of the pins when using a single channel
Although this device is a 2-channel DC/DC converter control IC, it is also able to be used as a 1-channel
DC/DC converter by handling the pins of the unused channel as shown in the following diagram.
“Open”
“Open”
“Open”
VOUTx
FBx
BSTx
DRVHx
DRVLx
CSx
ILIMx
ENx
LXx
Note: x is the unused channel number.
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2. Selecting parts
Selection of smoothing inductor
The inductor value selects the value that the ripple current peak-to-peak value of the inductor is 50% or less
of the maximum load current as a rough standard. Calculate the inductor value in this case by the following
formula.
VIN −VOUT
VOUT
L ≥
LOR IOUT_MAX
V
IN fOSC
L
: Inductor value [H]
IOUT_MAX
LOR
VIN
: Maximum load current [A]
: Ripple current peak-to-peak value of inductor/Maximum load current ratio (= 0.5)
: Power supply voltage [V]
VOUT
fOSC
: Output setting voltage [V]
: Switching frequency [Hz]
It is necessary to calculate the maximum current value that flows to the inductor to judge whether the
electric current that flows to the inductor is a rated value or less. Calculate the maximum current value of
the inductor by the following formula.
ΔIL
2
ILMAX ≥ IOUT_MAX
+
ILMAX : Maximum current value of inductor [A]
IOUT_MAX : Maximum load current [A]
: Ripple current peak-to-peak value of inductor [A]
: Inductor value [H]
ΔIL
L
VIN
VOUT
fOSC
: Power supply voltage [V]
: Output setting voltage [V]
: Switching frequency [Hz]
Inductor current
ILMAX
ΔIL
I
OUT_MAX
Time
0
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Selection of Switching FET
If selecting the high-side FET so that the value of the high-side FET conduction loss and the high-side FET
switching loss is same, the loss is effectively decreased.
Confirm that the high-side FET loss is within the rating value.
PMainFET = PRON_Main + PSW_Main
PMainFET : High-side FET loss [W]
PRON_Main : High-side FET conduction loss [W]
PSW_Main : High-side FET switching loss [W]
High-side FET conduction loss
VOUT
PRON_Main = IOUT_MAX2
RON_Main
VIN
PRON_Main : High-side FET conduction loss [W]
IOUT_MAX : Maximum load current [A]
VIN
: Power supply voltage [V]
: Output voltage [V]
VOUT
RON_Main : ON resistance of high-side FET [Ω]
The high-side FET switching loss can be calculated roughly by the following formula.
PSW_Main
1.56 VIN fOSC IOUT_MAX QSW
PSW_Main : Switching loss [W]
VIN
: Power supply voltage [V]
: Switching frequency [Hz]
fOSC
IOUT_MAX : Maximum load current [A]
QSW
: Amount of high-side FET gate switch electric charge [C]
MOSFET has a tendency where the gate drive loss increases because the lower drive voltage product has
the bigger amount of gate electric charge (QG). Normally, we recommend a 4 V drive product, however, the
idle period at light load (both the high-side FET and the low-side FET is off-period) gets longer and the gate
drive voltage of the high-side FET may decrease, in the automatic PFM/PWM selection mode. The voltage
drops most at no-load mode. At this time, confirm that the boost voltage (voltage between BST-LX pins) is
a big enough value for the gate threshold value voltage of the high-side FET.
If it is not enough, consider adding the boost diode, increasing the capacitor value of the boost capacitor or
using a 2.5 V (or 1.8 V) drive product to the high-side FET.
Select the ON resistance of low-side FET from the range below.
0.2
ΔIL
0.1
0.015
RON_Sync
≤
, RON_Sync ≤
, RON_Sync
≥
ΔIL
ΔIL
)
(ILIM
−
2
RON_Sync
ΔIL
: ON resistance of low-side FET [Ω]
: Ripple current peak-to-peak value of inductor [A]
: Over current detection value [A]
ILIM
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If the formula above has been already satisfied and then a low ON resistance FET as possible is used for the
low-side FET, the loss is effectively decreased. Especially, it works dramatically in the low on duty mode.
The loss of the low-side FET can be calculated by the following formula.
VOUT
PSyncFET = PRON_Sync = IOUT_MAX2 (1 –
) RON_Sync
VIN
PSyncFET : Low-side FET loss [W]
PRON_Sync : Low-side FET conduction loss [W]
IOUT_MAX : Maximum load current [A]
VIN
: Power supply voltage [V]
: Output voltage [V]
VOUT
RON_Sync : ON resistance of low-side FET [Ω]
Turn-on and turn-off voltage of the low-side FET is generally small and the switching loss is small enough
to ignore, so that is omitted here.
Especially, when turning on the high-side FET under the high power supply voltage condition, the
rush-current might be generated by according to self-turn-on of the low-side FET. The parasitic capacitor
value of the low-side FET needs to satisfy the following conditions.
Crss
VTH_Sync
>
VIN
Ciss
VTH_Sync : Threshold voltage of low-side FET [V]
Crss
Ciss
VIN
: Parasitic feedback capacitance of low-side FET [F]
: Parasitic input capacitance of low-side FET [F]
: Power supply voltage [V]
Also approaches of adding a capacitor close between the gate source pins of the low-side FET or adding
resistor between the BST pin and the boost capacitor, and so on are effective as a countermeasure of the
self-turn-on(adding resistor between the BST pin and the boost capacitor is also effective to adjust turn-on
time of the high-side FET).
This device monitors the gate voltage of the switching FET and optimizes the dead time. If the dumping
resistor is inserted among DRVH, DRVL and the switching FET gate to adjust turn-on and turn-off time of
the switching FET, this function might malfunction. In this device, resistor should not be connected among
the DRVH pin, the DRVL pin of IC and the switching FET gate, and should be connected by low
impedance as possible.
The gate drive power of the switching FET is supplied from LDO (VB) of IC inside. Select switching FET
so that the total amount of the switching FET electric charge for 2 channels (QG_Total1, QG_Total2)
satisfies the following formula.
I
VB_MAX > QG_Total1 fOSC1 + QG_Total2 fOSC2
IVB_MAX : VB load current upper limit value (see the following graph) [A]
QG_Total1 : Total quantity of charge for the high-side FET and the low-side FET of each CH1 [C]
QG_Total2 : Total quantity of charge for the high-side FET and the low-side FET of each CH2 [C]
fOSC1
fOSC2
: CH1Switching frequency [Hz]
: CH2 Switching frequency [Hz]
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MB39A214A
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
6
8 10 12 14 16 18 20 22 24 26 28
VIN [V]
Moreover, select the total quantity of the high-side FET electric charge as a guide that does not exceed the
total quantity of the high-side FET electric charge upper limit value shown below.
35
From the top line
FREQ=GND:CH1
30
FREQ=GND:CH2
FREQ=OPEN:CH1
FREQ=OPEN:CH2
25
FREQ=VB:CH1
FREQ=VB:CH2
20
15
10
5
0
5
10
15
20
25
30
Power supply voltage VIN [V]
Whether the mean current value that flows to switching FET is a rated value or less of switching FET is
judged. Each rating value for the switching FET can be calculated roughly by the following formula.
I
I
D_Main > IOUT_MAX D
D_Sync > IOUT_MAX (1 – D)
ID_Main : high-side FET drain current [A]
ID_Sync : Low-side FET drain current [A]
IOUT_MAX : Maximum load current [A]
D
: On-duty
VDSS > VIN
: Voltage between the high-side FET drain and source and the low-side FET drain and
source [V]
VDSS
VIN
: Power supply voltage [V]
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Selection of fly-back diode
This device is improved by adding the fly-back diode when the conversion efficiency improvement or the
suppression of the low-side FET fever is desired, although those are unnecessary to execute normally. The
effect is achieved in the condition where the switching frequency is high or output voltage is lower. Select
schottky barrier diode (SBD) that the forward current is as small as possible. In this DC/DC control IC, the
period for the electric current flow into fly-back diode is limited to dead time period because the
synchronous rectification system is adopted. (as for the dead time, see “Output Block” in “ELECTRICAL
CHARACTERISTICS”). Each rating for the fly-back diode can be calculated by the following formula.
ID ≥ IOUT_MAX fOSC (tD1 + tD2)
ID
IOUT_MAX : Maximum load current [A]
fOSC : Switching frequency [Hz]
: Forward current rating of SBD [A]
tD1, tD2 : Dead time [s]
ΔIL
2
IFSM ≥ IOUT_MAX
+
IFSM
: Peak forward surge current ratings of SBD [A]
IOUT_MAX : Maximum load current [A]
: Ripple current peak-to-peak value of inductor [A]
ΔIL
VR_Fly > VIN
VR_Fly
VIN
: Reverse voltage of fly-back diode direct current [V]
: Power supply voltage [V]
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Selection of input capacitor
Select the input capacitor whose ESR is as small as possible. The ceramic capacitor is an ideal. Use the
tantalum capacitor and the polymer capacitor of the low ESR when a mass capacitor is needed as the
ceramic capacitor can not support.
The ripple voltage is generated in the power supply voltage by the switching operation of DC/DC. Calculate
the lower bound of input capacitor according to an allowable ripple voltage. Calculate the ripple voltage of
the power supply from the following formula.
IOUT_MAX
VOUT
ΔIL
2
+ ESR (IOUT_MAX
+
)
ΔVIN
=
CIN
V
IN fOSC
: Power supply ripple voltage peak-to-peak value [V]
ΔVIN
IOUT_MAX : Maximum load current value [A]
CIN
: Input capacitor value [F]
VIN
: Power supply voltage [V]
VOUT
fOSC
ESR
ΔIL
: Output setting voltage [V]
: Switching frequency [Hz]
: Series resistance component of input capacitor [Ω]
: Ripple current peak-to-peak value of inductor [A]
Capacitor has frequency characteristic, the temperature characteristic, and the bias voltage characteristic, etc.
The effective capacitor value might become extremely small depending on the use conditions. Note the
effective capacitor value in the use conditions.
Calculate ratings of the input capacitor by the following formula:
VCIN > VIN
VCIN : Withstand voltage of the input capacitor [V]
VIN : Power supply voltage [V]
√ VOUT (VIN – VOUT
)
Irms ≥ IOMAX
VIN
Irms : Allowable ripple current of input capacitor (effective value) [A]
IOMAX : Maximum load current value [A]
VIN
: Power supply voltage [V]
VOUT : Output setting voltage [V]
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Selection of output capacitor
A certain level of ESR is required for stable operation of this IC. Use a tantalum capacitor or polymer
capacitor as the output capacitor. If using a ceramic capacitor with low ESR, a resistor should be connected
in series with it to increase ESR equivalently.
Calculate the output capacitor value by the following formula as a guide.
1
COUT
≥
4 fOSC ESR
COUT
: Output capacitor value [F]
fOSC
: Switching frequency [Hz]
ESR
: Series resistance of output capacitor [Ω]
Moreover, the output capacitor values are also derived from the allowable amount of overshoot and
undershoot. The following formula is represented as the worst condition in which the shift time for a sudden
load change is 0s. The output capacitor value allow a smaller amount than the value calculated by the
following formula when a longer shift time.
ΔIOUT2 L
COUT
≥
≥
…Overshoot condition
2 VOUT ΔVOUT_OVER
ΔIOUT2 L (VOUT + VIN fOSC tOFF_MIN
2 VOUT ΔVOUT_UNDER (VIN – VOUT – VIN fOSC tOFF_MIN
)
COUT
… Undershoot condition
)
COUT
: Output capacitor value [F]
: Allowable amount of output voltage overshoot [V]
: Allowable amount of output voltage undershoot [V]
: Current difference in sudden load change [A]
: Inductor value [H]
ΔVOUT_OVER
ΔVOUT_UNDER
ΔIOUT
L
VIN
: Power supply voltage [V]
VOUT
: Output setting voltage [V]
fOSC
: Switching frequency [Hz]
tOFF_MIN
: Minimum off time
When changing to no load suddenly, the output voltage is overshoot, however, the current sink is not
executed in the mode other than PWM fix. As a result, the decrement of the output voltage might take a
long time. This sometimes results in the stop mode because of the over voltage detection. In the mode other
than PWM fix, select the capacitor value so that the overshoot value is set to the over voltage detection
voltage value or less (115% of the output setting voltage or less).
The capacitor has frequency, operating temperature, and bias voltage characteristics, etc. Therefore, it must
be noted that its effective capacitor value may be significantly smaller, depending on the use conditions.
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Calculate each rating of the output capacitor by the following formula:
VCOUT > VOUT
VCOUT : Withstand voltage of the output capacitor [V]
VOUT
: Output voltage [V]
ΔIL
IRMS
≥
2 3
IRMS : Allowable ripple current of output capacitor (effective value) [A]
: Ripple current peak-to-peak value of inductor [A]
ΔIL
When connecting resistance in series configuration while a ceramic capacitor is in use, the resistor rating is
calculated by the following formula.
2
ESRΔIL
PESR
>
12
PESR
ESR
ΔIL
: Power dissipation of resistor [W]
: Resistor value [Ω]
: Ripple current peak-to-peak value of inductor [A]
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Selection of bootstrap capacitor
To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. 0.1 µF is
assumed to be standard, however, it is necessary to adjust it when the high-side FET QG is big. Consider the
capacitor value calculated by the following formula as the lowest value for the bootstrap capacitor and
select a thing any more.
CBST ≥ 10QG
CBST : Bootstrap capacitor value [F]
QG : Total quantity of charge for the high-side FET gate [C]
Calculate ratings of the bootstrap capacitor by the following formula:
CBST > VB
V
VCBST
VB
: Withstand voltage of the bootstrap capacitor [V]
: VB voltage [V]
VB pin capacitor
4.7 µF is assumed to be a standard, and when QG of switching FET used is large, it is necessary to adjust it.
To suppress the ripple voltage by the switching FET gate drive, consider the capacitor value calculated by
the following formula as the lowest value for VB capacitor and select a thing any more.
CVB ≥ 50QG
CVB : VB pin capacitor value [F]
: Total amount of gate charge of high-side FET and low-side switching FET for 2CH [C]
QG
Calculate ratings of the VB pin capacitor by the following formula:
VCVB > VB
VCVB
VB
: Withstand voltage of the VB pin capacitor [V]
: VB voltage [V]
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Layout
Consider the points listed below and do the layout design.
Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor
connected with the VCC and VB pins, and GND pin of the switching system parts with switching system
GND (PGND). Connect other GND connection pins with control system GND (AGND), and separate
each GND, and try not to pass the heavy current path through the control system GND (AGND) as much
as possible. In that case, connect control system GND (AGND) and switching system GND (PGND) at
the single point of GND (PGND) directly below IC. Switching system parts are Input capacitor (CIN),
Switching FET, fly-back diode (SBD), inductor (L) and Output capacitor (COUT).
Connect the switching system parts as much as possible on the surface. Avoid the connection through the
through-hole as much as possible.
As for GND pins of the switching system parts, provide the through hole at the proximal place, and
connect it with GND of internal layer.
Pay the most attention to the loop composed of input capacitor (CIN), switching FET, and fly-back diode
(SBD). Consider parts are disposed mutually to be near for making the current loop as small as possible.
Place the bootstrap capacitor (CBST1, CBST2) proximal to BSTx and LXx pins of IC as much as possible.
Connect the line to the LX pin proximal to the drain pin of low-side FET. Also large electric current
flows momentary in this net. Wire the line of width of about 0.8 mm as standard, and as short as possible.
Large electric current flows momentary in the net of DRVHx and DRVLx pins connected with the gate of
switching FET. Wire the linewidth of about 0.8 mm to be a standard, as short as possible. Take special
care about the line of the DRVLx pin, and wire the line as short as possible.
By-pass capacitor (CVCC, CVB) connected with VCC, and VB should be placed close to the pin as much as
possible. Also connect the GND pin of the bypass capacitor with GND of internal layer in the proximal
through-hole.
Pull the feedback line to be connected to the VOUTx pin of the IC separately from near the output
capacitor pin, whenever possible. Consider the line connected with VOUTx and FBx pins to keep away
from a switching system parts as much as possible because it is sensitive to the noise.
Also, place the output voltage setting resistor connected to this line near IC, and try to shorten the line to
the FBx pin. In addition, for the internal layer right under the component mounting place, provide the
control system GND (AGND) of few ripple and few spike noises, or provide the ground plane of the
power supply as much as possible.
Consider that the discharge current momentary flows into the VOUTx pin (about 200 mA at Vout = 5 V)
when the DC/DC operation stops, and then sustain the width for the feedback line.
There is leaked magnetic flux around the inductor or backside of place equipped with inductor. Line and
parts sensitive to noise should be considered to be placed away from the inductor (or backside of place
equipped with inductor).
Layout example of IC peripheral
Layout example of switching system parts
C
BST1
High-side FET
High-side FET
VIN
1pin
AGND
C
VCC
AGND
Through-hole
CIN
C
IN
Low-side FET
To the LX1 pin
Low-side FET
To the LX2 pin
PGND
PGND
CVB
SBD(option)
SBD (option)
COUT
COUT
Output voltage setting
resistor layout
L
L
PGND
C
BST2
VOUT1
VOUT2
Connect AGND and PGND right under IC
Internal
Surface
Output voltage
VOUT2 feedback
Output voltage
VOUT1 feedback
layer
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REFERENCE DATA
Conversion Efficiency vs.Load Current
Conversion Efficiency vs.Load Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 12V
VIN = 12V
VOUT2 = 1.8V
FREQ = Open
VOUT1 = 1.0V
FREQ = Open
PFM
PAF
PFM
PAF
PWM
PWM
0.001
0.01
0.1
1
10
0.001
0.01
Load Current IOUT1 (A)
*: EN2 Standby mode
Switching Frequency vs. Load Current
0.1
1
10
Load Current IOUT2 (A)
*: EN1 Standby mode
Switching Frequency vs. Load Current
1.E+6
1.E+5
1.E+6
1.E+5
1.E+4
1.E+3
VIN = 12V
VIN = 12V
VOUT2 = 1.8V
FREQ = Open
VOUT1 = 1.0V
FREQ = Open
1.E+4
1.E+3
PFM
PAF
PFM
PAF
PWM
PWM
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Load Current IOUT1(A)
Load Current IOUT2 (A)
Output Voltage vs. Load Current
Output Voltage vs. Load Current
1.89
1.87
1.85
1.84
1.82
1.80
1.78
1.76
1.75
1.73
1.71
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
VIN = 12V
FREQ = Open
VIN = 12V
FREQ = Open
PFM
PAF
PFM
PAF
PWM
PWM
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Load Current IOUT1 (A)
Load Current IOUT2 (A)
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Output Ripple Waveform
Automatic PFM/PWM selection mode
50ms/div
20ms/div
VOUT1 20mv/div
VOUT2 20mv/div
VOUT2 20mV/div
VOUT2 20mv/div
VOUT2 20mV/div
1
1
VIN=12V
VIN = 12V
IOUT2=0A
MODE=GND
FREQ = Open
IOUT1=0A
MODE=GND
FREQ=Open
2µs/div
2µs/div
VOUT1 20mv/div
1
1
VIN = 12V
IOUT1=7A
MODE=GND
FREQ = Open
VIN=12V
IOUT2=7A
MODE=GND
FREQ=Open
Automatic PFM/PWM selection mode with PAF function
10ms/div
5ms/div
VOUT1 20mV/div
1
1
VIN=12V
VIN=12V
IOUT1=0A
MODE=Open
FREQ=Open
IOUT2=0A
MODE=Open
FREQ=Open
PWM-fixed mode
2µs/div
2µs/div
VOUT1 20mv/div
1
1
VIN=12V
VIN=12V
IOUT1=0A
MODE=VB
FREQ=Open
IOUT2=0A
MODE=VB
FREQ=Open
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Switching Waveform
5µs/div
5µs/div
VOUT1 20mv/div
VOUT2 20mV/div
1
1
VIN=12V
VIN=12V
IOUT1=0.1A
MODE=GND
FREQ=Open
IOUT2=0.1A
MODE=GND
FREQ=Open
LX1 5V/div
LX2 5V/div
1
1
1µs/div
1µs/div
VOUT1 20mv/div
VOUT2 20mV/div
1
1
VIN=12V
VIN=12V
IOUT1=7A
MODE=GND
FREQ=Open
IOUT2=7A
MODE=GND
FREQ=Open
LX1 5V/div
LX2 5V/div
1
1
Load Sudden Change Waveform
10µs/div
10µs/div
VOUT1 50mV/div
VOUT2 50mV/div
IOUT2 2A/div
1
1
VIN=12V
MODE=VB
FREQ=Open
VIN=12V
MODE=VB
FREQ=Open
IOUT1 2A/div
0A 4A
0A 4A
1
1
10µs/div
10µs/div
VOUT1 50mV/div
VOUT2 50mV/div
IOUT2 2A/div
1
1
VIN=12V
MODE=GND
FREQ=Open
VIN=12V
MODE=GND
FREQ=Open
IOUT1 2A/div
0A 4A
0A 4A
1
1
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Startup, Shutdown and Protection Function Operation Waveform
500µs/div
500µs/div
VOUT2 500mV/div
VOUT2 500mV/div
VOUT1 500mV/div
1
1
VOUT1 500mV/div
EN1, EN2 10V/div
EN1, EN2 10V/div
3
3
VIN = 12V
VIN = 12V
IOUT1=7A(0.14Ω)
IOUT2=7A(0.26Ω)
MODE=GND
IOUT1=7A(0.14Ω)
IOUT2=7A(0.26Ω)
MODE=GND
FREQ=Open
FREQ=Open
500µs/div
500µs/div
EN1 10V/div
EN1 10V/div
3
3
VOUT1 500mV/div
VOUT1 500mV/div
LX1 10V/div
VIN=12V
IOUT1=7A(0.14Ω)
MODE=GND
FREQ=Open
1
1
VIN=12V
LX1 10V/div
IOUT1=7A(0.14Ω)
MODE=GND
FREQ=Open
2
2
Output Over Current Waveform
VOUT1 500mV/div
100µs/div
IOUT1 5A/div
1
VIN=12V
MODE=VB
FREQ=Open
4
LX1 10V/div
2
Normal operation
Under voltage protection
Over
current
protection
46
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USAGE PRECAUTION
1. Do not configure the IC over the maximum ratings.
If the IC is used over the maximum ratings, the LSI may be permanently damaged.
It is preferable for the device to normally operate within the recommended usage conditions. Usage outside
of these conditions can have an adverse effect on the reliability of the LSI.
2. Use the device within the recommended operating conditions.
The recommended values guarantee the normal LSI operation under the recommended operating conditions.
The electrical ratings are guaranteed when the device is used within the recommended operating conditions
and under the conditions stated for each item.
3. Printed circuit board ground lines should be set up with consideration for common impedance.
4. Take appropriate measures against static electricity.
Containers for semiconductor materials should have anti-static protection or be made of conductive
material.
After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
Work platforms, tools, and instruments should be properly grounded.
Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ in serial body and ground.
5. Do not apply negative voltages.
The use of negative voltages below ─0.3 V may make the parasitic transistor activated to the LSI, and can
cause malfunctions.
47
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MB39A214A
ORDERING INFORMATION
Part number
Package
Remarks
24-pin plastic TSSOP
(FPT-24P-M09)
MB39A214APFT
EV BOARD ORDERING INFORMATION
EV board number
EV board version No.
Remarks
MB39A214A-EVB-01
MB39A214A-EVB-01 Rev. 1.0
TSSOP-24
48
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MB39A214A
RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION
The LSI products of FUJITSU SEMICONDUCTOR with “E1” are compliant with RoHS Directive, and has
observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB),
and polybrominated diphenyl ethers (PBDE). A product whose part number has trailing characters “E1” is
RoHS compliant.
MARKING FORMAT (Lead Free version)
39A214A
XXXX
E1
XXX
Lead-free version
INDEX
49
DS405-00007-2v0-E
MB39A214A
LABELING SAMPLE (Lead free version)
Lead-free mark
JEITA logo JEDEC logo
MB123456P - 789 - GE1
(3N) 1MB123456P-789-GE1 1000
G
Pb
(3N)2 1561190005 107210
QC PASS
PCS
1,000
MB123456P - 789 - GE1
ASSEMBLED IN JAPAN
2006/03/01
MB123456P - 789 - GE1
1/1
1561190005
0605 - Z01A 1000
"ASSEMBLED IN CHINA" is printed on the label
of a product assembled in China.
The part number of a lead-free product has
the trailing characters "E1".
50
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MB39A214A
MB39A214APFT RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY
LEVEL
[FUJITSU SEMICONDUCTOR Recommended Mounting Conditions]
Item
Condition
IR (infrared reflow), warm air reflow
2 times
Mounting Method
Mounting times
Please use it within two years after
Before opening
manufacture.
From opening to the 2nd reflow
Less than 8 days
Storage period
Please process within 8 days
after baking (125°C ±3°C, 24H+ 2H/─0H) .
Baking can be performed up to two times.
When the storage period after
opening was exceeded
Storage conditions
5°C to 30°C, 70% RH or less (the lowest possible humidity)
[Mounting Conditions]
(1) IR (infrared reflow)
260°C
245°C
Main heating
170 °C
to
190 °C
(b)
(c)
(d)
(e)
RT
(a)
(d')
"M" rank : 250°C Max
(a) Temperature Increase gradient
(b) Preliminary heating
(c) Temperature Increase gradient
(d) Peak temperature
: Average 1°C/s to 4°C /s
: Temperature 170°C to 190°C, 60 s to 180 s
: Average 1°C /s to 4°C /s
: Temperature 250°C Max; 245°C or more, 10 s or less
: Temperature 230°C or more, 40 s or less
or
(d') Main Heating
Temperature 225°C or more, 60 s or less
or
Temperature 220°C or more, 80 s or less
: Natural cooling or forced cooling
(e) Cooling
Note: Temperature : the top of the package bod
51
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MB39A214A
(2) Manual soldering (partial heating method)
Item
Condition
Before opening
Within two years after manufacture
Within two years after manufacture
(No need to control moisture during the storage
period because of the partial heating method.)
Storage period
Between opening and mounting
Storage conditions
5°C to 30°C, 70% RH or less (the lowest possible humidity)
Temperature at the tip of a soldering iron: 400°C Max
Mounting conditions
Time: Five seconds or below per pin*
*: Make sure that the tip of a soldering iron does not come in contact with the package body.
52
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MB39A214A
PACKAGE DIMENSIONS
24-pin plastic TSSOP
Lead pitch
0.50 mm
4.40 mm × 6.50 mm
Gullwing
Package width ×
package length
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.20 mm MAX
0.08 g
(FPT-24P-M09)
24-pin plastic TSSOP
(FPT-24P-M09)
Note 1) Pins width and pins thickness include plating thickness.
Note 2) Pins width do not include tie bar cutting remainder.
Note 3) #: These dimensions do not include resin protrusion.
#
6.50± 0.10 (.256±. 004)
0.145± 0.045
(.0057±. 0018)
24
13
BTM E-MARK
#
4.40± 0.10 6.40± 0.20
(.252±. 008)
(.173±. 004)
INDEX
Details of "A" part
1.10+–00..1105
.043+–..000046
(Mounting height)
1
12
"A"
0.20+–00..072
0.50(.020)
M
0.13(.005)
0~8°
.008+–..000031
0.10± 0.05
0.60± 0.15
(.024±. 006)
(Stand off)
(.004±. 002)
0.10(.004)
Dimensions in mm (inches).
Note: The values in parenthesesare reference values.
C
2007-2010 FUJITSU SEMICONDUCTOR LIMITED F24032S-c-2-5
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
53
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MB39A214A
MAJOR CHANGES IN THIS EDITION
A change on a page is indicated by a vertical line drawn on the left side of that page.
Page
Section
FUNCTION
(9) Under Voltage Protection (UVP)
Change Results
Corrected the timing chart as follows.
Less than 15 μs → Less than 150 μs
19
24
EXAMPLE APPLICATION CIRCUIT Revised the figure.
PART LIST
Revised the symbol Q1, Q3, R1-1, R3-1 and R4 to
R6.
25, 26
Added the symbol C14, C15, R23 and R24.
Revised the company name.
43 ~ 46
REFERENCE DATA
Revised the figure.
54
DS405-00007-2v0-E
MB39A214A
CONTENTS
page
DESCRIPTION·····································································································································1
FEATURES···········································································································································1
APPLICATIONS···································································································································1
PIN ASSIGNMENT······························································································································2
PIN DESCRIPTIONS ···························································································································3
BLOCK DIAGRAM ·····························································································································4
ABSOLUTE MAXIMUM RATINGS ··································································································5
RECOMMENDED OPERATING CONDITIONS···············································································6
ELECTRICAL CHARACTERISTICS·································································································7
TYPICAL CHARACTERISTICS·······································································································10
FUNCTION·········································································································································13
I/O PIN EQUIVALENT CIRCUIT DIAGRAM·················································································22
EXAMPLE APPLICATION CIRCUIT ······························································································24
PART LIST··········································································································································25
APPLICATION NOTE ·······················································································································27
REFERENCE DATA···························································································································43
USAGE PRECAUTION ·····················································································································47
ORDERING INFORMATION············································································································48
EV BOARD ORDERING INFORMATION ······················································································48
RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION ····································49
MARKING FORMAT (Lead Free version)························································································49
LABELING SAMPLE (Lead free version) ························································································50
MB39A214APFT RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL ···51
PACKAGE DIMENSIONS·················································································································53
MAJOR CHANGES IN THIS EDITION···························································································54
CONTENTS········································································································································55
55
DS405-00007-2v0-E
MB39A214A
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
Asia Pacific
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
Tel: +1-408-737-5600
Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Europe
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
30F, Kerry Parkside, 1155 Fang Dian Road,
Pudong District, Shanghai 201204, China
Tel : +86-21-6146-3688 Fax : +86-21-6146-3660
http://cn.fujitsu.com/fss/
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
Korea
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
2/F, Green 18 Building, Hong Kong Science Park,
Shatin, N.T., Hong Kong
Tel : +852-2736-3232 Fax : +852-2314-4207
http://cn.fujitsu.com/fsp/
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely
for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU
SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When
you develop equipment incorporating the device based on such information, you must assume any responsibility arising
out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as
license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of
FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of
any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR
assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would
result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use
requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or
damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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