MB39C001PVB_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS04-27243-1E

ASSP For Power Supply Applications

(Switching FET Integrated DC/DC Converter)

1ch PFM/PWM Synchronous

Rectification Step-down Regulator

MB39C001

■ DESCRIPTION

The MB39C001 is a synchronous rectification type of single-channel, step-down DC/DC converter IC using current

mode control.

The MB39C001 integrates switching FETs, an oscillator, error amplifier, voltage detector, and a reference voltage

generator in a 18-pin BCC package. The required external components are only a coil and decoupling capacitors.

The MB39C001 is small in size, and can achieve a DC/DC converter highly effective in the full load range, and it

is the best for internal power supplies for portable devices such as cellular phones, PDAs and DSC.

■ FEATURES

• High efficiency

: 96% Max

• Quiescent current

: 20 µA (in PFM mode)

• Output current (DC/DC) : 600 mA Max

• Input voltage range

: 2.5 V to 5.5 V

• Oscillation frequency

• No flyback diode needed

: 1.0 MHz (in PWM mode)

• Low dropout operation : 100% on-duty support

(Continued)

■ PACKAGE

18-pin plastic BCC

(LCC-18P-M05)

MB39C001

(Continued)

• High-precision reference voltage generator integrated : 1.25 V ± 2% (with no load)

• Output voltage select function integrated

: Capable of selecting internal setting (3 bits) or

external setting

• Built-in switching FETs

: PMOS 0.43 Ω (Typ) , NMOS 0.32 Ω (Typ)

• Current mode control providing quick transition response to inputs/loads

• Built-in temperature protection function

• Low consumption current at shutdown mode

• Built-in undervoltage lockout protection circuit (UVLO) : Circuit actuation voltage of 2.3 V (Typ)

• Small package : BCC-18P

: 1 µA or less

2

MB39C001

■ PIN ASSIGNMENT

(TOP VIEW)

DVDD1

14

VSET1

VSET2

VSET3

11

13

12

DVDD2

15

10

AVDD

CNT

9

8

7

VSEL

16

17

18

MB39C001

AGND

DGND1

DGND2

VREFIN

6

POWER GOOD

1

2

3

4

5

LX1

LX2

VRSEL

OUT

VREF

LCC-18P-M05

■ PIN DESCRIPTION

Pin No.

Symbol

I/O

Description

Inductor connection output terminals. Connect mutually and use the LX1

and LX2 terminal. They enter the high impedance state at shutdown.

1, 2

LX1, LX2

O

I

Reference voltage switch terminal. (Refer (2) “Setting output voltages”

in ■ APPLICATION NOTES)

3

VRSEL

4

5

OUT

I

Output voltage feedback terminal.

VREF

O

Reference voltage (1.25 V) output terminal.

POWERGOOD circuit output terminal.

An N-ch MOS open-drain circuit is connected.

6

POWER GOOD

O

I

7

8

VREFIN

AGND

Error amplifier (ErrorAmp) noninverting input terminal.

Control block ground terminal.

9

CNT

I

Control input terminal (L : Shutdown, H : Normal operation ) .

Control block power-supply terminal.

10

AVDD

11

VSET3

I

Output voltage setting terminal. (Refer (2) “Setting output voltages” in

■ APPLICATION NOTES)

12

VSET2

13

VSET1

14, 15

DVDD1, DVDD2

Drive block power-supply terminal.

Output voltage switch terminal. (Refer (2) “Setting output voltages” in

■ APPLICATION NOTES.)

16

VSEL

I

17, 18 DGND1, DGND2

Drive block ground terminal.

3

MB39C001

■ I/O TERMINAL EQUIVALENT CIRCUIT DIAGRAM

DVDD1

DVDD2

AVDD

LX1

LX2

VREF

DGND1

DGND2

AGND

AVDD

POWER GOOD

VRSEL,

VSET1,

VSET2,

VSET3,

AGND

VSEL

AGND

AVDD

VREFIN

OUT

AGND

AVDD

CNT

AGND

* : ESD protection element

4

MB39C001

■ BLOCK DIAGRAM

VIN

AVDD DVDD2

10

DVDD1

15 14

CNT

9

To each block

ERR

Amplifier

OUT

4

−

+

Iout

Comparator

R

6

POWER GOOD

DET

PFM/PWM

Logic

Control

VSEL

16

LX1

LX2

VOUT

VSET1

13

1

2

VSET2

12

SELECT

L

VSET3

11

C

VREF

5

1.25 V

Ref

7

3

8

18 17

VREFIN

VRSEL

AGND DGND2 DGND1

5

MB39C001

■ FUNCTIONS

About the Current Mode

Conventional voltage mode control compares the voltage (Vc) obtained by applying negative feedback to the

output voltage using the ErrAmp with the reference triangular waveform (Vtri) to control the on-duty cycle, thereby

regulating the output voltage.

Current mode control uses the oscillator (rectangular waveform generator) , and the voltage (V^IDET) obtained by

applying I-V conversion to the current which flows into SW FET, and uses them in place of the triangular waveform.

Current-mode control compares the voltage (Vc) obtained by applying negative feedback to the output voltage

using the ErrAmp with VIDET to control the on-duty cycle, thereby regulating the output voltage.

Voltage mode control model

Current mode control model

VIN

Oscillator

Vc

−

+

S

Vc

−

Q

R

+

SR-FF

Vtri

VIDET

Vc

VIDET

Vc

Vtri

tON

tOFF

tON

Note : The above models illustrate principles of operation; they are slightly different from actual

operations of the IC.

Function of Each Block

• PFM/PWM Logic Control Circuit

This circuit controls the synchronous rectification of internal P-channel MOS FET and N-channel MOS FET

at the frequency (1 MHz), set by the internal oscillator (rectangular waveform oscillator) during normal oper-

ation. Under light loads, the circuit performs intermittent (burst) operation.

The precaution of the penetration current caused by synchronous rectification and the reverse current flowing

during discontinuous operation are performed to this circuit.

• Iout Comparator Circuit

This circuit detects the current (I^LX) flowing from the internal P-channel MOS FET to the external inductor.

The circuit compares the output of ErrAmp with VIDET, obtained by applying I-V conversion to the ILX peak current

(IPK), and approaches the PFM/PWM Logic Control circuit to turn off the internal P-channel MOS FET.

6

MB39C001

• ErrAmp phase compensation circuit

This circuit compares reference voltages such as VREF with output voltages. The IC contains a phase com-

pensation circuit and adjusted for the best operation of this IC, and it is eliminating the need for nominating a

phase compensation circuit and adding an external component for phase compensation.

• VREF circuit

A high-accuracy reference voltage is generated by a BGR (band gap reference) circuit. The output voltage is

1.25 V (Typ).

• SELECT circuit

This circuit is used to select a pre-set output voltage. The voltage can be set by changing the division resistance

value at the earlier stage of the ErrAmp.

• DET circuit

This circuit monitors the OUT terminal voltage. When that voltage reaches the output set voltage, the open-

drain output at the POWER GOOD terminal is turned on.

• Protection circuit

An over temperature protection circuit is built in the IC as a protection circuit.

The over temperature protection circuit turns off both of the N-channel and P-channel SW FETs when the

junction temperature reaches 135°C.

Also, when the junction temperature falls to 110 °C, the over temperature protection circuit operates normally.

Although the IC has no overcurrent protection circuit as a dedicated circuit, it uses current mode control for

voltage control, and thus the peak-current value is monitored and controlled at any time. (The maximum peak-

current value is 1 A.)

7

MB39C001

■ ABSOLUTE MAXIMUM RATINGS

Ratings

Unit

Parameter

Symbol

Condition

Min

Max

AVDD, DVDD1, and DVDD2

terminals

Power supply voltage

V^IN

7

V

OUT terminal

−0.3

VDD + 0.3

V^DD+ 0.3

CNT, VSEL, VSET1, VSET2,

VSET3, and VRSEL terminals

Input voltage

VI

V

VREFIN terminal

V^DD+ 0.3

7

POWER GOOD pull-up voltage

LX voltage

VIPG

V^LX

IPK

V

LX1/LX2 terminal

Ta ≤ + 25 °C

−0.3

VDD + 0.3

1.3

LX peak current

A

Power dissipation

P^D

540*

mV

°C

Operating ambient temperature

Storage temperature

Ta

−40

+ 85

TSTG

− 55

+ 125

* : The package is mounted on a 10x10-cm square, dual sided epoxy board.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■ RECOMMENDED OPERATING CONDITIONS

Values

Parameter

Symbol

Condition

Unit

Min

Typ

Max

AVDD, DVDD1, and

DVDD2 terminals

Power supply voltage

V^IN

2.5

3.7

5.5

V

VREFIN voltage

LX current

V^RIN

I^LX

—

VIN – VOUT ≥ 0.7 V*

—

0.3

—

0.7

600

1

V

mA

POWERGOOD current

IPG

—

* : The output possible current can be tends to decrease when the voltage difference between the power supply

voltage (VIN) and DC/DC converter output voltage (VOUT) is small. This is because of an effect of slope compen-

sation; it does not lead to the breakdown of the device. If it is the using condition which suppresses the output

current, it is possible to use it also with “VIN-VOUT<0.7 V”.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

8

MB39C001

■ ELECTRICAL CHARACTERISTICS

(Unless otherwise specified , VIN = 3.7 V, CNT = 3.7 V, VSET1 = VSET2 = 0 V, VSET3 = VSEL = 3.7 V,

VRSEL = 0 V, Ta = +25°C)

Values

Symbol

Parameter

Pin No.

Condition

Unit

Min

1.21 1.25 1.29

VREFIN = 0.6 V, VRSEL = 3.7 V −100 −40

Typ

Max

Reference voltage

Input current

V^REF

I^REFIN

VOUT

5

7

VREF = 0 mA

V

nA

V

Output voltage

Load current = −200 mA*^l

1.764 1.8 1.836

2.5 V < DVDD = AVDD < 5.5 V*²

Load current = 0 mA

Input stability

Load stability

Line

Load

R^OUT

40

20

mV

4

−200 mA > Load current >

−600 mA

OUT terminal

Input impedance

OUT = 2.0 V

OUT = 90%

1.01

MΩ

DC/DC

converter LX peak current

I^PK

fosc

f^SHORT

t^PG

1

A

block

1, 2

6

0.8

1.0

170

80

1.2 MHz

240 kHz

µs

Oscillation

frequency

OUT = 0 V

100

Rise delay time

SW PMOS-FET

ON resistor

RPMOS

RNMOS

I^LEAK

LX1 + LX2 = −100 mA

LX1 + LX2 = 100 mA

0.43

0.32

Ω

SW NMOS-FET

ON resistor

1, 2

SW FET leak

current

1

µA

Input threshold

voltage

3,9,11, CNT, VSEL, VSET1, VSET2,

12,13,16 VSET3, VRSEL terminal

VTH

0.3

1.0

0

1.5

1

V

Output

voltage

select

block

9

CNT terminal

µA

Input current

I^I

3,11,12, VSEL, VSET1, VSET2, VSET3,

13,16 VRSEL terminal

0.1

1

Over temperature

protection (junc-

tion temperature)

T^OTPH

135*

110*

°C

4

TOTPL

Protection

circuit

block

V^THH

2.3

V

UVLO

threshold voltage

VTHL

4, 10,

2.15

14, 15

UVLO hysteresis

width

V^HYS

0.15

V

* : Standard design value

(Continued)

9

MB39C001

(Continued)

(Unless otherwise specified , VIN = 3.7 V, CNT = 3.7 V, VSET1 = VSET2 = 0 V, VSET3 = VSEL = 3.7 V,

VRSEL = 0 V, Ta = +25°C)

Values

Unit

Symbol

Parameter

Pin No.

4, 6

Condition

Min

86

Typ Max

V^THHPG

VTHLPG

V^HYSPG

VOL

90

88

2

94

92

%

Threshold voltage

*3

POWER

GOOD

circuit

84

Hysteresis width

Output voltage

Output current

%

POWER GOOD = 25 µA

POWER GOOD = 5.5 V

0.1

1

V

block

6

I^OH

µA

Powersupplycurrent

at shutdown

I^VDD1

I^VDD2

I^VDD3

CNT = 0 V, All circuits = OFF*⁴

1

µA

10, 14,

15

Powersupplycurrent

on standby

General

Load current = 0 mA

20

35

Powersupplycurrent

during operation

VOUT = 90% or OUT = 1.62 V*⁵

300

400 µA

* : Standard design value

*1 : Refer (2) “Setting output voltages” in ■ APPLICATION NOTES.)

*2 : The minimum V^INvalue is 2.5 V or “output voltage setting value + 0.4 V”, either high one.

*3 : Detection to the output voltage setting value by VSET1 to VSET3. Refer (2) “Setting output voltages”

in ■ APPLICATION NOTES.)

*4 : The sum of the currents flowing to the AVDD terminal, DVDD1 terminal, and DVDD2 terminal.

*5 : Current consumption at a duty cycle of 100% (with the main SW FET full-on). The SW FET gate drive current

is not included because of a full-on state (not performing SW operation). And, the load current is not similarly

included.

10

MB39C001

■ TYPICAL OPERATING CHARACTERISTICS

(The following characteristics are provided for setup reference purposes only; they are not guaranteed

characteristics.)

Conversion efficiency vs. Load current

100

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

VIN = 2.7 V

VIN = 3.7 V

VIN = 4.5 V

VIN = 4.5 V Ta = +25 °C

L = 3.3 µH

Ta = +25 °C

L = 3.3 µH

C = 10 µF

VOUT = 1.8 V

VOUT = 2.5 V

0.1

1

10

100

1000

0.1

1

10

100

1000

Load current IOUT (mA)

Conversion efficiency vs. Load current

Output voltage vs. Load current

1.84

1.82

1.80

1.78

1.76

1.74

100

95

90

85

80

75

70

65

60

55

50

VIN = 3.7 V

VIN = 4.5 V

Ta = +25 °C

L = 3.3 µH

C = 10 µF

Ta = +25 °C

VIN = 3.7 V

VOUT = 1.8 V

VOUT = 3.3 V

0

100

200

300

400

500

600

0.1

1

10

100

1000

Load current IOUT (mA)

(Continued)

11

MB39C001

Output voltage vs. Power supply voltage

Reference voltage vs. Ambient temperature

1.30

1.90

1.88

1.86

1.84

1.82

1.80

1.78

1.76

1.74

1.72

1.70

1.28

1.26

IOUT = 0 A

1.24

IOUT = 600 mA

1.22

VIN = 3.7 V

VOUT = 1.8 V

Ta = +25 °C

VOUT = 1.8 V

1.20

−50

−25

0

25

50

75

100

2.0

3.0

4.0

5.0

6.0

Power supply voltage VIN (V)

Ambient temperature Ta ( °C)

Oscillation frequency vs. Power supply voltage

Oscillation frequency vs. Ambient temperature

1.2

1.1

1.0

0.9

1.1

1.0

0.9

Ta = +25 °C

VOUT = 1.8 V

VIN = 3.7 V

IOUT = 600 mA

0.8

−50

−25

0

25

50

75

100

2

3

4

5

6

Power supply voltage VIN (V)

Ambient temperature Ta ( °C)

(Continued)

12

MB39C001

Power supply current vs.

Ambient temperature

Power supply current vs.

Power supply voltage

50

45

40

35

30

25

20

15

10

5

50

45

40

35

30

25

20

15

10

5

Ta = +25 °C

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 0 A

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 0 A

0

2

3

4

5

6

−50

−25

0

25

50

75

100

Power supply voltage VIN (V)

Ambient temperature Ta ( °C)

SW FET ON resistance vs.

Power supply voltage

Oscillation frequency − V^REFINvoltage

0.7

1.2

0.6

0.5

0.4

0.3

0.2

0.1

0.0

1.0

0.8

0.6

0.4

0.2

0.0

Pch

Nch

Ta = +25 °C

VIN = 3.7 V

IOUT = 200 mA

Ta = +25 °C

2

3

4

5

6

0.0

0.2

0.4

0.6

0.8

1.0

VREFIN voltage (V)

Power supply voltage VIN (V)

(Continued)

13

MB39C001

Nch SW FET ON resistance vs.

Ambient temperature

Pch SW FET ON resistance vs.

Ambient temperature

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

VIN = 2.5 V

VIN = 3.7 V

VIN = 5.5 V

−50

−25

0

25

50

75

100

−50

−25

0

25

50

75

100

Ambient temperature Ta ( °C)

Power dissipation vs.

Ambient temperature

600

540

500

400

300

210

200

100

0

−50 −25

0

25

50

75⁸⁵100 125

Ambient temperature Ta ( °C)

(Continued)

14

MB39C001

Output waveforms at load sudden changes

VOUT 200 mV/div

IOUT 0.5 A/div

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 0 mA to 600 mA

20 µs/div

Output waveforms at load sudden changes

VOUT 200 mV/div

IOUT 0.5 A/div

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 200 mA to 600 mA

20 µs/div

(Continued)

15

MB39C001

Output waveforms at load sudden changes

VOUT 200 mV/div

IOUT 0.5 A/div

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 100 mA to 600 mA

20 µs/div

Switching waveforms (continuous operation)

VOUT 20 mV/div

VLX 2 V/div

ILX 0.5 A/div

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 600 mA

400 ns/div

(Continued)

16

MB39C001

(Continued)

Switching waveforms (during burst operation)

VOUT 100 mV/div

VLX 2 V/div

ILX 0.5 A/div

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 100 mA

2 µs/div

CNT terminal response characteristics

VOUT 1 V/div

ILX 0.5 A/div

VCNT 2 V/div

VIN = 3.7 V

VOUT = 1.8 V

IOUT = 600 mA

20 µs/div

17

MB39C001

■ TYPICAL OPERATING CHARACTERISTICS MEASUREMENT CIRCUIT

VDD

VIN

AVDD

OUT

DVDD1, DVDD2

LX1, LX2

C2

C5

VOUT

Load current

L1

VRSEL

× 3

VSET1 to VSET3

CNT

C1

lOUT

GND

R1

AGND

DGND1, DGND2

COMPONENT

ITEM

Specification

Vendor

ssm

Parts No.

PFR05Q-105-D-1

C2012JB1A475K

C1608JB1H103K

C2012JB0J106M

VLF4012AT-3R3M

R1

C2

C5

C1

L1

Resistor

1 MΩ

4.7 µF

0.01 µF

10 µF

Ceramic condenser

Inductor

TDK

3.3 µH

TDK

ssm : SUSUMU CO., LTD.

TDK : TDK Corporation

Note : The above components are recommended parts confirmed by Fujitsu to operate normally.

18

MB39C001

■ APPLICATION NOTES

(1) Selection of components

• Selection of external inductor

The design of the inductor is basically unnecessary. This IC is designed to operate efficiently with a 3.3 µH

inductor.

Select the inductor whose rated saturation current is larger than the LX peak current in the operating conditions,

and select the inductor whose DC resistance is as low as possible (150 mΩ or less is recommended) .

The LX peak current value (I^PK) is obtained from the following formula :

VIN − VOUT

D

1

2

(VIN − VOUT) • VOUT

2 • L • fsw • VIN

I^PK= IOUT +

•

= IOUT +

L

fsw

L

: External inductor value

I^OUT: Load current

V^IN: Power supply voltage

V^OUT: Output setting voltage

D

: Switching on-duty cycle ( = VOUT / VIN)

fosc : Switching frequency (fixed at 1 MHz)

Example : Peak current maximum value (I^PK) : At VIN = 3.7 V, VOUT = 1.8 V, IOUT = 0.6 A, L = 3.3 µH.

(V^IN− VOUT) • VOUT

(3.7 V − 1.8 V) • 1.8 V

IPK = IOUT +

= 0.6 A +

=: 0.74 A

2 • L • fsw • V^IN

2 • 3.3 µH • 1 MHz • 3.7 V

• Selection of I/O condenser

• Select the DVDD input condenser whose equivalent series resistance (ESR) is low in particular, to suppress

the loss by ripple currents.

• Better line regulation and load regulation characteristics can be obtained by adding an input condenser im-

mediately close to AVDD. Although the appropriate capacitance may be different depending on the layout

design, the reference range for selection is from , 1000 pF to 0.01 µF.

• The output condenser should also have low equivalent series resistance (ESR). The ripple current of the

fluctuation portion of the inductor current, it flows into the output condenser. The ripple voltage is the product

of this fluctuation portion and ESR, it is generated at the output. The output capacitance significantly affects

the stability of operation as a DC/DC converter. In principle, an output condenser of about 10 µF is recom-

mended. If there is a problem with the ripple voltage, you can work around the problem by selecting one with

large capacitance.

• Condenser types

Selecting ceramic condenser for both of input and output is effective for reduction in ESR and size. Since

power supply circuits are heat generators, you should avoid using ceramic condenser which have an F tem-

peraturecharacteristic(-80% to+20%). YoushouldusethosewithaBcharacteristic(± 10% to± 20%)orthelike.

Avoid using normal electrolytic condenser as their ESR is high.

Tantalum condenser are effective for reduction in ESR but are very dangerous as they have a disadvantage,

they establish a short mode if a failure occurs. When using a Tantalum condenser, choose one with a fuse.

19

MB39C001

(2) Setting output voltages

When output voltages are set in advance, only treat the control terminals as shown in the table below. Any

additional component such as a voltage dividing resistor is not required.

As VSET1 to VSET3, VSEL, and VRSEL terminals have built-in pull-down equal circuits, their level is equal to

“L” when opened.

Note : For a circuit configuration example, refer (1) “Setting 1.8-V output using the internal reference voltage”

in ■ APPLICATION EXAMPLES.

• Output voltage setting table 1

VSET1

VSET2

VSET3

VSEL

VRSEL

V^OUT

1.1 V

0.8 V

1.2 V

1.3 V

1.1 V

1.5 V

1.1 V

1.8 V

2.5 V

2.8 V

3.3 V

L

X

L

H

L

H

X

L

H

L

H

L

H

L

H

L

H

L

H

X

H

L

H

X : Don’t care

To set arbitrary voltages other than above, set VRSEL to “H” and apply voltage to VREFIN. The voltage applied

to VREFIN is supplied either from external or by dividing VREF using a resistor. The output voltage using

VREFIN with VREF resistor-divided is obtained from the following formula :

R8

1.25

0.6

VOUT = (Output voltage setting value) • Kv

Kv =

•

R7 + R8

R8

R7 + R8

(VREFIN voltage :

× 1.25 Refer (4) “VREFIN terminal in ■ NOTES ON CIRCUIT DESIGN”.

Note : For a circuit configuration example, refer (2) “Supplying the VREF terminal voltage to the reference voltage

external input (VREFIN) after resistor voltage division and setting the V^OUTvoltage to 1.25 V with VOUT setting

gain doubled” in ■ APPLICATION EXAMPLES.

The output voltage is determined by the resistor ratio. Select the resistance value so that the current flowing

through the resistor does not exceed the rated VREF current (1 mA) .

20

MB39C001

• Output voltage setting table 2

VSET1

VSET2

VSET3

VSEL

VRSEL

V^OUT(Outputvoltagesettingvalue×Kv)

1.1 V × Kv

L

X

L

H

0.8 V × Kv

H

L

H

X

L

1.2 V × Kv

L

H

L

1.3 V × Kv

H

L

1.1 V × Kv

H

L

H

L

H

1.5 V × Kv

L

H

1.1 V × Kv

L

H

X

1.8 V × Kv

H

L

2.5 V × Kv

L

H

2.8 V × Kv

H

3.3 V × Kv

X : Don’t care

(3) About conversion efficiency

The conversion efficiency can be improved by reducing the loss of the DC/DC converter circuit.

The total loss (P^LOSS) of the DC/DC converter is roughly divided as follows :

P^LOSS= PCONT + PSW + PC

PCONT : Control system circuit loss (The power used for this IC to operate, including the the gate driving power

for internal SW FETs)

P^SW: Switching loss (The loss caused during switching of the IC's internal SW FETs)

PC

: Continuity loss (The loss caused when currents flow through the IC's internal SW FETs and external

circuits )

The IC's control circuit loss (P^CONT) is extremely small, which is about 1 mW (IIN = 300 µA) * , at VIN = 3.7 V.

As the IC contains FETs which can switch faster with smaller power, the continuity loss (PC) is more predominant

as the loss during heavy-load operation than the control circuit loss (PCONT) and switching loss (PSW) .

Further the continuity loss (PC) is divided roughly, into the loss by internal SW FET ON-resistance and by external

inductor series resistance.

2

PC = IOUT • (RDC + D • RONp + (1 − D) • RONn)

D

: Switching on-duty cycle ( = V^OUT/ VIN)

RONp : Internal Pch SW FET ON resistance

RONn : Internal Nch SW FET ON resistance

RDC : External inductor series resistance

I^OUT= Load current

21

MB39C001

The above formula indicates that it is important to reduce RDC as much as possible to improve efficiency by

selecting components.

* : The loss is caused during continuous operation. When the load is light, the IC performs burst operation, thereby

further suppressing the loss (I^IN= about 30 µA with no load). The mode is changed depending on the peak

current value Ipk flowing into SW FETs, at a threshold value of about 150 mA.

(4) Power dissipation and temperature examination

The IC is so efficient that no examination is required in most cases. But if the IC is used at a low power supply

voltage, heavy load, high output voltage, or high temperature, it requires further examination for higher efficiency.

The internal loss (P) is roughly obtained from the following formula :

2

P = I^OUT• (D • RONp + (1 − D) • RONn)

D

: Switching on-duty cycle ( = V^OUT/ VIN)

RONp : Internal Pch SW FET ON resistance

RONn : Internal Nch SW FET ON resistance

I^OUT= Load current

The loss expressed by the above formula is mainly continuity loss. The internal loss includes the switching loss

and the control circuit loss as well but they are so small compared to the continuity loss they can be ignored.

In this IC with RONp greater than RONn, the larger the on-duty cycle, the greater the loss.

When assuming V^IN= 3.7 V, Ta = 70 °C, VOUT = 1.8 V, and IOUT = 0.6 A, for example, RONp = 0.48 Ω and

RONn = 0.39 Ω according to the graph “SW FET ON resistance vs. Ambient temperature”. The IC's internal

loss P is 156 mW. According to the graph “Power dissipation vs. ambient temperature”, the power dissipation

at an ambient temperature Ta of 70 °C is 300 mW and the internal loss is smaller than the power dissipation.

(5) Transient response

The IC contains an optimized version of ErrAmp, providing favorable transient response characteristics.

The response characteristics such as response time, overshoot, and undershoot, are checked usually by chang-

ing suddenly I^OUT, with VIN and VOUT left constant.

(6) Example of designing board layout

For stable operation, the IC requires the optimized design of board layout.

Pay attention to the following points during layout design.

• Connect the GND terminals (AGND, DGND1, DGND2) and power terminals (AVDD, DVDD1, DVDD2) imme-

diately near the IC.

• Place the DVDD input condenser (C2) near DVDD and DGND. If the power supply or ground plains exists on

any other board layer, place TH (through hole) close to the condenser terminal.

• Place the AVDD input condenser (C5) near AVDD and AGND. If the power supply or ground plains exists on

any other board layer, place TH (through hole) close to the condenser terminal.

22

MB39C001

• Place the GND side terminal of the output condenser (C1) as near DGND of the IC and the GND side terminal

of the input condenser (C2). If the ground plains exists on any other board layer, place TH close to the GND

side terminal of the condenser. For wiring to OUT, start close to the V^OUTside terminal of the output condenser

(CI). Note that the OUT terminal is highly sensitive and should be wired as apart from the wiring of the LX

terminal of the IC.

• Large currents flow among the input condenser (C2, C5), output condenser (C1), external inductor (L1), and

this IC. Place these components near the IC, to minimize the loop area made up of these components. Also,

mount these components on the same layer and wire them without using any TH. Wire these nets using as

bold, short, and straight patterns (plains layout is advisable).

• For the IC mounted layer, provide a ground plane.

Recommended layout drawing (with only important wiring)

TH

VIN

C2

C5

MB39C001

GND

C1

L1

VOUT

23

MB39C001

■ NOTES ON CIRCUIT DESIGN

(1) GND Potential

Connect AGND and DGND to GND of the power supply circuit, so that they have equal potential.

(2) Control input terminals

• The voltages applied to the CNT, VSET1 to VSET3, VSEL, and VRSEL terminals must not exceed the absolute

maximum rating (VDD + 0.3 V). Applying a voltage exceeding the absolute maximum rating may cause

permanent damage to the LSI. If it is inevitable, insert a resistor of about 20 kΩ between a terminal of the

controller (such as a CPU) and the control terminal of the IC. This prevents a latch-up to some extent.

Note : Finally, judge right or wrong of the adoption after confirming it is unquestionable under your system require-

ments as permanent measure.

• The CNT terminal has no internal pull-down resistor function (while the VSET1 to VSET3, VSEL, and VRSEL

have one). If the terminal of the controller (such as the CPU) connected to the CNT terminal can enter a high

impedance state an unpredictable malfunction may occur. To prevent this, a pull-down resistor (of about

1 MΩ) should be connected to the CNT terminal.

• If the fall time of the CNT terminal is long, the output (V^OUT) may cause an overshoot when the load is light.

Be careful not to let the rise time and fall time exceed 500 µs.

(3) Power supply input

• If the rise time or fall time of the supply voltage (V^IN) is long, a malfunction may occurs. Be careful not to let

the rise time and fall time exceed 100 ms.

• If the power supply voltage fluctuates around the UVLO detection voltage (between 2.15 and 2.3 V) when the

power supply is turned on or shut off. The output is stopped by under-voltage and restarted by restored voltage

repeatedly and there is a possibility that chattering is generated in V^OUT. Although the UVLO detection voltage

has a hysteresis of 0.15 V, fluctuation over 0.15 V cannot be suppressed. Be careful to prevent the supply

voltage from going up and down near UVLO.

• If the CNT terminal becomes "L" from "H" when the supply voltage (V^IN) becomes lower than the output voltage

(V^OUT), the IC may cause a latch-up by the action of an external inductor. Although this is an operating condition

unintended for normal use, it can occur frequently when the power supply voltage is shut off with light loads.

Even if a latch-up occurs by normal shutdown, the latch-up is cleared when the power supply voltage goes

below 0.8 V. Therefore, there are few things which become problem, when the power supply is turned back

on again. If the power supply is turned back on with the power supply voltage exceeding 0.8 V, the IC may

be broken by an excessive current due to a latch-up. This problem can be worked around by either of the

following two methods :

• When the CNT terminal becomes "L" from "H" as the power supply voltage goes down, be sure to lower

the power supply voltage to 0.8 V or less before turning the power supply back on again.

• Add a Schottky barrier diode as shown in the latch-up preventive circuit example.

Note, however, that this work around adversely affects the regulation or conversion efficiency when the

application uses an extremely small load current. When selecting the Schottky barrier diode, pay attention

to the following points :

Reverse current [I^R]

Select a diode whose reverse current is smaller than the load current. (If a diode whose reverse current

is greater than the load current is adopted, the output voltage (VOUT) is raised by the reverse current,

and the regulation deteriorates.

24

MB39C001

Forward voltage [V^F]

The forward voltage must be smaller than the voltage triggering latch-up. Select a diode whose forward

voltage is about 0.5 V or less.

Non repetitive peak surge current [I^FSM]

Select a diode whose non repetitive peak surge current is greater than the peak reverse current. The

peak current is different depending on the operating conditions; the reference value is 1 A to 3 A.

Latch-up preventive circuit example

Schottky barrier diode

for latch-up prevention

VIN

10

14

15

AVDD DVDD1 DVDD2

1

2

LX1

LX2

VOUT

4

OUT

AGND DGND1 DGND2

17 18

8

(4) VREFIN terminal

When the VREFIN terminal is used, the switching frequency is lowered if the VREFIN voltage is 0.5 V or less.

When the load current (I^OUT) is 100 mA or less, the VREFIN voltage should fall within the range of 0.5 to 0.7 V.

The VREFIN voltage can be between 0.3 and 0.7 V if the switching frequency lowered is acceptable when the

load current (IOUT) is 100 mA or less.

(5) POWER GOOD terminal

The POWER GOOD terminal always monitors the OUT terminal voltage, with no exception, even when the

output voltage is changed by switching the terminals such as VSET1 to VSET3 and VSEL. When the output

voltage rises slowly with heavy loads, the POWER GOOD terminal become "H" until the output voltage becomes

90% of the setting voltage.

Be careful when using the POWER GOOD terminal to reset a load circuit which uses a CPU. Be careful that

the POWER GOOD terminal temporarily becomes “H” level when dynamically changing the voltage, thereby

resetting the circuit accidentally at an unintended timing.

(6) Output overcurrent protection

This IC uses current mode control which provides a certain level of overcurrent protection. If LX is connected

to VDD or GND, or V^OUTis connected to GND with an extremely low resistor of 0.1 Ω or less, the IC may not be

protected from overcurrents and it is break down.

The IC is apt to break down, when the inductance element of the short-circuit route is large or when the output

voltage is high. To prevent the IC from breaking due to a short-circuit, it is advisable to insert a resistor of about

1 kΩ between the OUT terminal and V^OUT.

25

MB39C001

■ APPLICATION EXAMPLES

(1) Output setting of 1.8 V by reference voltage use of internal

C5

0.01 µF

C2

4.7 µF

VIN

10

14

DVDD1

15

DVDD2

AVDD

VOUT

LX1

13

12

11

16

1

2

VSET1

VSET2

VSET3

VSEL

L1

3.3 µH

C1

10 µF

LX2

OUT

4

6

R2

R6

1 MΩ

20 kΩ

CPU

9

CNT

APLI

POWER GOOD

R1

1 MΩ

3

5

7

VRSEL

VREF

VREFIN

AGND DGND1 DGND2

17 18

8

(2) Supplying the VREF terminal voltage to the reference voltage external input (VREFIN) after resistor

voltage division, the V^OUTvoltage is set to 1.25 V by the OUT setting gain twice

C5

0.01 µF

C2

4.7 µF

VIN

10

14

DVDD1

15

DVDD2

AVDD

VOUT

LX1

13

12

11

16

1

2

VSET1

VSET2

VSET3

VSEL

L1

3.3 µH

C1

10 µF

LX2

OUT

4

6

R2

20 kΩ

CPU

9

CNT

APLI

POWER GOOD

R1

1 MΩ

3

5

7

VRSEL

VREF

R7

100 kΩ

VREFIN

R8

VREFIN

0.6

100 kΩ

AGND DGND1 DGND2

17 18

VOUT = (Output voltage setting value ) ×

8

1.2

0.6

R8

=

• VREFIN = 2 ×

VREF

R7 + R8

100 k

= 2 ×

× 1.25 = 1.25 V

100 k + 100 k

26

MB39C001

(3) Supplying an external voltage to the reference voltage external input (VREFIN), the V^OUTvoltage is set

by the V^OUTsetting gain triple

C5

0.01 µF

C2

4.7 µF

VIN

10

14

DVDD1 DVDD2

LX1

15

AVDD

VOUT

13

12

11

16

1

2

VSET1

VSET2

VSET3

VSEL

L1

3.3 µH

C1

10 µF

LX2

OUT

4

6

R2

20 kΩ

CPU

DAC

9

CNT

APLI

POWER GOOD

R1

1 MΩ

3

5

7

VRSEL

VREF

VREFIN

AGND DGND1 DGND2

17 18

VREFIN

0.6

8

VOUT = (Output voltage setting value ) ×

1.8

=

• VREFIN = 3 × VREFIN

0.6

The components for the above example are listed below.

Manufacturer

TDK

Component

Part name

Inductor

Specification

Model name

VLF4012AT-3R3M

C2012JB0J106M

C2012JB1A475K

C1608JB1H103K

PFR05Q-105-D-1

RR0816P-203-D

PFR05Q-105-D-1

RR0816P-104-D

L1

C1

C2

C5

R1

R2

R6

R7

R8

3.3 µH

10 µF

4.7 µF

20% R^DC= 120 mΩ

20% 6.3 V

Ceramic condenser

Resistor

TDK

10% 10 V

TDK

0.0 1 µF 10% 50 V

TDK

1 MΩ

20 kΩ

1 MΩ

0.5%

ssm

Resistor

ssm

Resistor

ssm

Resistor

100 kΩ

ssm

Resistor

ssm

TDK

ssm

: TDK Corporation

: SUSUMU CO., LTD.

27

MB39C001

■ NOTES ON USE

1. Do not exceed maximum ratings.

Using the LSI beyond maximum ratings may generate a parasitic transistor, resulting in permanent damage to

the LSI due to a latch-up. The LSI should be used under the recommended operating conditions and exceeding

any of the recommended conditions may adversely affect LSI reliability.

2. Use under recommended operating conditions.

The recommended operating conditions are reommended values that guarantee the normal operation of the LSI.

The values of electrical characteristics are guaranteed when the LSI is used under the recommended operating

conditions with each parameter falling in the specified range.

3. Take measures against static electricity.

• Containers for semiconductors must be antistatic or conductive.

• When storing or carrying a printed circuit board with components mounted, put it in a conductive bag or

container.

• The work table, tools, and measuring instruments must be properly grounded.

• The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series.

4. Do not apply a negative voltage.

Applying a negative voltage of − 0.3 V or less to an LSI may generate a parasitic transistor, resulting malfunction.

■ ORDERING INFORMATION

Model

MB39C001PVB

Package

Remarks

18-pin plastic BCC

(LCC-18P-M05)

28

MB39C001

■ PACKAGE DIMENSIONS

18-pin plastic BCC

(LCC-18P-M05)

2.31(.090)

TYP

2.70±0.10

(.106±.004)

0.45±0.05

(.018±.002)

0.45(.018)

TYP.

10

15

10

(Mount height)

2.01(.079)

TYP

INDEX AREA

2.40±0.10

(.094±.004)

0.90(.035)

REF

1.90(.075)

REF

"A"

0.45(.018)

TYP.

"C"

"B"

0.075±0.025

(.003±.001)

(Stand off)

1

6

1.35(.053)

REF

6

1

2.28(.090)

REF

Details of "A" part

Details of "B" part

C0.10(.004)

Details of "C" part

0.36±0.06

0.05(.002)

0.36±0.06

(.014±.002)

0.25±0.06

(.010±.002)

0.14(.006)

MIN.

(.014±.002)

0.25±0.06

0.28±0.06

(.010±.002)

(.011±.002)

C

2003 FUJITSU LIMITED C18058S-c-1-1

Unit : mm (inches)

Note : Parenthesized values are reference values.

29

MB39C001

■ EVALUATION BOARD SPECIFICATIONS

The MB39C001 evaluation board is a surface-mounting board of a single-channel down-conversion circuit. The

output voltage can be set by switch of each SW (^*1), and supplies the current of up to 600 mA at a power supply

voltage from 2.5 V to 5.5 V (^*2).

*1 : For setting the output voltage, refer (2) "Setting output voltages" in ■ APPLICATION NOTES.

*2 : The current can be supplied when “V^IN- VOUT ≥ 0.7 V”. It can be supplied even “VIN - VOUT < 0.7 V” when under

operating conditions in which the output current is suppressed.

• Terminal Description

Symbol

Function

Power supply terminal.

VIN = 2.5 V to 5.5 V (3.7 V Typ)

VIN

OUT

DC/DC converter output terminal.

Power supply terminal for mode setting SW.

Connect with VIN and use it.

VCTL

Power control terminal.

CNT

VCNT = 0 V to 0.3 V : Shutdown

VCNT = 1.5 V to VIN : Normal operation

POWER_GOOD

VREF

Fixed at “L” ( = 0 V) , when the OUT voltage reaches the output setting voltage.

Reference voltage output terminal.

External reference voltage input terminal.

When an external reference voltage is used, this terminal supplies it.

VREFIN

GND

DC/DC converter ground terminal.

MB39C001 ground terminal.

AGND

• Switch Description

SW

1

Name

FUNCTION

Remarks

VSEL

VSET1

VSET2

VSET3

VRSEL

Output voltage setting

Reference voltage setting

2

For details on each setting, refer (2) "Setting output

voltages" in ■ APPLICATION NOTES.

3

4

5

• Setup and checkup

(1) Setup

Connect the power supply terminal of the power supply to VIN, VCTL, and CNT and its ground terminal to GND.

Connect the OUT side to the required loading device or measuring instrument.

Set SW1 (VSEL) and SW4 (VSET3) to ON; SW2 (VSET1), SW3 (VSET2), and SW5 (VRSEL) to OFF. (Set the

output to 1.8 V using the internal reference voltage.)

(2) Checkup

Supply power to VIN. The IC is working normally when the OUT voltage is 1.8 V (Typ) .

30

MB39C001

• On-board Component Layout

Top side (Top View)

1

2

3

4

5

6

AGND

SW1

VCTL

CNT

VIN

GND

OUT

VREFIN

C5

M1

C2

R8

R7

POWER_GOOD

VREF

R6

C1

C3

L1

Bottom side (Top View)

31

MB39C001

Board Layout

Top Side (Layer1)

In Side VIN & GND (Layer2)

Inside GND (Layer3)

Bottom Side (Layer4)

32

MB39C001

• Connection Diagram

IIN

VIN

C5

0.01 µF

C2

4.7 µF

C4

IOUT

10

14

15

SW2

13

VCTL

CNT

1

2

OUT

L1

3.3 µH

SW3

SW4

SW1

12

11

16

C1

10 µF

4

6

R6

1 MΩ

9

3

POWER GOOD

SW5

MB39C001

R7

100 kΩ

VREF

5

7

AGND

GND

VREFIN

R8

100 kΩ

8

17

18

C3

0.1 µF

• Parts List

Manufacturer Remarks

Symbol

Part name

Inductor

Model name

Specification

Package

3.3 µH,

RDC = 120 mΩ

L1

VLF4012AT-3R3M

SMD

TDK

C1

C2

C3

C4

C5

R6

R7

R8

SW

Ceramic capacitor

C2012JB0J106M 10 µF (6.3 V)

C2012JB1A475K 4.7 µF (10 V)

C1608JB1H104K 0.1 µF (50 V)

2012

1608

TDK

Not mounted

TDK

Ceramic capacitor

Resistor

C1608JB1H103K 0.01 µF (50 V)

PFR05Q-105-D-1 1 MΩ ± 0.5%

1608

1005

1608

ssm

Resistor

RR0816P-104-D

DMS-6H

100 kΩ ± 0.5%

6 poles

ssm

Resistor

ssm

Switch

MATSUKYU

MacEight

Terminal pins

WT-2-1

TDK

ssm

: TDK Corporation

: SUSUMU CO., LTD.

MATSUKYU : Matsukyu Co., Ltd.

MacEight : MacEight Co., Ltd.

• Ordering Information

EV board part No.

MB39C001EVB-01

EV board version No.

MB39C001EV Board Rev.2.0

Remarks

33

MB39C001

FUJITSU LIMITED

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

The information, such as descriptions of function and application

circuit examples, in this document are presented solely for the

purpose of reference to show examples of operations and uses of

Fujitsu semiconductor device; Fujitsu does not warrant proper

operation of the device with respect to use based on such

information. When you develop equipment incorporating the

device based on such information, you must assume any

responsibility arising out of such use of the information. Fujitsu

assumes no liability for any damages whatsoever arising out of

the use of the information.

Any information in this document, including descriptions of

function and schematic diagrams, shall not be construed as license

of the use or exercise of any intellectual property right, such as

patent right or copyright, or any other right of Fujitsu or any third

party or does Fujitsu warrant non-infringement of any third-party’s

intellectual property right or other right by using such information.

Fujitsu assumes no liability for any infringement of the intellectual

property rights or other rights of third parties which would result

from the use of information contained herein.

The products described in this document are designed, developed

and manufactured as contemplated for general use, including

without limitation, ordinary industrial use, general office use,

personal use, and household use, but are not designed, developed

and manufactured as contemplated (1) for use accompanying fatal

risks or dangers that, unless extremely high safety is secured, could

have a serious effect to the public, and could lead directly to death,

personal injury, severe physical damage or other loss (i.e., nuclear

reaction control in nuclear facility, aircraft flight control, air traffic

control, mass transport control, medical life support system, missile

launch control in weapon system), or (2) for use requiring

extremely high reliability (i.e., submersible repeater and artificial

satellite).

Please note that Fujitsu will not be liable against you and/or any

third party for any claims or damages arising in connection with

above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You

must protect against injury, damage or loss from such failures by

incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Law of Japan, the prior

authorization by Japanese government will be required for export

of those products from Japan.

F0405

FUJITSU LIMITED Printed in Japan


型号：	MB39C001PVB
厂家：	FUJITSU
描述：	Switching Regulator, Current-mode, 1.3A, 1200kHz Switching Freq-Max, BICMOS, PBCC18, PLASTIC, LCC-18 信息通信管理开关
文件：	总34页 (文件大小：378K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB39C001PVB [FUJITSU]

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