GPR25L12805F [GENERALPLUS]
128M-bit [x 1/x 2/x 4] CMOS Serial Flash;
| 型号： | GPR25L12805F |
| 厂家： | 
Generalplus Technology Inc. |
| 描述： | 128M-bit [x 1/x 2/x 4] CMOS Serial Flash |
| 文件： | 总58页 (文件大小：3458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128M-bit [x 1/x 2/x 4] CMOS Serial
Flash
Nov. 23, 2017
Version 1.1
GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS
TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may
appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No
responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.
In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a
malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.
GPR25L12805F
Table of Contents
PAGE
1. FEATURES.............................................................................................................................................................................................4
1.1. GENERAL..........................................................................................................................................................................................4
1.2. SOFTWARE FEATURES.......................................................................................................................................................................4
1.3. HARDWARE FEATURES ......................................................................................................................................................................4
2. GENERAL DESCRIPTION......................................................................................................................................................................4
3. PIN CONFIGURATIONS .........................................................................................................................................................................5
3.1. 8-PIN SOP (200MIL).........................................................................................................................................................................5
4. PIN DESCRIPTION.................................................................................................................................................................................5
5. BLOCK DIAGRAM..................................................................................................................................................................................6
6. DATA PROTECTION ..............................................................................................................................................................................7
7. MEMORY ORGANIZATION.....................................................................................................................................................................9
8. DEVICE OPERATION ...........................................................................................................................................................................10
8.1. QUAD PERIPHERAL INTERFACE (QPI) READ MODE............................................................................................................................. 11
9. COMMAND DESCRIPTION ..................................................................................................................................................................12
9.1. COMMAND SET(TABLE 5) .................................................................................................................................................................12
9.1.1. Read/Write Array Commands..............................................................................................................................................12
9.1.2. Register/Setting Commands ...............................................................................................................................................13
9.1.1. ID/Security Commands .......................................................................................................................................................14
9.1.2. Reset Commands ...............................................................................................................................................................15
9.2. WRITE ENABLE (WREN)..................................................................................................................................................................16
9.3. WRITE DISABLE (WRDI) ..................................................................................................................................................................16
9.4. READ IDENTIFICATION (RDID) ..........................................................................................................................................................16
9.5. RELEASE FROM DEEP POWER-DOWN (RDP), READ ELECTRONIC SIGNATURE (RES)............................................................................16
9.6. READ ELECTRONIC MANUFACTURER ID & DEVICE ID (REMS)............................................................................................................17
9.7. QPI ID READ (QPIID)......................................................................................................................................................................18
9.8. READ STATUS REGISTER (RDSR) ....................................................................................................................................................18
9.9. READ CONFIGURATION REGISTER (RDCR) .......................................................................................................................................18
9.10.WRITE STATUS REGISTER (WRSR) ..................................................................................................................................................23
9.11.READ DATA BYTES (READ)..............................................................................................................................................................25
9.12.READ DATA BYTES AT HIGHER SPEED (FAST_READ)........................................................................................................................25
9.13.DUAL OUTPUT READ MODE (DREAD) ..............................................................................................................................................25
9.14.2 X I/O READ MODE (2READ)..........................................................................................................................................................25
9.15.QUAD READ MODE (QREAD) ..........................................................................................................................................................26
9.16.4 X I/O READ MODE (4READ)..........................................................................................................................................................26
9.17.BURST READ...................................................................................................................................................................................27
9.18.PERFORMANCE ENHANCE MODE ......................................................................................................................................................27
9.19.PERFORMANCE ENHANCE MODE RESET ...........................................................................................................................................28
9.20.FAST BOOT .....................................................................................................................................................................................28
9.21.SECTOR ERASE (SE).......................................................................................................................................................................30
9.22.BLOCK ERASE (BE32K)...................................................................................................................................................................30
9.23.BLOCK ERASE (BE).........................................................................................................................................................................30
9.24.CHIP ERASE (CE)............................................................................................................................................................................31
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9.25.PAGE PROGRAM (PP)......................................................................................................................................................................31
9.26.4 X I/O PAGE PROGRAM (4PP).........................................................................................................................................................32
9.27.DEEP POWER-DOWN (DP) ...............................................................................................................................................................32
9.28.ENTER SECURED OTP (ENSO)........................................................................................................................................................32
9.29.EXIT SECURED OTP (EXSO) ...........................................................................................................................................................33
9.30.READ SECURITY REGISTER (RDSCUR)............................................................................................................................................33
9.31.WRITE SECURITY REGISTER (WRSCUR)..........................................................................................................................................33
9.32.WRITE PROTECTION SELECTION (WPSEL) .......................................................................................................................................34
9.33.ADVANCED SECTOR PROTECTION.....................................................................................................................................................36
9.34.LOCK REGISTER..............................................................................................................................................................................36
9.35.SPB LOCK BIT (SPBLB)..................................................................................................................................................................37
9.36.SOLID PROTECTION BITS .................................................................................................................................................................37
9.37.DYNAMIC WRITE PROTECTION BITS ..................................................................................................................................................38
9.38.GANG BLOCK LOCK/UNLOCK (GBLK/GBULK) ..................................................................................................................................39
9.39.PASSWORD PROTECTION MODE .......................................................................................................................................................39
9.40.PROGRAM/ERASE SUSPEND/RESUME...............................................................................................................................................40
9.41.ERASE SUSPEND.............................................................................................................................................................................40
9.42.WRITE-RESUME ..............................................................................................................................................................................40
9.43.NO OPERATION (NOP) ....................................................................................................................................................................41
9.44.SOFTWARE RESET (RESET-ENABLE (RSTEN) AND RESET (RST)) ......................................................................................................41
9.45.READ SFDP MODE (RDSFDP)........................................................................................................................................................41
10.RESET..................................................................................................................................................................................................46
11. POWER-ON STATE ..............................................................................................................................................................................47
12.ELECTRICAL SPECIFICATIONS..........................................................................................................................................................48
12.1.ABSOLUTE MAXIMUM RATINGS .........................................................................................................................................................48
12.2.CAPACITANCE..................................................................................................................................................................................48
12.3.TABLE 16. DC CHARACTERISTICS ...............................................................................................................................................50
12.4.TABLE 17. AC CHARACTERISTICS................................................................................................................................................51
13.OPERATING CONDITIONS ..................................................................................................................................................................52
13.1.INITIAL DELIVERY STATE...................................................................................................................................................................53
14.ERASE AND PROGRAMMING PERFORMANCE.................................................................................................................................54
15.DATA RETENTION...............................................................................................................................................................................54
16.LATCH-UP CHARACTERISTICS .........................................................................................................................................................54
17.ORDERING INFORMATION .................................................................................................................................................................55
18.PACKAGE INFORMATION...................................................................................................................................................................56
18.1.TITLE: PACKAGE OUTLINE FOR SOP 8L 200MIL (OFFICIAL NAME-209 MIL) ..........................................................................................56
18.1.1. Dimensions (Inch dimensions are derived from the original mm dimensions)..................................................................56
19.DISCLAIMER........................................................................................................................................................................................57
20.REVISION HISTORY.............................................................................................................................................................................58
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GPR25L12805F
128M-BIT [x 1/x 2/x 4] CMOS SERIAL FLASH
1. FEATURES
1.1. General
- RES command for 1-byte Device ID
- REMS command for 1-byte manufacturer ID and 1-byte
device ID
Serial Peripheral Interface compatible -- Mode 0 and Mode 3
Single Power Supply Operation
Support Serial Flash Discoverable Parameters (SFDP) mode
- 2.7 to 3.6 volt for read, erase, and program operations
128Mb: 134,217,728 x 1 bit structure or 67,108,864 x 2 bits (two
I/O mode) structure or 33,554,432 x 4 bits (four I/O mode)
structure
1.3. Hardware Features
SCLK Input
Protocol Support
- Serial clock input
- Single I/O, Dual I/O and Quad I/O
SI/SIO0
Latch-up protected to 100mA from -1V to Vcc +1V
Low Vcc write inhibit is from 2.3V to 2.5V
Fast read for SPI mode
- Serial Data Input or Serial Data Input/Output for 2 x I/O read
mode and 4 x I/O read mode
SO/SIO1
- Support clock frequency up to 133MHz for all protocols
- Support Fast Read, 2READ, DREAD, 4READ, QREAD
instructions.
- Serial Data Output or Serial Data Input/Output for 2 x I/O read
mode and 4 x I/O read mode
WP#/SIO2
- Configurable dummy cycle number for fast read operation
Quad Peripheral Interface (QPI) available
Equal Sectors with 4K byte each, or Equal Blocks with 32K byte
each or Equal Blocks with 64K byte each
- Any Block can be erased individually
Programming :
- Hardware write protection or serial data Input/Output for 4 x
I/O read mode
RESET#/SIO3
- Hardware Reset pin or Serial input & Output for 4 x I/O read
mode
PACKAGE
- 256byte page buffer
- 8-pin SOP (200mil)
- Quad Input/Output page program(4PP) to enhance program
performance
2. GENERAL DESCRIPTION
Typical 100,000 erase/program cycles
20 years data retention
GPR25L12805F is 128Mb bits serial Flash memory, which is
configured as 16,777,216 x 8 internally. When it is in two or four
GPR25L12805F is compatible with MX25L12835F
I/O mode, the structure becomes 67,108,864 bits
x 2 or
33,554,432 bits x 4. GPR25L12805F feature a serial peripheral
interface and software protocol allowing operation on a simple
3-wire bus while it is in single I/O mode. The three bus signals
are a clock input (SCLK), a serial data input (SI), and a serial data
output (SO). Serial access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become
SIO0 pin and SIO1 pin for address/dummy bits input and data
output. When it is in four I/O read mode, the SI pin, SO pin, WP#
and RESET# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3
pin for address/dummy bits input and data output.
1.2. Software Features
Input Data Format
- 1-byte Command code
Advanced Security Features
- Block lock protection
The BP0-BP3 and T/B status bit defines the size of the area to
be protection against program and erase instructions
- Advanced sector protection function (Solid and Password
Protect)
Additional 4K bit security OTP
The GPR25L12805F provides sequential read operation on whole
chip.
- Features unique identifier
- factory locked identifiable, and customer lockable
Command Reset
After program/erase command is issued, auto program/erase
algorithms which program/erase and verify the specified page or
sector/block locations will be executed. Program command is
executed on byte basis, or page (256 bytes) basis, or word basis
for erase command is executed on sector (4K-byte), block
Program/Erase Suspend and Resume operation
Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
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(32K-byte), or block (64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included
to indicate the status of the chip. The status read command can
be issued to detect completion status of a program or erase
operation via WIP bit.
functions, please see security features section for more details.
When the device is not in operation and CS# is high, it is put in
standby mode.
The GPR25L12805F utilizes proprietary memory cell, which
reliably stores memory contents even after 100,000 program and
erase cycles.
Advanced security features enhance the protection and security
Table 1. Read Performance Comparison
Numbers
of Fast Read (MHz)
Dual Output Fast Quad Output Fast Dual IO Fast Read
Quad
IO
Fast
Dummy Cycles
Read (MHz)
Read (MHz)
(MHz)
Read (MHz)
4
6
-
-
-
84*
104
104
133
70
104
104*
133
104
104*
133
84
84*
104
133
8
104*
133
10
Note: *means default status
3. PIN CONFIGURATIONS
3.1. 8-PIN SOP (200mil)
4. PIN DESCRIPTION
Symbol
CS#
Description
Chip Select
SI/SIO0
Serial Data Input (for 1 x I/O)/ Serial Data
Input & Output (for 2xI/O or 4xI/O read mode)
Serial Data Output (for 1 x I/O)/ Serial Data
Input & Output (for 2xI/O or 4xI/O read mode)
Clock Input
SO/SIO1
SCLK
WP#/SIO2
Write protection: connect to GND or Serial
Data Input & Output (for 4xI/O read mode)
RESET#/SIO3 Hardware Reset Pin Active low or Serial Data
Input & Output (for 4xI/O read mode)
VCC
GND
NC
+ 3V Power Supply
Ground
No Connection
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GPR25L12805F
5. BLOCK DIAGRAM
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6. DATA PROTECTION
The device is designed to offer protection against accidental
erasure or programming caused by spurious system level signals
that may exist during power transition. During power up the
device automatically resets the state machine in the Read mode.
In addition, with its control register architecture, alteration of the
memory contents only occurs after successful completion of
specific command sequences. The device also incorporates
several features to prevent inadvertent write cycles resulting from
VCC power-up and power-down transition or system noise.
Valid command length checking: The command length will be
checked whether it is at byte base and completed on byte
boundary.
Advanced Security Features: there are some protection and
security features which protect content from inadvertent write
and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1,
BP0 and T/B) bits to allow part of memory to be protected as
read only. The protected area definition is shown as "Table
2. Protected Area Sizes", the protected areas are more
flexible which may protect various area by setting value of
BP0-BP3 bits.
- The Hardware Protected Mode (HPM) use WP#/SIO2 to
protect the (BP3, BP2, BP1, BP0) bits and Status Register
Write Protect bit.
Write Enable (WREN) command: WREN command is required
to set the Write Enable Latch bit (WEL) before other command
to change data. The WEL bit will return to reset stage under
following situation:
- In four I/O and QPI mode, the feature of HPM will be disabled.
- Power-up
Table2. Protected Area Sizes
- Reset# pin driven low
Protected Area Sizes (TB bit = 0)
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase 32KB (BE32K) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
Status bit
Protect Level
128Mb
BP3 BP2 BP1 BP0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 (none)
1 (1 block, protected block 255th)
2 (2 blocks, block 254th-255th)
3 (4 blocks, block 252nd-255th)
4 (8 blocks, block 248th-255th)
5 (16 blocks, block 240th-255th)
6 (32 blocks, block 224th-255th)
7 (64 blocks, block 192nd-255th)
8 (128 blocks, block 128th-255th)
9 (256 blocks, protected all)
- Program/Erase Suspend
- Softreset command completion
- Write Security Register (WRSCUR) command completion
- Write Protection Selection (WPSEL) command completion
- GBLK command completion
- GBULK command completion
10 (256 blocks, protected all)
11 (256 blocks, protected all)
12 (256 blocks, protected all)
13 (256 blocks, protected all)
14 (256 blocks, protected all)
15 (256 blocks, protected all)
- WEAR command completion
- ASP program
- PASSWD program
- PASSWD check mode
- Write SPB lock bit
- Write SPB bit
- Erase SPB bit
- DPB write
Protected Area Sizes (TB bit = 1)
Status bit
- Fastboot write
Protect Level
128Mb
- Fastboot erase mode.
BP3 BP2 BP1 BP0
Deep Power Down Mode: By entering deep power down mode,
the flash device also is under protected from writing all
commands except Release from deep power down mode
command (RDP) and Read Electronic Signature command
(RES), Erase/Program suspend command, Erase/Program
resume command and softreset command.
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0 (none)
1 (1 block, protected block 0th)
2 (2 blocks, protected block 0th~1th)
3 (4 blocks, protected block 0th~3rd)
4 (8 blocks, protected block 0th~7th)
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II. Additional 4K-bit secured OTP for unique identifier: to
provide 4K-bit one-time program area for setting device unique
serial number - Which may be set by factory or system customer.
- Security register bit 0 indicates whether the chip is locked by
factory or not.
Status bit
Protect Level
128Mb
BP3 BP2 BP1 BP0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
5
(16 blocks, protected block
0th~15th)
6
(32 blocks, protected block
- To program the 4K-bit secured OTP by entering 4K-bit
secured OTP mode (with Enter Security OTP command), and
going through normal program procedure, and then exiting
4K-bit secured OTP mode by writing Exit Security OTP
command.
0th~31st)
7
(64 blocks, protected block
0th~63rd)
8
(128 blocks, protected block
0th~127th)
- Customer may lock-down the customer lockable secured OTP
by writing WRSCUR(write security register) command to set
customer lock-down bit1 as "1". Please refer to "Table 9.
Security Register Definition" for security register bit definition
and "Table 3. 4K-bit Secured OTP Definition" for address
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
9 (256 blocks, protected all)
10 (256 blocks, protected all)
11 (256 blocks, protected all)
12 (256 blocks, protected all)
13 (256 blocks, protected all)
14 (256 blocks, protected all)
15 (256 blocks, protected all)
1
1
1
1
1
1
0
1
1
1
0
1
range definition.
Note: Once lock-down whatever by factory or customer, it cannot be
changed any more. While in 4K-bit secured OTP mode, array access is
not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
Size
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
xxx000~xxx00F
128-bit
3968-bit
Determined by customer
xxx010~xxx1FF
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7. MEMORY ORGANIZATION
Table 4. Memory Organization
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8. DEVICE OPERATION
1. Before a command is issued, status register should be checked
to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this device, this device
becomes standby mode and keeps the standby mode until next
CS# falling edge. In standby mode, SO pin of this device
should be High-Z.
FAST_READ, 2READ, DREAD, 4READ, QREAD, RDSFDP,
RES, REMS, QPIID, RDDPB, RDSPB, RDPASS, RDLR,
RDEAR, RDFBR, RDSPBLK, RDCR the shifted-in instruction
sequence is followed by a data-out sequence. After any bit of
data being shifted out, the CS# can be high. For the following
instructions: WREN, WRDI, WRSR, SE, BE32K, BE, CE, PP,
4PP, DP, ENSO, EXSO, WRSCUR, WPSEL, GBLK, GBULK,
SPBLK, SUSPEND, RESUME, NOP, RSTEN, RST, EQIO,
RSTQIO the CS# must go high exactly at the byte boundary;
otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase
operation, to access the memory array is neglected and not
affect the current operation of Write Status Register, Program,
Erase.
3. When correct command is inputted to this device, this device
becomes active mode and keeps the active mode until next CS#
rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK)
and data shifts out on the falling edge of SCLK. The difference
of Serial mode 0 and mode 3 is shown as "Serial Modes
Supported".
5. For the following instructions: RDID, RDSR, RDSCUR, READ,
Figure1. SPI Modes Supported
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase.
The combination of CPOL bit and CPHA bit decides which Serial mode is supported.
Figure 2. Serial Input Timing
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Figure 3. Output Timing
8.1. Quad Peripheral Interface (QPI) Read Mode
QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in command cycles, address
cycles and as well as data output cycles.
Enable QPI mode
By issuing 35H command, the QPI mode is enable.
Figure 4. Enable QPI Sequence
Reset QPI (RSTQIO)
The Reset QPI instruction, F5H, resets the device to SPI protocol operation. To execute a Reset QPI operation, the host drives CS# low,
sends the Reset QPI command cycle (F5h) then, drives CS# high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care when during SPI mode.
Note: For EQIO/RSTQIO/C0 PCSB high width has to follow "write spec" tSHSL for next instruction.
Figure 5. Reset QPI Mode
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9. COMMAND DESCRIPTION
9.1. Command Set(Table 5)
9.1.1. Read/Write Array Commands
Command (byte)
READ
FAST READ
2READ
DREAD
4READ
QREAD
(normal read)
(fast read data)
(2 x I/O read
command)
(1I 2O read)
(4 I/O read)
(1I 4O read)
Mode
SPI
3/4
SPI
3/4
SPI
3/4
SPI
3/4
SPI/QPI
3/4
SPI
3/4
Address Bytes
1st byte
03 (hex)
ADD1
ADD2
ADD3
0B (hex)
ADD1
ADD2
ADD3
Dummy*
BB (hex)
ADD1
ADD2
ADD3
Dummy*
3B (hex)
ADD1
ADD2
ADD3
Dummy*
EB (hex)
ADD1
6B (hex)
ADD1
ADD2
ADD3
Dummy*
2nd byte
3rd byte
4th byte
ADD2
ADD3
5th byte
Dummy*
Data Cycles
Action
n bytes read out n bytes read out n bytes read out n bytes read out n bytes read out n bytes read out
until CS# goes until CS# goes by I/O until by Dual output by I/O until by Quad output
2
x
4 x
high
high
CS# goes high
until CS# goes CS# goes high
high
until CS# goes
high
Command (byte) PP
4PP
SE
BE 32K
(block
32KB)
BE
erase (block
64KB)
CE
(page program) (quad
program)
page (sector erase)
erase (chip erase)
Mode
SPI/QPI
3/4
SPI
3/4
SPI/QPI
3/4
SPI/QPI
SPI/QPI
SPI/QPI
0
Address Bytes
1st byte
3/4
3/4
02 (hex)
38 (hex)
ADD1
ADD2
ADD3
20 (hex)
ADD1
ADD2
ADD3
52 (hex)
ADD1
ADD2
ADD3
D8 (hex)
ADD1
ADD2
ADD3
60 or C7 (hex)
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
1-256
1-256
input
to program the quad
to to
erase
the to
erase
the to
erase
the to erase whole
selected page
program
the selected sector
selected 32K block selected block chip
selected page
* Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in configuration register.
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9.1.2. Register/Setting Commands
Command
(byte)
WREN
(write enable) (write disable) (read
register)
WRDI
RDSR
RDCR
WRSR
status/
(write WPSEL
EQIO
status (read
(Write Protect (Enable QPI)
configuration configuration Selection)
register) register)
SPI/QPI SPI/QPI
15 (hex)
Mode
SPI/QPI
06 (hex)
SPI/QPI
04 (hex)
SPI/QPI
05 (hex)
SPI/QPI
68 (hex)
SPI
1st byte
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
01 (hex)
Values
Values
35 (hex)
1-2
sets the (WEL) resets
the to read out the to read out the to write new to enter and Entering
the
write
enable (WEL)
write values of the values of the values of the enable
QPI mode
latch bit
enable latch bit status register configuration
status/
individual block
protect mode
register
configuration
register
Command
(byte)
RSTQIO (Reset PGM/ERS
PGM/ERS
Resume
(Resumes
Program/
Erase)
DP
(Deep RDP (Release SBL
RDFBR
QPI)
Suspend
(Suspends
Program/
Erase)
power down)
from
deep (Set
Burst (read fast boot
register)
power down)
Length)
Mode
QPI
SPI/QPI
B0 (hex)
SPI/QPI
30 (hex)
SPI/QPI
B9 (hex)
SPI/QPI
AB (hex)
SPI/QPI
C0 (hex)
SPI
1st byte
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
F5 (hex)
16(hex)
1-4
Exiting the QPI
mode
enters
power
mode
deep release
down deep
down mode
from to set Burst
power length
Command
(byte)
WRFBR
ESFBR
(write fast boot (erase fast boot
register) register)
SPI SPI
17(hex) 18(hex)
Mode
1st byte
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
4
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9.1.1. ID/Security Commands
Command
(byte)
RDID
(read
RES
REMS
(read QPIID
RDSFDP
ENSO
(enter secured (exit secured
OTP) OTP)
EXSO
(read
electronic
(QPI ID Read)
identification) electronic ID) manufacturer
& device ID)
Mode
SPI
0
SPI/QPI
SPI
QPI
0
SPI/QPI
SPI/QPI
SPI/QPI
Address Bytes
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
0
0
3
0
0
9F (hex)
AB (hex)
90 (hex)
AF (hex)
5A (hex)
ADD1
B1 (hex)
C1 (hex)
x
x
x
x
x
ADD2
ADD1 (Note 1)
ADD3
Dummy (8)
outputs JEDEC to
read
out output
the ID
in
QPI Read
mode
SFDP to enter the to exit the 4K-bit
4K-bit secured secured OTP
OTP mode mode
ID:
1-byte 1-byte
Device Manufacturer ID interface
& Device ID
Manufacturer ID ID
& 2-byte Device
ID
Command
(byte)
RDSCUR
(read
WRSCUR
GBLK
GBULK
WRLR
RDLR
WRPASS
Lock (write
password
RDPASS
(read
(write
(gang block (gang block (write Lock (read
security
register)
security
register)
lock)
unlock)
register)
register)
password
register)
register)
Mode
SPI/QPI
0
SPI/QPI
SPI/QPI
SPI/QPI
SPI
0
SPI
0
SPI
0
SPI
0
Address Bytes
1st byte
0
0
0
2B (hex)
2F (hex)
7E (hex)
98 (hex)
2C (hex)
2D (hex)
28 (hex)
27 (hex)
2nd byte
3rd byte
4th byte
5th byte
Data Cycles
Action
2
2
1-8
1-8
to read value to set the whole
chip whole
chip
of security lock-down bit write protect unprotect
register
as "1" (once
lock-down,
cannot
be
updated)
Command
(byte)
PASSULK
(password
unlock)
SPI
WRSPB
(SPB
ESSPB
bit (all SPB bit (read
erase) status)
SPI SPI
RDSPB
SPBLK
RDSPBLK
WRDPB
RDDPB
SPB (SPB
set)
lock (SPB
lock (write
DPB (read
DPB
program)
SPI
register read) register)
register)
Mode
SPI
0
SPI
0
SPI
4
SPI
4
Address Bytes
1st byte
0
4
0
4
29 (hex)
E3 (hex)
ADD1
ADD2
ADD3
E4 (hex)
E2 (hex)
ADD1
ADD2
ADD3
A6 (hex)
A7 (hex)
E1 (hex)
ADD1
ADD2
ADD3
E0 (hex)
2nd byte
3rd byte
4th byte
ADD1
ADD2
ADD3
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Command
(byte)
PASSULK
(password
unlock)
WRSPB
(SPB
ESSPB
bit (all SPB bit (read
erase) status)
ADD4
RDSPB
SPBLK
SPB (SPB
set)
RDSPBLK
WRDPB
RDDPB
DPB (read
register)
lock (SPB lock (write
DPB
program)
ADD4
register read) register)
5th byte
Data Cycles
Action
ADD4
ADD4
1
8
1
2
1
9.1.2. Reset Commands
Command
(byte)
NOP
RSTEN
RST
(No
(Reset
(Reset
Memory)
Operation)
Enable)
Mode
SPI/QPI
00 (hex)
SPI/QPI
66 (hex)
SPI/QPI
99 (hex)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SO/SIO1 which is different from 1 x I/O condition.
Note 2: ADD=00H will output the manufacturer ID first and AD=01H will output device ID first.
Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode.
Note 4: RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
Note 5: The number in parentheses after "ADD" or "Data" stands for how many clock cycles it has. For example, "Data(8)" represents there are 8 clock cycles
for the data in.
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9.2. Write Enable (WREN)
- PASSWD check mode
- Write SPB lock bit
- Write SPB bit
The Write Enable (WREN) instruction is for setting Write Enable
Latch (WEL) bit. For those instructions like PP, 4PP, SE, BE32K,
BE, CE, and WRSR, which are intended to change the device
content WEL bit should be set every time after the WREN
instruction setting the WEL bit.
- Erase SPB bit
- DPB write
- Fastboot write
- Fastboot erase mode
The sequence of issuing WREN instruction is: CS# goes
low→sending WREN instruction code→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care in SPI mode.
Figure 6. Write Enable (WREN) Sequence (SPI Mode)
Figure 8. Write Disable (WRDI) Sequence (SPI Mode)
Figure 9. Write Disable (WRDI) Sequence (QPI Mode)
Figure 7. Write Enable (WREN) Sequence (QPI Mode)
9.4. Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte
and followed by Device ID of 2-byte. The Manufacturer ID and
Device ID are listed as "Table 6. ID Definitions".
9.3. Write Disable (WRDI)
The Write Disable (WRDI) instruction is to reset Write Enable
Latch (WEL) bit.
The sequence of issuing RDID instruction is: CS# goes low→
sending RDID instruction code→24-bits ID data out on SO→ to
end RDID operation can drive CS# to high at any time during data
out.
The sequence of issuing WRDI instruction is: CS# goes
low→sending WRDI instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care in SPI mode.
The WEL bit is reset by following situations:
- Power-up
While Program/Erase operation is in progress, it will not decode
the RDID instruction, therefore there's no effect on the cycle of
program/erase operation which is currently in progress. When
CS# goes high, the device is at standby stage.
- Reset# pin driven low
Figure 10. Read Identification (RDID) Sequence (SPI mode only)
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase 32KB (BE32K) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
- Program/Erase Suspend
9.5. Release from Deep Power-down (RDP), Read
Electronic Signature (RES)
- Softreset command completion
- Write Security Register (WRSCUR) command completion
- Write Protection Selection (WPSEL) command completion
- GBLK command completion
The Release from Deep Power-down (RDP) instruction is
completed by driving Chip Select (CS#) High. When Chip Select
(CS#) is driven High, the device is put in the Stand-by Power mode.
If the device was not previously in the Deep Power-down mode,
the transition to the Stand-by Power mode is immediate. If the
device was previously in the Deep Power-down mode, though, the
transition to the Stand-by Power mode is delayed by tRES2, and
- GBULK command completion
- WEAR command completion
- ASP program
- PASSWD program
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Chip Select (CS#) must remain High for at least tRES2(max), as
specified in "Table 17. AC CHARACTERISTICS". Once in the
Stand-by Power mode, the device waits to be selected, so that it
Figure 13. Release from Deep Power-down (RDP) Sequence (SPI
Mode)
can receive, decode and execute instructions.
The RDP
instruction is only for releasing from Deep Power Down Mode.
Reset# pin goes low will release the Flash from deep power down
mode.
RES instruction is for reading out the old style of 8-bit Electronic
Signature, whose values are shown as "Table 6. ID Definitions".
This is not the same as RDID instruction. It is not recommended
to use for new design. For new design, please use RDID
instruction.
Figure 14. Release from Deep Power-down (RDP) Sequence (QPI
Mode)
Even in Deep power-down mode, the RDP and RES are also
allowed to be executed, only except the device is in progress of
program/erase/write cycle; there's no effect on the current
program/erase/write cycle in progress.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
9.6. Read Electronic Manufacturer ID & Device ID
(REMS)
The REMS instruction is an alternative to the Release from
Power-down/Device ID instruction that provides both the JEDEC
assigned manufacturer ID and the specific device ID.
The RES instruction is ended by CS# goes high after the ID been
read out at least once. The ID outputs repeatedly if continuously
send the additional clock cycles on SCLK while CS# is at low. If
the device was not previously in Deep Power-down mode, the
device transition to standby mode is immediate. If the device was
previously in Deep Power-down mode, there's a delay of tRES2 to
transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be
selected, so it can be receive, decode, and execute instruction.
The REMS instruction is very similar to the Release from
Power-down/Device ID instruction. The instruction is initiated by
driving the CS# pin low and shift the instruction code "90h"
followed by two dummy bytes and one bytes address (A7~A0).
After which, the Manufacturer ID for (C2h) and the Device ID are
shifted out on the falling edge of SCLK with most significant bit
(MSB) first. The Device ID values are listed in "Table 6. ID
Definitions". If the one-byte address is initially set to 01h, then
the device ID will be read first and then followed by the
Manufacturer ID. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is
completed by driving CS# high.
Figure 11. Read Electronic Signature (RES) Sequence (SPI Mode)
Figure 15. Read Electronic Manufacturer & Device ID (REMS)
Sequence (SPI Mode only)
Figure 12. Read Electronic Signature (RES) Sequence (QPI
Mode)
Notes:
ADD=00H will output the manufacturer's ID first and ADD=01H will output
device ID first.
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9.7. QPI ID Read (QPIID)
Immediately following the command cycle the device outputs data
on the falling edge of the SCLK signal. The data output stream is
continuous until terminated by a low-to high transition of CS#.
The device outputs three bytes of data: manufacturer, device type,
and device ID.
The QPIID Read instruction identifies the devices as
GPR25L12805F and Manufacturer ID. The sequence of issue
QPIID instruction is CS# goes low→sending QPI ID
instruction→Data out on SO→CS# goes high. Most significant bit
(MSB) first.
Table 6. ID Definitions
Command Type
Manufactory ID
GPR25L12805F
Memory type
Memory density
18
RDID
9Fh
ABh
90h
AFh
C2
20
Electronic ID
17
RES
Manufactory ID
Device ID
17
REMS
QPIID
C2
Manufactory ID
C2
Memory type
20
Memory density
18
9.8. Read Status Register (RDSR)
9.9. Read Configuration Register (RDCR)
The RDSR instruction is for reading Status Register Bits. The
Read Status Register can be read at any time (even in
program/erase/write status register condition). It is recommended
to check the Write in Progress (WIP) bit before sending a new
The RDCR instruction is for reading Configuration Register Bits.
The Read Configuration Register can be read at any time (even in
program/erase/write configuration register condition).
It is
recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write
configuration register operation is in progress.
instruction when
a program, erase, or write status register
operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→
sending RDSR instruction code→ Status Register data out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
The sequence of issuing RDCR instruction is: CS# goes low→
sending RDCR instruction code→ Configuration Register data out
on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
Figure 16. Read Status Register (RDSR) Sequence (SPI Mode)
Figure 18. Read Configuration Register (RDCR) Sequence (SPI
Mode)
Figure 17. Read Status Register (RDSR) Sequence (QPI Mode)
Figure 19. Read Configuration Register (RDCR) Sequence (QPI
Mode)
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For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:
Figure 20. Program/Erase flow with read array data
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Figure 21. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)
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Status Register
set. To write the Block Protect (BP3, BP2, BP1, BP0) bits
requires the Write Status Register (WRSR) instruction to be
executed. Those bits define the protected area of the memory to
against Page Program (PP), Sector Erase (SE), Block Erase 32KB
(BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only
if Block Protect bits (BP3:BP0) set to 0, the CE instruction can be
executed). The BP3, BP2, BP1, BP0 bits are "0" as default.
Which is un-protected.
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates
whether the device is busy in program/erase/write status register
progress. When WIP bit sets to 1, which means the device is
busy in program/erase/write status register progress. When WIP
bit sets to 0, which means the device is not in progress of
program/erase/write status register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates
whether the device is set to internal write enable latch. When
WEL bit sets to 1, which means the internal write enable latch is
set, the device can accept program/ erase/write status register
instruction. When WEL bit sets to 0, which means no internal
write enable latch; the device will not accept program/erase/write
status register instruction. The program/erase command will be
ignored if it is applied to a protected memory area. To ensure
both WIP bit & WEL bit are both set to 0 and available for next
program/ erase/operations, WIP bit needs to be confirm to be 0
before polling WEL bit. After WIP bit confirmed, WEL bit needs to
be confirm to be 0.
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0"
(factory default), it performs non-Quad and WP#, RESET# are
enable. While QE is "1", it performs Quad I/O mode and WP#,
RESET# are disabled. In the other word, if the system goes into
four I/O mode (QE=1), the feature of HPM and RESET# will be
disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit,
non-volatile bit, is operated together with Write Protection
(WP#/SIO2) pin for providing hardware protection mode. The
hardware protection mode requires SRWD sets to
1 and
WP#/SIO2 pin signal is low stage. In the hardware protection
mode, the Write Status Register (WRSR) instruction is no longer
accepted for execution and the SRWD bit and Block Protect bits
(BP3, BP2, BP1, BP0) are read only. The SRWD bit defaults to
be "0".
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1,
BP0) bits, non-volatile bits, indicate the protected area (as defined
in "Table 2. Protected Area Sizes") of the device to against the
program/erase instruction without hardware protection mode being
Status Register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SRWD (status QE
BP3
BP2
BP1
BP0
WEL
WIP
register write
protect)
(Quad Enable) (level of
(level of
(level of
(level of
(write enable
(write in
progress bit)
protected block) protected block) protected block) protected block) latch)
1=status
1=Quad Enable (note 1)
0=not Quad
(note 1)
(note 1)
(note 1)
1=write enable 1=write
register write
disable
0=not write
enable
operation
Enable
0=not in write
operation
Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit volatile bit
volatile bit
Note 1: See the "Table 2. Protected Area Sizes".
Configuration Register
TB bit
The Configuration Register is able to change the default status of
Flash memory. Flash memory will be configured after the CR bit
is set.
The Top/Bottom (TB) bit is
a
non-volatile OTP bit.
The
Top/Bottom (TB) bit is used to configure the Block Protect area by
BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the
memory array. The TB bit is defaulted as “0”, which means Top
area protect. When it is set as “1”, the protect area will change to
Bottom area of the memory device. To write the TB bits requires
the Write Status Register (WRSR) instruction to be executed.
ODS bit
The output driver strength (ODS2, ODS1, ODS0) bits are volatile
bits, which indicate the output driver level (as defined in Output
Driver Strength Table) of the device. The Output Driver Strength
is defaulted as 30 Ohms when delivered from factory. To write
the ODS bits requires the Write Status Register (WRSR)
instruction to be executed.
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Table 7. Configuration Register Table
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DC1
DC0
Reserved
Reserved
TB
ODS 2
ODS 1
driver (output
strength)
ODS 0
driver (output
strength)
(Dummy cycle 1) (Dummy cycle 0)
(top/bottom selected) (output
strength)
driver
(note 2)
(note 2)
x
x
x
0=Top area protect
(note 1)
(note 1)
(note 1)
1=Bottom
area
protect (Default=0)
OTP
volatile bit
volatile bit
x
volatile bit
volatile bit
volatile bit
Note 1: see "Output Driver Strength Table"
Note 2: see "Dummy Cycle and Frequency Table (MHz)"
Output Driver Strength Table
ODS2
ODS1
ODS0
Description
Note
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
90 Ohms
60 Ohms
45 Ohms
Impedance at VCC/2
Reserved
20 Ohms
15 Ohms
30 Ohms (Default)
Dummy Cycle and Frequency Table (MHz)
DC[1:0]
Numbers of Dummy Fast Read
clock cycles
Dual Output Fast Read
Quad
Read
Output
Fast
01
6
8
104
104
104
133
104
84
10
104
133
104
104
133
104
11
10
8
00 (default)
DC[1:0]
Numbers of Dummy Dual IO Fast Read
clock cycles
01
6
8
104
104
133
84
10
11
10
4
00 (default)
DC[1:0]
Numbers of Dummy Quad IO Fast Read
clock cycles
01
4
8
70
104
133
84
10
11
10
6
00 (default)
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9.10. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status
Register Bits and Configuration Register Bits. Before sending
WRSR instruction, the Write Enable (WREN) instruction must be
decoded and executed to set the Write Enable Latch (WEL) bit in
advance. The WRSR instruction can change the value of Block
Protect (BP3, BP2, BP1, BP0) bits to define the protected area of
memory (as shown in "Table 2. Protected Area Sizes"). The
WRSR also can set or reset the Quad enable (QE) bit and set or
reset the Status Register Write Disable (SRWD) bit in accordance
with Write Protection (WP#/SIO2) pin signal, but has no effect on
bit1(WEL) and bit0 (WIP) of the status register. The WRSR
instruction cannot be executed once the Hardware Protected
Mode (HPM) is entered.
Figure 23. Write Status Register (WRSR) Sequence (QPI Mode)
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP#/SIO2 is low or high, the
WREN instruction may set the WEL bit and can change the values
of SRWD, BP3, BP2, BP1, BP0. The protected area, which is
defined by BP3, BP2, BP1, BP0 and T/B bit, is at software
protected mode (SPM).
- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction
may set the WEL bit can change the values of SRWD, BP3, BP2,
BP1, BP0. The protected area, which is defined by BP3, BP2,
BP1, BP0 and T/B bit, is at software protected mode (SPM)
The sequence of issuing WRSR instruction is: CS# goes low→
sending WRSR instruction code→ Status Register data on
SI→CS# goes high.
The CS# must go high exactly at the 8 bits or 16 bits data
boundary; otherwise, the instruction will be rejected and not
executed. The self-timed Write Status Register cycle time (tW) is
initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Write Status
Register cycle is in progress. The WIP sets 1 during the tW
timing, and sets 0 when Write Status Register Cycle is completed,
and the Write Enable Latch (WEL) bit is reset.
Note:
If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status
Register even if the WEL bit has previously been set. It is rejected to write
the Status Register and not be executed.
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is
low before SRWD bit=1), it enters the hardware protected mode
(HPM). The data of the protected area is protected by software
protected mode by BP3, BP2, BP1, BP0 and T/B bit and hardware
protected mode by the WP#/SIO2 to against data modification.
Figure 22. Write Status Register (WRSR) Sequence (SPI Mode)
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once
the hardware protected mode is entered. If the WP#/SIO2 pin is
permanently connected to high, the hardware protected mode can never be
entered; only can use software protected mode via BP3, BP2, BP1, BP0 and
T/B bit.
Note: The CS# must go high exactly at 8 bits or 16 bits data boundary to
completed the write register command.
If the system enter QPI or set QE=1, the feature of HPM will be disabled.
Table 8. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Software
(SPM)
protection
mode Status register can be written in WP#=1 and SRWD bit=0, or The protected area cannot be
(WEL bit is set to "1") and the WP#=0 and SRWD bit=0, or program or erase.
SRWD, BP0-BP3 bits can be WP#=1 and SRWD=1
changed
Hardware protection mode The SRWD, BP0-BP3 of status WP#=0, SRWD bit=1
(HPM) register bits cannot be changed
The protected area cannot be
program or erase.
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in "Table 2. Protected Area Sizes".
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Figure 24. WRSR flow
Figure 25. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
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9.11. Read Data Bytes (READ)
Figure 27. Read at Higher Speed (FAST_READ) Sequence (SPI
Mode)
The read instruction is for reading data out. The address is
latched on rising edge of SCLK, and data shifts out on the falling
edge of SCLK at a maximum frequency fR. The first address
byte can be at any location. The address is automatically
increased to the next higher address after each byte data is shifted
out, so the whole memory can be read out at a single READ
instruction. The address counter rolls over to 0 when the highest
address has been reached.
The sequence of issuing READ instruction is: CS# goes
low→sending READ instruction code→ 3-byte address on SI→
data out on SO→to end READ operation can use CS# to high at
any time during data out.
Figure 26. Read Data Bytes (READ) Sequence (SPI Mode only)
9.13. Dual Output Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial Flash
in read mode. The address is latched on rising edge of SCLK,
and data of every two bits (interleave on 2 I/O pins) shift out on the
falling edge of SCLK at a maximum frequency fT. The first
address byte can be at any location.
The address is
9.12. Read Data Bytes at Higher Speed (FAST_READ)
automatically increased to the next higher address after each byte
data is shifted out, so the whole memory can be read out at a
single DREAD instruction. The address counter rolls over to 0
when the highest address has been reached. Once writing
DREAD instruction, the following data out will perform as 2-bit
instead of previous 1-bit.
The FAST_READ instruction is for quickly reading data out. The
address is latched on rising edge of SCLK, and data of each bit
shifts out on the falling edge of SCLK at a maximum frequency fC.
The first address byte can be at any location. The address is
automatically increased to the next higher address after each byte
data is shifted out, so the whole memory can be read out at a
single FAST_READ instruction. The address counter rolls over to
0 when the highest address has been reached.
The sequence of issuing DREAD instruction is: CS# goes low→
sending DREAD instruction→3-byte address on SIO0→ 8 dummy
cycles (default) on SIO0→ data out interleave on SIO1 & SIO0→
to end DREAD operation can use CS# to high at any time during
data out.
Read on SPI Mode The sequence of issuing FAST_READ
instruction is: CS# goes low→ sending FAST_READ instruction
code→ 3-byte address on SI→ 8 dummy cycles (default)→ data
out on SO→ to end FAST_READ operation can use CS# to high at
any time during data out.
While Program/Erase/Write Status Register cycle is in progress,
DREAD instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
Figure 28. Dual Read Mode Sequence
In the performance-enhancing mode, P[7:4] must be toggling with
P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can make this mode
continue and reduce the next 4READ instruction. Once P[7:4] is
no longer toggling with P[3:0]; likewise P[7:0]=FFh,00h,AAh or 55h
and afterwards CS# is raised and then lowered, the system then
will escape from performance enhance mode and return to normal
operation.
While Program/Erase/Write Status Register cycle is in progress,
FAST_READ instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
9.14. 2 x I/O Read Mode (2READ)
The 2READ instruction enable double throughput of Serial Flash in
read mode. The address is latched on rising edge of SCLK, and
data of every two bits (interleave on 2 I/O pins) shift out on the
falling edge of SCLK at a maximum frequency fT. The first
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address byte can be at any location.
The address is
Figure 30. Quad Read Mode Sequence
automatically increased to the next higher address after each byte
data is shifted out, so the whole memory can be read out at a
single 2READ instruction. The address counter rolls over to 0
when the highest address has been reached. Once writing
2READ instruction, the following address/dummy/data out will
perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→
sending 2READ instruction→ 3-byte address interleave on SIO1 &
SIO0→ 4 dummy cycles (default) on SIO1 & SIO0→ data out
interleave on SIO1 & SIO0→ to end 2READ operation can use
CS# to high at any time during data out.
9.16. 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in
read mode. A Quad Enable (QE) bit of status Register must be
set to "1" before sending the 4READ instruction. The address is
latched on rising edge of SCLK, and data of every four bits
(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any
location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole
memory can be read out at a single 4READ instruction. The
address counter rolls over to 0 when the highest address has been
reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous
1-bit.
While Program/Erase/Write Status Register cycle is in progress,
2READ instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
Figure 29. 2 x I/O Read Mode Sequence (SPI Mode only)
9.15. Quad Read Mode (QREAD)
4 x I/O Read on SPI Mode (4READ) The sequence of issuing
4READ instruction is: CS# goes low→ sending 4READ
instruction→ 3-byte address interleave on SIO3, SIO2, SIO1 &
SIO0→ 6 dummy cycles (Default) →data out interleave on SIO3,
SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to
high at any time during data out.
The QREAD instruction enable quad throughput of Serial Flash in
read mode. The address is latched on rising edge of SCLK, and
data of every four bits (interleave on 4 I/O pins) shift out on the
falling edge of SCLK at a maximum frequency fQ. The first
address byte can be at any location.
The address is
automatically increased to the next higher address after each byte
data is shifted out, so the whole memory can be read out at a
single QREAD instruction. The address counter rolls over to 0
when the highest address has been reached. Once writing
QREAD instruction, the following data out will perform as 4-bit
instead of previous 1-bit.
4 x I/O Read on QPI Mode (4READ) The 4READ instruction also
support on QPI command mode. The sequence of issuing
4READ instruction QPI mode is: CS# goes low→ sending 4READ
instruction→ 3-byte address interleave on SIO3, SIO2, SIO1 &
SIO0→ 6 dummy cycles (Default) →data out interleave on SIO3,
SIO2, SIO1 & SIO0→ to end 4READ operation can use CS# to
high at any time during data out.
The sequence of issuing QREAD instruction is: CS# goes low→
sending QREAD instruction → 3-byte address on SI → 8 dummy
cycle (Default) → data out interleave on SO3, SO2, SO1 & SO0→
to end QREAD operation can use CS# to high at any time during
data out.
While Program/Erase/Write Status Register cycle is in progress,
4READ instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
While Program/Erase/Write Status Register cycle is in progress,
QREAD instruction is rejected without any impact on the
Program/Erase/Write Status Register current cycle.
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Figure 31. 4 x I/O Read Mode Sequence (SPI Mode)
Figure 32. 4 x I/O Read Mode Sequence (QPI Mode)
9.17. Burst Read
This device supports Burst Read in both SPI and QPI mode.
To set the Burst length, following command operation is required to
issue command: “C0h” in the first Byte (8-clocks), following 4
clocks defining wrap around enable with “0h” and disable with“1h”.
The next 4 clocks are to define wrap around depth. Their
definitions are as the following table:
Notes:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
3. Configuration Dummy cycle numbers will be different depending on the
bit6 & bit 7 (DC0 & DC1) setting in configuration register.
Data
1xh
1xh
1xh
1xh
Wrap Around
Wrap Depth
Data
00h
01h
02h
03h
Wrap Around
Wrap Depth
8-byte
No
No
No
No
X
X
X
X
Yes
Yes
Yes
Yes
16-byte
32-byte
64-byte
9.18. Performance Enhance Mode
The wrap around unit is defined within the 256Byte page, with
random initial address. It is defined as “wrap-around mode
disable” for the default state of the device. To exit wrap around, it
is required to issue another “C0” command in which data=‘1xh”.
Otherwise, wrap around status will be retained until power down or
reset command. To change wrap around depth, it is required to
issue another “C0” command in which data=“0xh”. QPI “EBh”
and SPI “EBh” support wrap around feature after wrap around is
enabled. Burst read is supported in both SPI and QPI mode.
The device is default without Burst read.
The device could waive the command cycle bits if the two cycle
bits after address cycle toggles.
Performance enhance mode is supported in both SPI and QPI
mode.
In QPI mode, “EBh” and SPI “EBh” commands support enhance
mode. The performance enhance mode is not supported in dual
I/O mode.
To enter performance-enhancing mode, P[7:4] must be toggling
with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can make this
mode continue and skip the next 4READ instruction. To leave
enhance mode, P[7:4] is no longer toggling with P[3:0]; likewise
P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised
and then lowered. Issuing ”FFh” command can also exit enhance
mode. The system then will leave performance enhance mode
and return to normal operation.
Figure 33. SPI Mode
Figure 34. QPI Mode
After entering enhance mode, following CS# go high, the device
will stay in the read mode and treat CS# go low of the first clock as
address instead of command cycle.
Another sequence of issuing 4READ instruction especially useful
in random access is
: CS# goes low→sending 4 READ
Note: MSB=Most Significant Bit
instruction→3-bytes address interleave on SIO3, SIO2, SIO1 &
SIO0 →performance enhance toggling bit P[7:0]→ 4 dummy
cycles (Default) →data out still CS# goes high → CS# goes low
(reduce 4 Read instruction) → 3-bytes random access address.
LSB=Least Significant Bit
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Figure 35. 4 x I/O Read enhance performance Mode Sequence
(SPI Mode)
mode.
Figure 37. Performance Enhance Mode Reset for Fast Read Quad
I/O (SPI Mode)
Figure 38. Performance Enhance Mode Reset for Fast Read Quad
I/O (QPI Mode)
9.20. Fast Boot
The Fast Boot Feature provides the ability to automatically execute
read operation after power on cycle or reset without any read
instruction.
Notes:
1. If not using performance enhance recommend to keep
performance enhance indicator.
1 or 0 in
2. Configuration Dummy cycle numbers will be different depending on the
bit6 & bit 7 (DC0 & DC1) setting in configuration register.
A Fast Boot Register is provided on this device. It can enable the
Fast Boot function and also define the number of delay cycles and
start address (where boot code being transferred). Instruction
WRFBR (write fast boot register) and ESFBR (erase fast boot
register) can be used for the status configuration or alternation of
the Fast Boot Register bit. RDFBR (read fast boot register) can
be used to verify the program state of the Fast Boot Register.
The default number of delay cycles is 12 cycles (11h), and there is
a 8bytes boundary address for the start of boot code access.
When CS# starts to go low, data begins to output from default
address after the delay cycles (default as 12 cycles). After CS#
returns to go high, the device will go back to standard SPI mode.
In the fast boot data out process from CS# goes low to CS# goes
high, a minimum of one byte must be output.
Figure 36. 4 x I/O Read enhance performance Mode Sequence
(QPI Mode)
Notes:
Once Fast Boot feature has been enabled, the device will
automatically start a read operation after power on cycle, reset
command, or hardware reset operation.
1. Configuration Dummy cycle numbers will be different depending on the
bit6 & bit 7 (DC0 & DC1) setting in configuration register.
The fast Boot feature can support Single I/O and Quad I/O
interface. If the QE bit of Status Register is “0”, the data is output
by Single I/O interface. If the QE bit of Status Register is set to
“1”, the data is output by Quad I/O interface.
9.19. Performance Enhance Mode Reset
To conduct the Performance Enhance Mode Reset operation in
SPI mode, FFh data cycle, 8 clocks, should be issued in 1I/O
sequence. In QPI Mode, FFFFFFFFh data cycle, 8 clocks, in
4I/O should be issued.
If the system controller is being Reset during operation, the flash
device will return to the standard SPI operation.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
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Fast Boot Register (FBR)
Bits
Description
Bit Status
Default State
Type
31 to 4
FBSA (FastBoot Start Address)
8 bytes boundary address for FFFFFFF
Non- Volatile
the start of boot code access.
1
3
x
Non- Volatile
Non- Volatile
2 to 1
FBSD (FastBoot Start Delay 00: 6 delay cycles
11
Cycle)
01: 8 delay cycles
10: 10 delay cycles
11: 12 delay cycles
0
FBE (FastBoot Enable)
0=FastBoot is enabled.
1=FastBoot is not enabled.
1
Non- Volatile
Note: If FBSD = 11, the maximum clock frequency is 133 MHz
If FBSD = 10, the maximum clock frequency is 104 MHz
If FBSD = 01, the maximum clock frequency is 84 MHz
If FBSD = 00, the maximum clock frequency is 70 MHz
Figure 39. Fast Boot Sequence (QE bit =0)
Figure 42. Write Fast Boot Register (WRFBR) Sequence
Figure 43. Erase Fast Boot Register (ESFBR) Sequence
Figure 40. Fast Boot Sequence (QE bit =1)
Figure 41. Read Fast Boot Register (RDFBR) Sequence
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9.21. Sector Erase (SE)
instruction. The CS# must go high exactly at the byte boundary
(the least significant bit of address byte been latched-in); otherwise,
the instruction will be rejected and not executed.
The Sector Erase (SE) instruction is for erasing the data of the
chosen sector to be "1". The instruction is used for any 4K-byte
sector. A Write Enable (WREN) instruction must execute to set
the Write Enable Latch (WEL) bit before sending the Sector Erase
The sequence of issuing BE32K instruction is: CS# goes low→
sending BE32K instruction code→ 3-byte address on SI→CS#
goes high.
(SE).
Any address of the sector (see "Table 4. Memory
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
Organization") is a valid address for Sector Erase (SE) instruction.
The CS# must go high exactly at the byte boundary (the least
significant bit of the address byte been latched-in); otherwise, the
instruction will be rejected and not executed.
The self-timed Block Erase Cycle time (tBE32K) is initiated as
soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be checked while during the Block Erase cycle is
in progress. The WIP sets during the tBE32K timing, and clears
when Block Erase Cycle is completed, and the Write Enable Latch
(WEL) bit is cleared. If the Block is protected by BP bits
(WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1;
Advanced Sector Protect Mode), the Block Erase (BE32K)
instruction will not be executed on the block.
Address bits [Am-A12] (Am is the most significant address) select
the sector address.
The sequence of issuing SE instruction is: CS# goes low→
sending SE instruction code→ 3-byte address on SI→ CS# goes
high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon
as Chip Select (CS#) goes high. The Write in Progress (WIP) bit
still can be checked while the Sector Erase cycle is in progress.
The WIP sets 1 during the tSE timing, and clears when Sector
Erase Cycle is completed, and the Write Enable Latch (WEL) bit is
cleared. If the Block is protected by BP bits (WPSEL=0; Block
Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect
Mode), the Sector Erase (SE) instruction will not be executed on
the block.
Figure 46. Block Erase 32KB (BE32K) Sequence (SPI Mode)
Figure 47. Block Erase 32KB (BE32K) Sequence (QPI Mode)
Figure 44. Sector Erase (SE) Sequence (SPI Mode)
9.23. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the
chosen block to be "1". The instruction is used for 64K-byte block
erase operation. A Write Enable (WREN) instruction must be
executed to set the Write Enable Latch (WEL) bit before sending
the Block Erase (BE). Any address of the block (Please refer to
"Table 4. Memory Organization") is a valid address for Block Erase
(BE) instruction. The CS# must go high exactly at the byte
boundary (the least significant bit of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low→
sending BE instruction code→ 3-byte address on SI→ CS# goes
high.
Figure 45. Sector Erase (SE) Sequence (QPI Mode)
9.22. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the
chosen block to be "1". The instruction is used for 32K-byte block
erase operation. A Write Enable (WREN) instruction be executed
to set the Write Enable Latch (WEL) bit before sending the Block
Erase (BE32K). Any address of the block (see "Table 4. Memory
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as
Organization") is
a valid address for Block Erase (BE32K)
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Chip Select (CS#) goes high. The Write in Progress (WIP) bit still
can be checked while the Block Erase cycle is in progress. The
WIP sets during the tBE timing, and clears when Block Erase
Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
If the Block is protected by BP bits (WPSEL=0; Block Protect
Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode),
the Block Erase (BE) instruction will not be executed on the block.
Figure 50. Chip Erase (CE) Sequence (SPI Mode)
Figure 51. Chip Erase (CE) Sequence (QPI Mode)
Figure 48. Block Erase (BE) Sequence (SPI Mode)
9.25. Page Program (PP)
The Page Program (PP) instruction is for programming the
memory to be "0". A Write Enable (WREN) instruction must be
executed to set the Write Enable Latch (WEL) bit before sending
the Page Program (PP). The device programs only the last 256
data bytes sent to the device. If the entire 256 data bytes are
going to be programmed, A7- A0 (The eight least significant
address bits) should be set to 0. If the eight least significant
address bits (A7-A0) are not all 0, all transmitted data going
beyond the end of the current page are programmed from the start
address of the same page (from the address A7-A0 are all 0). If
more than 256 bytes are sent to the device, the data of the last
256-byte is programmed at the requested page and previous data
will be disregarded. If less than 256 bytes are sent to the device,
the data is programmed at the requested address of the page
without effect on other address of the same page.
Figure 49. Block Erase (BE) Sequence (QPI Mode)
9.24. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the
whole chip to be "1". A Write Enable (WREN) instruction must be
executed to set the Write Enable Latch (WEL) bit before sending
the Chip Erase (CE). The CS# must go high exactly at the byte
boundary, otherwise the instruction will be rejected and not
executed.
The sequence of issuing PP instruction is: CS# goes low→
sending PP instruction code→ 3-byte address on SI→ at least
1-byte on data on SI→ CS# goes high.
The sequence of issuing CE instruction is: CS# goes low→sending
CE instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
The CS# must be kept to low during the whole Page Program
cycle; The CS# must go high exactly at the byte boundary( the
latest eighth bit of data being latched in), otherwise the instruction
will be rejected and will not be executed.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as
Chip Select (CS#) goes high. The Write in Progress (WIP) bit still
can be checked while the Chip Erase cycle is in progress. The
WIP sets during the tCE timing, and clears when Chip Erase Cycle
is completed, and the Write Enable Latch (WEL) bit is cleared.
When the chip is under "Block protect (BP) Mode" (WPSEL=0).
The Chip Erase(CE) instruction will not be executed, if one (or
more) sector is protected by BP3-BP0 bits. It will be only
executed when BP3-BP0 all set to "0".
The self-timed Page Program Cycle time (tPP) is initiated as soon
as Chip Select (CS#) goes high. The Write in Progress (WIP) bit
still can be checked while the Page Program cycle is in progress.
The WIP sets during the tPP timing, and clears when Page
Program Cycle is completed, and the Write Enable Latch (WEL) bit
is cleared. If the Block is protected by BP bits (WPSEL=0; Block
Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect
Mode) the Page Program (PP) instruction will not be executed.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
When the chip is under "Advances Sector Protect Mode"
(WPSEL=1). The Chip Erase (CE) instruction will be executed on
unprotected block. The protected Block will be skipped. If one
(or more) 4K byte sector was protected in top or bottom 64K byte
block, the protected block will also skip the chip erase command.
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Figure 52. Page Program (PP) Sequence (SPI Mode)
Power-down (DP) instruction to enter, during the Deep
Power-down mode, the device is not active and all
Write/Program/Erase instruction are ignored. When CS# goes
high, it's only in deep power-down mode not standby mode. It's
different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→sending
DP instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
Once the DP instruction is set, all instruction will be ignored except
the Release from Deep Power-down mode (RDP) and Read
Electronic Signature (RES) instruction and softreset command.
(those instructions allow the ID being reading out). When
Power-down, or software reset command the deep power-down
mode automatically stops, and when power-up, the device
automatically is in standby mode. For DP instruction the CS#
must go high exactly at the byte boundary (the latest eighth bit of
instruction code been latched-in); otherwise, the instruction will not
executed. As soon as Chip Select (CS#) goes high, a delay of
tDP is required before entering the Deep Power-down mode.
Figure 55. Deep Power-down (DP) Sequence (SPI Mode)
Figure 53. Page Program (PP) Sequence (QPI Mode)
9.26. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the
memory to be "0". A Write Enable (WREN) instruction must be
executed to set the Write Enable Latch (WEL) bit and Quad
Enable (QE) bit must be set to "1" before sending the Quad Page
Program (4PP). The Quad Page Programming takes four pins:
SIO0, SIO1, SIO2, and SIO3 as address and data input, which can
improve programmer performance and the effectiveness of
application. The other function descriptions are as same as
standard page program.
Figure 56. Deep Power-down (DP) Sequence (QPI Mode)
The sequence of issuing 4PP instruction is: CS# goes low→
sending 4PP instruction code→ 3-byte address on SIO[3:0]→ at
least 1-byte on data on SIO[3:0]→CS# goes high.
If the page is protected by BP bits (WPSEL=0; Block Protect Mode)
or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode), the
Quad Page Program (4PP) instruction will not be executed.
9.28. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit secured
OTP mode. While device is in 4K-bit secured OTP mode, main
array access is not available. The additional 4K-bit secured OTP
is independent from main array and may be used to store unique
serial number for system identifier. After entering the Secured
OTP mode, follow standard read or program procedure to read out
the data or update data. The Secured OTP data cannot be
updated again once it is lock-down.
Figure 54. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)
The sequence of issuing ENSO instruction is: CS# goes low→
sending ENSO instruction to enter Secured OTP mode→ CS#
goes high.
9.27. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device to
minimum power consumption (the standby current is reduced from
ISB1 to ISB2). The Deep Power-down mode requires the Deep
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
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Please note that after issuing ENSO command user can only
access secure OTP region with standard read or program
procedure. Furthermore, once security OTP is lock down, only
read related commands are valid.
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
The CS# must go high exactly at the boundary; otherwise, the
instruction will be rejected and not executed.
9.29. Exit Secured OTP (EXSO)
Security Register
The definition of the Security Register bits is as below:
Write Protection Selection bit. Please reference to "Write
Protection Selection"
The EXSO instruction is for exiting the additional 4K-bit secured
OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→
sending EXSO instruction to exit Secured OTP mode→ CS# goes
high.
Erase Fail bit. The Erase Fail bit is a status flag, which shows the
status of last Erase operation. It will be set to "1", if the erase
operation fails or the erase region is protected. It will be set to "0",
if the last operation is success. Please note that it will not
interrupt or stop any operation in the flash memory.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
Program Fail bit. The Program Fail bit is a status flag, which
shows the status of last Program operation. It will be set to "1", if
the program operation fails or the program region is protected. It
will be set to "0", if the last operation is success. Please note that
it will not interrupt or stop any operation in the flash memory.
Erase Suspend bit. Erase Suspend bit (ESB) indicates the status
of Erase suspend operation. When issue a suspend command
during erase operation ESB=1, when erase operation resumes,
ESB will be reset to "0".
9.30. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security
Register bits. The Read Security Register can be read at any
time (even in program/erase/write status register/write security
register condition) and continuously.
The sequence of issuing RDSCUR instruction is: CS# goes
low→sending RDSCUR instruction→Security Register data out on
SO→ CS# goes high.
Program Suspend bit. Program Suspend Bit (PSB) indicates the
status of Program suspend operation. When issue a suspend
command during program operation PSB=1, when program
operation resumes, PSB will be reset to "0".
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
Secured OTP Indicator bit. The Secured OTP indicator bit shows
the chip is locked by factory or not. When it is "0", it indicates
non-factory lock; "1" indicates factory-lock.
9.31. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security
Register Bits. The WREN (Write Enable) instruction is required
before issuing WRSCUR instruction. The WRSCUR instruction
may change the values of bit1 (LDSO bit) for customer to
lock-down the 4K-bit Secured OTP area. Once the LDSO bit is
set to "1", the Secured OTP area cannot be updated any more.
The sequence of issuing WRSCUR instruction is: CS# goes low→
sending WRSCUR instruction → CS# goes high.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR
instruction, the LDSO bit may be set to "1" for customer lock-down
purpose. However, once the bit is set to "1" (lock-down), the
LDSO bit and the 4K-bit Secured OTP area cannot be updated
any more. While it is in 4K-bit secured OTP mode, main array
access is not allowed.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
Table 9. Security Register Definition
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
WPSEL
E_FAIL
P_FAIL
Reserved ESB
PSB
LDSO
Secured OTP
indicator bit
(Erase Suspend bit) (Program
Suspend bit)
0=Program is
(indicate if
lock-down)
0 = not
0=normal
mode
WP 0=normal
0=normal
-
0=Erase is not
suspended
1= Erase
0 = non-factory
lock
Erase succeed Program succeed
not suspended lock-down
1=individual
1=individual
1=indicate
Program
1= Program
suspended
(default=0)
1 = lock-down
1 = factory lock
mode (default=0) Erase failed
(default=0)
failed
suspended
(default=0)
(cannot
(default=0)
program/ erase
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bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
OTP)
Non-volatile
(OTP)
bit Volatile bit
Volatile bit
Volatile bit Volatile bit
Volatile bit
Non-volatile bit Non-volatile bit
(OTP) (OTP)
9.32. Write Protection Selection (WPSEL)
There are two write protection methods provided on this device, (1)
Block Lock (BP) protection mode (2) Advance Sector protection
mode. If WPSEL=0, flash is under BP protection mode. If
WPSEL=1, flash is under Advance Sector protection mode. The
default value of WPSEL is “0”. WPSEL command can be used to
set WPSEL=1. Please note that WPSEL is an OTP bit. Once
WPSEL is set to 1, there is no chance to recovery WPSEL
back to “0”. If the flash is put on BP mode, the Advance Sector
protection mode is disabled. Contrarily, if flash is on the Advance
Sector protection mode, the BP mode is disabled.
register will be set. It will activate WRLR, RDLR, WRPASS,
RDPASS, PASSULK, WRSPB, ESSPB, SPBLK, RDSPBLK,
WRDPB, RDDPB, GBLK, GBULK etc instructions to conduct block
lock protection and replace the original Software Protect Mode
(SPM) use (BP3~BP0) indicated block methods. Under the
Advance Sector protection mode (WPSEL=1), hardware protection
is performed by driving WP#=0.
Once WP#=0 all array
blocks/sectors are protected regardless of the contents of SPB or
DPB lock bits.
The sequence of issuing WPSEL instruction is: CS# goes low →
sending WPSEL instruction to enter the individual block protect
mode → CS# goes high.
Every time after the system is powered-on, and the Security
Register bit 7 is checked to be WPSEL=1, all the blocks or
sectors will be write protected by Dynamic Protected Bit (DPB)
in default. User may only unlock the blocks or sectors via
GBULK instruction. Program or erase functions can only be
operated after the Unlock instruction is conducted.
Write Protection Selection
When WPSEL = 0: Block Lock (BP) protection mode,
Array is protected by BP3~BP0 and BP bits are protected by
“SRWD=1 and WP#=0”, where SRWD is bit 7 of status register
that can be set by WRSR command.
When WPSEL =1: Advance Sector protection mode,
Blocks are individually protected by their own SPB or DPB lock
bits which are set to “1” after power up. When the system
accepts and executes WPSEL instruction, the bit 7 in security
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Figure 57. WPSEL Flow
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9.33. Advanced Sector Protection
There are two ways to implement software Advanced Sector
Protection on this device: Password method or Solid method.
Through these two protection methods, user can disable or enable
the programming or erasing operation to any individual sector or
all sectors.
sectors is protected from programming or erasing operation when
the bit is set.
The figure below helps describing an overview of these methods.
The device is default to the Solid mode when shipped from factory.
The detail algorithm of advance sector protection is shown as
follows:
There is a non-volatile (SPB) and volatile (DPB) protection bit
related to the single sector in main flash array. Each of the
Figure 58. Advanced Sector Protection Overview
9.34. Lock Register
User can choose favorite sector protecting method via setting Lock
Register bits 1 and 2. Lock Register is a 16- bit one-time
programmable register. Once bit 1 or bit2 has been programming
(set to "0"), they will be locked in that mode and the others will be
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disabled permanently. bit1 and bit2 can not be programmed at the
same time, otherwise the device will abort the operation. If user
selects Password Protection mode, the password setting is
required. User can set password by issuing password program
command.
Lock Register
Bit 15-3
Reserved
x
Bit 2
Bit 1
Bit0
Password Protection Mode Lock Bit
0=Password Protection Mode Enable
1= Password Protection Mode not enable (Default =1)
OTP
Solid Protection Mode Lock Bit
0=Solid Protection Mode Enable
1= Solid Protection Mode not enable (Default =1)
OTP
Reserved
x
OTP
OTP
Notes:
1. While bit2 or bit1 has been "0" status, other bit can't be changed any more. If set lock register program mode, program fail will be set to "1".
2. While bit2 and bit 1 is "1" status, other bits can be programed, program fail will be set to "1".
Figure 59. Read Lock Register (RDLR) Sequence
Figure 60. Write Lock Register (WRLR) Sequence (SPI Mode)
9.35. SPB Lock Bit (SPBLB)
The Solid Protection Bit Lock Bit (SPBLB) is assigned to control all
SPB status. It is a unique and volatile.
sequence requested to unlocks this bit. To clear the SPB lock bit,
just take the device through a reset or a power-up cycle. When
under Password Protected Mode, in order to prevent modified, the
SPB Lock Bit must be set after all SPBs are setting the desired
status.
The default status of this register is determined by Lock Register
bit 1 and bit 2 status. Refer to "SPB Lock Register" for more SPB
Lock information.
When under Solid Protect Mode, there is no software command
SPB Lock Register
Bit
Description
Bit Status
00h= SPB bit protected Solid Protected Mode=FFh
FFh=SPB bit unprotected Password Protected Mode=00h
Default
Type
7-0
SPBLK (Lock SPB Bit)
Volatile
Figure 61. SPB Lock Bit Set (SPBLK) Sequence
Figure 62. Read SPB Lock Register (RDSPBLK) Sequence
9.36. Solid Protection Bits
The Solid write Protection bit (SPB) is a nonvolatile bit with the
same endurances as the Flash memory. It is assigned to each
preventing any program or erase operation on this sector. The
SPB bits are set individually by SPB program command.
However, it cannot be cleared individually. Issuing the All SPB
Erase command will erase all SPB in the same time.
sector individually.
The SPB is Preprogramming, and its
verification prior to erasure are managed by the device, so system
monitoring is not necessary.
If one of the protected sector need to be unprotected
(corresponding SPB set to “0”), a few more steps are required.
When a SPB is set to “1”, the associated sector is protected,
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First, the SPB lock bit must be cleared by PASSWD unlock
command if lock register bit2 is set to "0" or by a power-on cycle or
hardware reset if lock register bit1 is set to "0". The SPBs can
then be changed to reflect the desired settings. Setting the SPB
Lock Bit once again locks the SPBs, and the device operates
normally again. To verify the programming state of the SPB for a
given sector, issuing a SPB Read Command to the device is
required.
Note:
1. Once SPB Lock Bit is set, its Program or erase command will not be
executed and times-out without programming or erasing the SPB.
SPB Register (SPBR)
Bit
Description
Bit Status
Default
Type
7 to 0
SPB (Solid protected Bit)
00h= SPB for the sector address unprotected
FFh= SPB for the sector address protected
00h
Non-volatile
Figure 63. Read SPB Status (RDSPB) Sequence
Figure 65. SPB Program (WRSPB) Sequence
Note: One dummy byte follow 3-byte address.
Note: One dummy byte follow 3-byte address.
Figure 64. SPB Erase (ESSPB) Sequence
9.37. Dynamic Write Protection Bits
The Dynamic Protection allows the software application to easily
Program command, then placing each sector in the protected or
unprotected state separately. After the DPB state is set to "0", the
sector may be modified depending on the SPB state of that sector.
The DPBs are protected (FFh) upon power up or reset. Program
or erase function can only be operated after the unlock instruction
is conducted.
protect sectors against inadvertent change.
However, the
protection can be easily disabled when changes are necessary.
All Dynamic Protection bits (DPB) are volatile and assigned to
each sector. They can be modified individually. DPBs provide
the protection scheme only for unprotected sectors that have their
SPBs cleared. To modify the DPB status by issuing the DPB
DPB Register (DPBR)
Bit
Description
Bit Status
Default
Type
7 to 0
DPB (Dynamic protected Bit) 00h=DPB for the sector address unprotected
FFh=DPB for the sector address protected
FFh
Volatile
Figure 66. Read DPB Register (RDDPB) Sequence
Figure 67. Write DPB Register (WRDPB) Sequence
Note: One dummy byte follow 3-byte address.
Note: One dummy byte follow 3-byte address.
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9.38. Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed.
low → send GBLK/GBULK (7Eh/98h) instruction →CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
The GBLK/GBULK instruction is
a chip-based protected or
unprotected operation. It can enable or disable all DPB.
The WREN (Write Enable) instruction is required before issuing
GBLK/GBULK instruction.
The CS# must go high exactly at the byte boundary, otherwise, the
instruction will be rejected and not be executed.
The sequence of issuing GBLK/GBULK instruction is: CS# goes
Sector Protection States Summary Table
Protection Status
Sector State
DPB bit
Unprotect
Unprotect
Unprotect
Unprotect
Protect
SPB bit
Unprotect
Unprotect
Protect
SPB Lock bit
lock
Unprotect – SPB is unchangeable
Unprotect – SPB is changeable
Protect – SPB is unchangeable
Protect – SPB is changeable
Protect – SPB is unchangeable
Protect – SPB is changeable
Protect – SPB is unchangeable
Protect – SPB is changeable
un-lock
lock
Protect
un-lock
lock
Unprotect
Unprotect
Protect
Protect
un-lock
lock
Protect
Protect
Protect
un-lock
9.39. Password Protection Mode
The security level of Password Protection Method is higher than
the Solid protection mode. The 64 bit password is requested
before modify SPB lock bit status. When device is under
password protection mode, the SPB lock bit is set “0”, after a
power-up cycle or Reset Command.
special address is required for programming the password. The
password is no longer readable after the Password Protection
mode is selected by programming Lock register bit 2 to "0".
Once sector under protected status, device will ignores the
program/erase command, enable status polling and returns to read
mode without contents change. The DPB, SPB and SPB lock bit
status of each sector can be verified by issuing DPB, SPB and
SPB Lock bit read commands.
A correct password is required for password Unlock command, to
unlock the SPB lock bit. Await 2us is necessary to unlocked the
device after valid password is given. After that, the SPB bits are
allows to be changed. The Password Unlock command are
issued slower than 2us every time, to prevent hacker from trying
all the 64-bit password combinations.
The unlock operation may fail if the password provided by
password unlock command does not match the previously
entered password.
It causes the same result when a
To place the device in password protection mode, a few more
programming operation is performed on a protected sector. The
P_ERR bit is set to 1 and the WIP Bit remains set.
steps are required.
First, prior to entering the password
protection mode, it is necessary to set a 64-bit password to verify it.
Password verification is only allowed during the password
programming operation. Second, the password protection mode
is then activated by programming the Password Protection Mode
Lock Bit to”0”. This operation is not reversible. Once the bit is
programmed, it cannot be erased, and the device remains
permanently in password protection mode, and the 64-bit
password can neither be retrieved nor reprogrammed. Moreover,
all commands to the address where the password is stored are
disabled.
It is not allowed to execute the Password Unlock command
faster than every 100us ± 20us. The reason behind it is to
make it impossible to hack into the system by running through
all the combinations of a set of 64-bit password (58 million
years). To verify if the device has completed the password
unlock command and is available to process a new password
command, the Read Status Register command is needed to
read the WIP bit. When a valid password is provided the
password unlock command does not insert the 100us delay
before returning the WIP bit to zero.
The password is all “1”s when shipped from the factory, it is only
capable of programming "0"s under password program command.
All 64-bit password combinations are valid as a password. No
It is not feasible to set the SPB Lock bit if the password is
missing after the Password Mode is selected.
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Password Register (PASS)
Bits Field Name
63 to 0 PWD
Function
Type
Default State
Description
Hidden Password
OTP
FFFFFFFFFFFFFFFFh
Non-volatile OTP storage of 64 bit password. The
password is no longer readable after the password
protection mode is selected by programming Lock
register bit 2 to zero.
Figure 68. Read Password Register (RDPASS) Sequence
being erase suspended is invalid.
After erase suspend, WEL bit will be clear, only read related,
resume and reset command can be accepted. (including: 03h, 0Bh,
3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h,
ABh, 90h, B1h, C1h, B0h, 30h, 66h, 99h, 00h, 35h, F5h, 15h, 2Dh,
27h, A7h, E2h, E0h, 16h)
If the system issues an Erase Suspend command after the sector
erase operation has already begun, the device will not enter
Erase-Suspended mode until 20us time has elapsed.
Figure 69. Write Password Register (WRPASS) Sequence
Figure 70. Password Unlock (PASSULK) Sequence
9.40. Program/Erase Suspend/Resume
ESB (Erase Suspend Bit) indicates the status of Erase suspend
operation.
When issue a suspend command during erase
operation ESB=1, when erase operation resumes, ESB will be
reset to "0".
Figure 71. Suspend to Read Latency
Figure 72. Resume to Read Latency
Figure 73. Resume to Suspend Latency
9.42. Write-Resume
The device allow the interruption of Sector-Erase, Block-Erase or
Page-Program operations and conduct other operations.
After issue suspend command, the system can determine if the
device has entered the Erase-Suspended mode through Bit2 (PSB)
and Bit3 (ESB) of security register. (please refer to "Table 9.
Security Register Definition")
The latency time of erase operation :
The Write operation is being resumed when Write-Resume
instruction issued. ESB or PSB (suspend status bit) in Status
register will be changed back to “0”
Suspend to suspend ready timing: 20us.
Resume to another suspend timing: 1ms.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
The operation of Write-Resume is as follows: CS# drives low →
send write resume command cycle (30H) → drive CS# high. By
polling Busy Bit in status register, the internal write operation
status could be checked to be completed or not. The user may
also wait the time lag of TSE, TBE, TPP for Sector-erase,
Block-erase or Page-programming. WREN (command "06" is not
required to issue before resume. Resume to another suspend
operation requires latency time of 1ms.
9.41. Erase Suspend
Erase suspend allow the interruption of all erase operations.
After the device has entered Erase-Suspended mode, the system
can read any sector(s) or Block(s) except those being erased by
the suspended erase operation. Reading the sector or Block
Please note that, if "performance enhance mode" is executed
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during suspend operation, the device can not be resume. To
restart the write command, disable the "performance enhance
mode" is required. After the "performance enhance mode" is
disable, the write-resume command is effective.
Figure 76. Reset Sequence (QPI mode)
9.43. No Operation (NOP)
9.45. Read SFDP Mode (RDSFDP)
The No Operation command only cancels
a Reset Enable
The Serial Flash Discoverable Parameter (SFDP) standard
provides a consistent method of describing the functional and
feature capabilities of serial flash devices in a standard set of
command. NOP has no impact on any other command.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
internal parameter tables.
These parameter tables can be
interrogated by host system software to enable adjustments
needed to accommodate divergent features from multiple vendors.
The concept is similar to the one found in the Introduction of
JEDEC Standard, JESD68 on CFI.
9.44. Software Reset (Reset-Enable (RSTEN) and
Reset (RST))
The Reset operation is used as a system (software) reset that puts
the device in normal operating Ready mode. This operation
consists of two commands: Reset-Enable (RSTEN) and Reset
(RST).
The sequence of issuing RDSFDP instruction is CS# goes
low→send RDSFDP instruction (5Ah)→send 3 address bytes on
SI pin→send 1 dummy byte on SI pin→read SFDP code on
SO→to end RDSFDP operation can use CS# to high at any time
during data out.
To reset the device the host drives CS# low, sends the
Reset-Enable command (66H), and drives CS# high. Next, the
host drives CS# low again, sends the Reset command (99H), and
drives CS# high.
SFDP is a JEDEC Standard, JESD216.
Figure 77. Read Serial Flash Discoverable Parameter (RDSFDP)
Sequence
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept
by this instruction. The SIO[3:1] are don't care when during SPI
mode.
The Reset operation requires the Reset-Enable command followed
by the Reset command. Any command other than the Reset
command after the Reset-Enable command will disable the
Reset-Enable.
A successful command execution will reset the device to SPI
stand-by read mode, which are their respective default states.
A
device reset during an active Program or Erase operation aborts
the operation, which can cause the data of the targeted address
range to be corrupted or lost. Depending on the prior operation,
the reset timing may vary. Recovery from a Write operation
requires more latency time than recovery from other operations.
Figure 74. Software Reset Recovery
Note: Refer to "Table 13. Reset Timing" for tRHSL data.
Figure 75. Reset Sequence (SPI mode)
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Table 10. Signature and Parameter Identification Data Values
note1
Description
Comment
Add (h) (Byte)
DW Add (Bit) Data (h/b)
Data (h)
53h
SFDP Signature
Fixed: 50444653h
00h
01h
02h
03h
04h
07:00
15:08
23:16
31:24
07:00
53h
46h
44h
50h
00h
46h
44h
50h
SFDP Minor Revision Start from 00h
00h
Number
SFDP Major Revision Start from 01h
Number
05h
06h
15:08
23:16
01h
01h
01h
01h
Number of Parameter This number is 0-based. Therefore,
0
Headers
indicates 1 parameter header.
Unused
07h
08h
09h
31:24
07:00
15:08
FFh
00h
00h
FFh
00h
00h
ID number (JEDEC)
00h: it indicates a JEDEC specified header.
Parameter Table Minor Start from 00h
Revision Number
Parameter Table Major Start from 01h
Revision Number
0Ah
0Bh
23:16
31:24
01h
09h
01h
09h
Parameter
Table How many DWORDs in the Parameter table
Length (in double word)
Parameter
Table First address of JEDEC Flash Parameter
0Ch
0Dh
0Eh
0Fh
10h
07:00
15:08
23:16
31:24
07:00
30h
00h
00h
FFh
C2h
30h
00h
00h
FFh
C2h
Pointer (PTP)
table
Unused
ID
number it indicates manufacturer ID
(manufacturer ID)
Parameter Table Minor Start from 00h
Revision Number
11h
12h
13h
15:08
23:16
31:24
00h
01h
04h
00h
01h
04h
Parameter Table Major Start from 01h
Revision Number
Parameter
Table How many DWORDs in the Parameter table
Length (in double word)
Parameter
Table First address of Flash Parameter table
14h
15h
16h
17h
07:00
15:08
23:16
31:24
60h
00h
00h
FFh
60h
00h
00h
FFh
Pointer (PTP)
Unused
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Table 11. Parameter Table (0): JEDEC Flash Parameter Tables
note1
Description
Comment
Add (h) (Byte) DW Add (Bit) Data (h/b)
Data (h)
Block/Sector Erase sizes
00: Reserved, 01: 4KB erase, 10:
Reserved, 11: not support 4KB erase
0: 1Byte, 1: 64Byte or larger
01:00
02
01b
1b
Write Granularity
Write Enable Instruction 0: not required
Required for Writing to 1: required 00h to be written to the
03
0b
Volatile Status Registers
status register
30h
E5h
Write Enable Opcode Select 0: use 50h opcode,
for Writing to Volatile Status 1: use 06h opcode
Registers
Unused
Note: If target flash status register is
04
0b
nonvolatile, then bits 3 and 4 must be
set to 00b.
Contains 111b and can never be
changed
07:05
111b
4KB Erase Opcode
31h
32h
15:08
16
20h
1b
20h
F1h
FFh
(1-1-2) Fast Read (Note2)
0=not support 1=support
Address Bytes Number used 00: 3Byte only, 01: 3 or 4Byte, 10: 4Byte
in addressing flash array only, 11: Reserved
18:17
19
00b
0b
Double Transfer Rate (DTR) 0=not support 1=support
Clocking
(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
20
21
1b
1b
22
1b
23
1b
Unused
33h
31:24
31:00
FFh
Flash Memory Density
37h:34h
07FF FFFFh
(1-4-4) Fast Read Number of 0 0000b: Wait states (Dummy Clocks)
not support
04:00
0 0100b
Wait states (Note3)
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
44h
EBh
08h
6Bh
08h
3Bh
04h
BBh
(1-4-4) Fast Read Number of 000b: Mode Bits not support
Mode Bits (Note4)
07:05
15:08
20:16
010b
EBh
(1-4-4) Fast Read Opcode
(1-1-4) Fast Read Number of 0 0000b: Wait states (Dummy Clocks)
0 1000b
Wait states
not support
(1-1-4) Fast Read Number of 000b: Mode Bits not support
Mode Bits
23:21
31:24
04:00
000b
6Bh
(1-1-4) Fast Read Opcode
(1-1-2) Fast Read Number of 0 0000b: Wait states (Dummy Clocks)
0 1000b
Wait states
not supported
(1-1-2) Fast Read Number of 000b: Mode Bits not supported
Mode Bits
07:05
15:08
20:16
000b
3Bh
(1-1-2) Fast Read Opcode
(1-2-2) Fast Read Number of 0 0000b: Wait states (Dummy Clocks)
0 0100b
Wait states
not supported
(1-2-2) Fast Read Number of 000b: Mode Bits not supported
23:21
31:24
000b
BBh
Mode Bits
(1-2-2) Fast Read Opcode
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note1
Description
(2-2-2) Fast Read
Unused
Comment
Add (h) (Byte) DW Add (Bit) Data (h/b)
Data (h)
0=not support 1=support
00
0b
111b
1b
03:01
04
40h
FEh
(4-4-4) Fast Read
Unused
0=not support 1=support
07:05
31:08
15:00
111b
FFh
FFh
Unused
43h:41h
45h:44h
FFh
FFh
Unused
(2-2-2) Fast Read Number of 0 0000b: Wait states (Dummy Clocks)
Wait states not supported
20:16
23:21
0 0000b
000b
46h
00h
(2-2-2) Fast Read Number of 000b: Mode Bits not supported
Mode Bits
(2-2-2) Fast Read Opcode
47h
31:24
15:00
FFh
FFh
FFh
FFh
Unused
49h:48h
(4-4-4) Fast Read Number of 0 0000b: Wait states (Dummy Clocks)
20:16
0 0100b
Wait states
not supported
4Ah
44h
(4-4-4) Fast Read Number of 000b: Mode Bits not supported
23:21
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
010b
EBh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
Mode Bits
(4-4-4) Fast Read Opcode
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
EBh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
(Note5)
Sector Type 1 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 4 erase Opcode
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Table 12. Parameter Table (1): Flash Parameter Tables
Description Comment
Vcc Supply Maximum 2000h=2.000V
Add (h) (Byte) DW Add (Bit)
Data (h/b) note1
Data (h)
07:00
61h:60h
00h
36h
Voltage
2700h=2.700V
3600h=3.600V
00h 36h
15:08
Vcc Supply Minimum 1650h=1.650V
Voltage
2250h=2.250V
23:16
63h:62h
00h
27h
00h 27h
2350h=2.350V
31:24
2700h=2.700V
H/W Reset# pin
H/W Hold# pin
0=not support 1=support
0=not support 1=support
0=not support 1=support
0=not support 1=support
Reset Enable (66h) should be issued
before Reset Opcode
0=not support 1=support
00
01
02
03
1b
0b
1b
1b
Deep Power Down Mode
S/W Reset
S/W Reset Opcode
11:04
1001 1001b (99h)
1b
65h:64h
F99Dh
Program
12
Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
13
14
15
1b
1b
1b
Wrap-Around Read mode 0=not support 1=support
Wrap-Around Read mode
66h
67h
23:16
C0h
C0h
Opcode
Wrap-Around Read data 08h:support 8B wrap-around read
length
16h:8B&16B
31:24
64h
64h
32h:8B&16B&32B
64h:8B&16B&32B&64B
0=not support 1=support
Individual block lock
00
01
1b
0b
CB85h
Individual block lock bit 0=Volatile 1=Nonvolatile
(Volatile/Nonvolatile)
Individual
Opcode
block
lock
09:02
10
1110 0001b (E1h)
0b
Individual
block
lock 0=protect 1=unprotect
Volatile protect bit default
protect status
Secured OTP
Read Lock
6Bh:68h
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
Permanent Lock
Unused
13
0b
15:14
31:16
[31:00]
11b
FFh
FFh
Unused
FFh
FFh
Unused
6Fh:6Ch
Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). At the present time,
the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2), and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller if they are specified. (eg,read performance
enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: All unused and undefined area data is blank FFh.
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GPR25L12805F
10. RESET
Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at the following states:
- Standby mode
- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.
- 3-byte address mode
If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data could be lost. During
the resetting cycle, the SO data becomes high impedance and the current will be reduced to minimum.
Figure 78. RESET Timing
Table 13. Reset Timing
Symbol Alt.
tRLRH
Parameter
Min.
10
Typ.
Max.
Unit
us
Reset Pulse Width
Reset Setup Time
Reset Hold Time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tRS
15
ns
tRH
15
ns
tRHSL
Reset Recovery Time (During instruction decoding) (Note 2)
30
us
Reset Recovery Time (For Read operation)
30
us
Reset Recovery Time (For Program operation)
300
12
us
Reset Recovery Time (For SE/4KB Sector Erase operation)
Reset Recovery Time (For BE64K/32KB Block Erase operation)
Reset Recovery Time (For Chip Erase operation)
Reset Recovery Time (for WRSR operation)
ms
ms
ms
ms
25
100
tW(Note 1)
Notes:
1. See "Table 17. AC CHARACTERISTICS" for tSE/tBE (32KB)/tW data.
2. Reset Recovery Time (During instruction decoding) is for Hardware Reset only.
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11. POWER-ON STATE
The device is at below states when power-up:
- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state.
When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device has no response to any
command.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read,
write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
Please refer to the "Figure 85. Power-up Timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any command. The data corruption might
occur during the stage while a write, program, erase cycle is in progress.
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12. ELECTRICAL SPECIFICATIONS
12.1. Absolute Maximum Ratings
Rating
Value
Ambient Operating Temperature
Storage Temperature
Industrial grade
-40°C to 85°C
-65°C to 150°C
-0.5V to Vcc+0.5V
-0.5V to Vcc+0.5V
-0.5V to Vcc+0.5V
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and
functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vcc to +2.0V or to -2.0V for periods up to 20ns.
4. All input and output pins may overshoot to VCC+0.2V.
Figure 79. Maximum Negative Overshoot Waveform
Figure 80. Maximum Positive Overshoot Waveform
12.2. Capacitance
TA = 25°C, f = 1.0 MHz
Symbol
CIN
Parameter
Min.
Typ.
Max.
Unit
pF
Conditions
VIN = 0V
Input Capacitance
Output Capacitance
-
-
-
-
6
8
COUT
pF
VOUT = 0V
Figure 81. Input test waveforms and measurement level
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GPR25L12805F
Figure 82. Output loading
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GPR25L12805F
12.3. Table 16. DC CHARACTERISTICS
(Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V)
Symbol
Parameter
Notes
Min.
Typ.
Max.
Units
Test Conditions
VCC = VCC Max,
VIN = VCC or GND
VCC = VCC Max,
VOUT = VCC or GND
VIN = VCC or GND,
CS# = VCC
ILI
Input Load Current
1
-
-
±2
uA
ILO
Output Leakage Current
VCC Standby Current
1
1
-
-
-
-
-
±2
100
20
uA
uA
uA
ISB1
ISB2
30
5
VIN = VCC or GND,
CS# = VCC
Deep Power-down Current
f=104MHz, (4 x I/O read)
SCLK=0.1VCC/0.9VCC,
SO=Open
20
15
mA
mA
ICC1
VCC Read
1
-
-
f=84MHz,
SCLK=0.1VCC/0.9VCC,
SO=Open
Program in Progress,
CS# = VCC
ICC2
ICC3
ICC4
ICC5
VCC Program Current (PP)
1
-
-
-
-
-
20
-
25
20
25
25
mA
mA
mA
mA
VCC Write Status Register (WRSR)
Current
Program status register in
progress, CS#=VCC
VCC Sector/Block (32K, 64K) Erase
Current (SE/BE/BE32K)
Erase
in
Progress,
1
1
20
20
CS#=VCC
Erase
in
Progress,
VCC Chip Erase Current (CE)
CS#=VCC
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-
-
-
-
-0.5
0.7VCC
-
-
-
-
-
0.8VCC
V
V
V
V
VIH
VOL
VCC+0.4
0.2
-
IOL = 100uA
IOH = -100uA
VOH
VCC-0.2
Notes:
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
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GPR25L12805F
12.4. Table 17. AC CHARACTERISTICS
(Temperature = -40°C to 85°C, VCC = 2.7V ~ 3.6V)
Symbol
fSCLK
Alt.
fC
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for all commands (except Read)
Clock Frequency for READ instructions
Clock Frequency for 2READ instructions
Clock Frequency for 4READ instructions
D.C.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
133
MHz
MHz
MHz
MHz
ns
fRSCLK
fTSCLK
fR
-
-
50
fT
84(7)
fQ
-
84(7)
tCH(1)
tCL(1)
tCLH Clock High Time
Others (fSCLK)
3.3
9
-
-
Normal Read (fRSCLK)
Others (fSCLK)
ns
tCLL Clock Low Time
3.3
9
-
ns
Normal Read (fRSCLK)
-
ns
tCLCH(2)
tCHCL(2)
tSLCH
Clock Rise Time (3) (peak to peak)
0.1
0.1
5
-
V/ns
V/ns
ns
Clock Fall Time (3) (peak to peak)
tCSS CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
tDSU Data In Setup Time
-
-
tCHSL
7
-
ns
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL(3)
2
-
ns
tDH Data In Hold Time
3
-
ns
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
5
-
ns
5
-
ns
tCSH CS# Deselect Time
Read
7
-
ns
Write/Erase/Program
30
-
-
ns
tSHQZ(2)
tDIS Output Disable Time
8
8
6
-
ns
tCLQV
tV
Clock Low to Output Valid
Loading: 30pF/15pF
Loading: 30pF
Loading: 15pF
-
ns
-
ns
tCLQX
tWHSL
tSHWL
tDP(2)
tRES1(2)
tRES2(2)
tW
tHO Output Hold Time
Write Protect Setup Time
Write Protect Hold Time
1
ns
20
100
-
-
ns
-
ns
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic Signature Read
CS# High to Standby Mode with Electronic Signature Read
Write Status/Configuration Register Cycle Time
Write Extended Address Register
10
30
30
40
-
us
-
us
-
-
us
-
-
40
ms
ns
tWREAW
tBP
-
Byte-Program
-
12
30
3
us
tPP
Page Program Cycle Time
-
0.6
ms
tPP(5)
Page Program Cycle Time (n bytes)
0.008+
(nx0.004) (6)
43
-
3
ms
tSE
Sector Erase Cycle Time
-
-
-
-
200
1000
2000
160
ms
ms
ms
s
tBE32
Block Erase (32KB) Cycle Time
Block Erase (64KB) Cycle Time
Chip Erase Cycle Time
190
tBE
340
tCE
72
Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values given for TA=25°C. Not 100% tested.
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. Test condition is shown as "Figure 81. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL" and "Figure 82. OUTPUT LOADING".
5. While programming consecutive bytes, Page Program instruction provides optimized timings by selecting to program the whole 256 bytes or only a few bytes
between 1~256 bytes.
6. “n”=how many bytes to program. In the formula, while n=1, byte program time=12us.
7. By default dummy cycle value. Please refer to the "Table 1. Read performance Comparison".
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GPR25L12805F
13. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in "Figure 83. AC Timing at Device Power-Up" and "Figure 84. Power-Down Sequence" are for the supply voltages
and the control signals at device power-up and power-down. If the timing in the figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be selected. The CS# can
be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 83. AC Timing at Device Power-Up
Symbol
Parameter
Notes
Min.
Max.
Unit
tVR
VCC Rise Time
1
20
500000
us/V
Notes:
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "Table 17. AC CHARACTERISTICS".
Figure 84. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
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Figure 85. Power-up Timing
Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.
Table 18. Power-Up Timing and VWI Threshold
Symbol
tVSL(1)
VWI(1)
Parameter
Min.
500
2.3
Max.
-
Unit
us
VCC(min) to CS# low (VCC Rise Time)
Command Inhibit Voltage
2.5
V
13.1. Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all
Status Register bits are 0).
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GPR25L12805F
14. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Min.
Typ. (1)
-
Max. (2)
Unit
ms
ms
s
Write Status Register Cycle Time
Sector Erase Time (4KB)
Block Erase Time (32KB)
Block Erase Time (64KB)
Chip Erase Time
-
-
-
-
-
40
200
1
43
0.19
0.34
72
2
s
160
s
Byte Program Time (via page program
command)
-
12
30
us
Page Program Time
-
-
0.6
3
-
ms
Erase/Program Cycle
100,000
cycles
Notes:
1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and all zero pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.
4. The maximum chip programming time is evaluated under the worst conditions of 0°C, VCC=3.3V, and 100K cycle with 90% confidence level.
15. DATA RETENTION
Parameter
Condition
Min.
Max.
Unit
Data retention
55˚C
20
-
years
16. LATCH-UP CHARACTERISTICS
Parameter
Min.
-1.0V
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
2 VCC max
VCC + 1.0V
+100mA
-1.0V
Current
-100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
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GPR25L12805F
17. ORDERING INFORMATION
Product Number
Package Type
SOP 8L 200mil-Halogen Free package
GPR25L12805F – QS13x
Note1: Code number is assigned for customer.
Note2: Package form number (x = 1 - 9, serial number).
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GPR25L12805F
18. PACKAGE INFORMATION
18.1. Title: Package Outline for SOP 8L 200MIL (Official name-209 mil)
18.1.1. Dimensions (Inch dimensions are derived from the original mm dimensions)
Symbol
Θ
A
A1
A2
b
C
D
E
E1
e
L
L1
S
Unit
Min.
Nom.
Max.
Min.
-
0.05
0.15
1.70
1.80
0.36
0.41
0.19
0.20
5.13
5.23
7.70
7.90
5.18
5.28
-
0.50
0.65
1.21
1.31
0.62
0.74
0
5
8
0
5
8
mm
-
1.27
2.16
0.20
1.91
0.51
0.25
5.33
8.10
5.38
-
0.80
1.41
0.88
-
-
0.002
0.006
0.008
0.067
0.071
0.075
0.014
0.016
0.020
0.007
0.008
0.010
0.202
0.206
0.210
0.303
0.311
0.319
0.204
0.208
0.212
-
0.050
-
0.020
0.026
0.031
0.048
0.052
0.056
0.024
0.029
0.035
inch
Nom.
Max.
0.085
REFERENCE
DWG. NO.
REVISION
ISSUE DATE
JEDEC
EIAJ
6110-1406
3
-
-
-
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GPR25L12805F
19. DISCLAIMER
The information appearing in this publication is believed to be accurate.
Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the
terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this
publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO
WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter
the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other
information in this publication are current before placing orders. Products described herein are intended for use in normal commercial
applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support
equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that
application circuits illustrated in this document are for reference purposes only.
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GPR25L12805F
20. REVISION HISTORY
Date
Revision#
1.1
Description
Modify 17. ORDERING INFORMATION.
Original
Page
Nov. 23, 217
Dec 26, 2012
1.0
58
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