GPR25L1603E-HS13x_技术文档

GPR25L1603E

16M-bit [x 1/x 2/x 4] CMOS MXSMIO^®

(Serial Multi I/O) Flash Memory

May 10, 2013

Version 1.0

GENERALPLUS TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by GENERALPLUS

TECHNOLOGY INC. is believed to be accurate and reliable. However, GENERALPLUS TECHNOLOGY INC. makes no warranty for any errors which may

appear in this document. Contact GENERALPLUS TECHNOLOGY INC. to obtain the latest version of device specifications before placing your order. No

responsibility is assumed by GENERALPLUS TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use.

In addition, GENERALPLUS products are not authorized for use as critical components in life support devices/systems or aviation devices/systems, where a

malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Generalplus.

GPR25L1603E

Table of Contents

PAGE

1. FEATURES.................................................................................................................................................................................................. 4

1.1. GENERAL .............................................................................................................................................................................................. 4

1.2. PERFORMANCE...................................................................................................................................................................................... 4

1.3. SOFTWARE FEATURES ........................................................................................................................................................................... 4

1.4. HARDWARE FEATURES .......................................................................................................................................................................... 4

2. GENERAL DESCRIPTION.......................................................................................................................................................................... 4

3. PIN CONFIGURATIONS ............................................................................................................................................................................. 5

3.1. 8-PIN SOP (200MIL) ............................................................................................................................................................................. 5

4. PIN DESCRIPTION...................................................................................................................................................................................... 5

5. BLOCK DIAGRAM ...................................................................................................................................................................................... 6

6. DATA PROTECTION................................................................................................................................................................................... 7

6.1. MEMORY ORGANIZATION........................................................................................................................................................................ 8

7. DEVICE OPERATION.................................................................................................................................................................................. 9

8. COMMAND DESCRIPTION ...................................................................................................................................................................... 10

8.1. WRITE ENABLE (WREN).......................................................................................................................................................................11

8.2. WRITE DISABLE (WRDI) .......................................................................................................................................................................11

8.3. READ IDENTIFICATION (RDID) ...............................................................................................................................................................11

8.4. READ STATUS REGISTER (RDSR) .........................................................................................................................................................11

8.5. WRITE STATUS REGISTER (WRSR)...................................................................................................................................................... 12

8.6. READ DATA BYTES (READ).................................................................................................................................................................. 13

8.7. READ DATA BYTES AT HIGHER SPEED (FAST_READ)........................................................................................................................... 13

8.8. 2 X I/O READ MODE (2READ).............................................................................................................................................................. 13

8.9. 4 X I/O READ MODE (4READ).............................................................................................................................................................. 13

8.10.SECTOR ERASE (SE)........................................................................................................................................................................... 13

8.11.BLOCK ERASE (BE) ............................................................................................................................................................................. 14

8.12.CHIP ERASE (CE)................................................................................................................................................................................ 14

8.13.PAGE PROGRAM (PP) .......................................................................................................................................................................... 14

8.14.4 X I/O PAGE PROGRAM (4PP)............................................................................................................................................................. 14

8.15.DEEP POWER-DOWN (DP) ................................................................................................................................................................... 15

8.16.RELEASE FROM DEEP POWER-DOWN (RDP), READ ELECTRONIC SIGNATURE (RES) ............................................................................. 15

8.17.READ ELECTRONIC MANUFACTURER ID & DEVICE ID (REMS), (REMS2), (REMS4) ............................................................................. 15

8.18.ENTER SECURED OTP (ENSO) ........................................................................................................................................................... 16

8.19.EXIT SECURED OTP (EXSO)............................................................................................................................................................... 16

8.20.READ SECURITY REGISTER (RDSCUR) ............................................................................................................................................... 16

8.21.WRITE SECURITY REGISTER (WRSCUR) ............................................................................................................................................. 16

9. POWER-ON STATE .................................................................................................................................................................................. 17

10.ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 18

10.1.ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 18

10.2.CAPACITANCE TA = 25℃, F = 1.0 MHZ ................................................................................................................................................ 18

10.3.DC CHARACTERISTICS (TEMPERATURE = -40° C TO 85° C FOR INDUSTRIAL GRADE, VCC = 2.7V ~ 3.6V)(TABLE9) ................................ 20

10.4.AC CHARACTERISTICS (TEMPERATURE = -40° C TO 85° C FOR INDUSTRIAL GRADE, VCC = 2.7V ~ 3.6V)(TABLE10) .............................. 21

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10.5.TIMING ANALYSIS ................................................................................................................................................................................. 22

10.6.INITIAL DELIVERY STATE ....................................................................................................................................................................... 32

11.OPERATING CONDITIONS ...................................................................................................................................................................... 33

11.1.AT DEVICE POWER-UP AND POWER-DOWN........................................................................................................................................... 33

12.ERASE AND PROGRAMMING PERFORMANCE.................................................................................................................................... 34

13.DATA RETENTION ................................................................................................................................................................................... 34

14.LATCH-UP CHARACTERISTICS ............................................................................................................................................................. 34

15.ORDERING INFORMATION ..................................................................................................................................................................... 35

16.PACKAGE INFORMATION....................................................................................................................................................................... 36

16.1.TITLE: PACKAGE OUTLINE FOR SOP 8L (200MIL)................................................................................................................................. 36

16.2.DIMENSIONS (INCH DIMENSIONS ARE DERIVED FROM THE ORIGINAL MM DIMENSIONS).............................................................................. 36

17.DISCLAIMER............................................................................................................................................................................................. 37

18.REVISION HISTORY................................................................................................................................................................................. 38

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16M-bit [x 1/x 2/x 4] CMOS MXSMIO®

(Serial Multi I/O) Flash Memory

1. FEATURES

1.1. General

- Additional 512-bit secured OTP for unique identifier

․Auto Erase and Auto Program Algorithm

- Automatically erases and verifies data at selected sector

- Automatically programs and verifies data at selected page by

an internal algorithm that automatically times the program pulse

widths (Any page to be programed should have page in the

erased state first)

․Serial Peripheral Interface compatible -- Mode 0 and Mode 3

․16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read

mode) structure or 4,194,304 x 4 bits (four I/O read mode)

structure

․512 Equal Sectors with 4K byte each

․Status Register Feature

- Any Sector can be erased individually

․Electronic Identification

․32 Equal Blocks with 64K byte each

- JEDEC 1-byte manufacturer ID and 2-byte device ID

- RES command for 1-byte Device ID

- Any Block can be erased individually

․Single Power Supply Operation

- Both REMS, REMS2 and REMS4 commands for 1-byte

manufacturer ID and 1-byte device ID

- 2.7 to 3.6 volt for read, erase, and program operations

․Latch-up protected to 100mA from -1V to Vcc +1V

1.4. Hardware Features

1.2. Performance

․SCLK Input

․High Performance

- Serial clock input

- Fast read

․SI/SIO0

- 1 I/O: 104MHz with 8 dummy cycles

- 2 I/O: 85MHz with 4 dummy cycles

- 4 I/O: 85MHz with 6 dummy cycles

- Fast access time: 104MHz serial clock

- Serial clock of four I/O read mode : 85MHz, which is equivalent

to 340MHz

- Serial Data Input or Serial Data Input/Output for 2 x I/O read

mode and 4 x I/O read mode

․SO/SIO1

- Serial Data Output or Serial Data Input/Output for 2 x I/O read

mode and 4 x I/O read mode

․WP#/SIO2

- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte

per page)

- Hardware write protection or serial data Input/Output for 4 x I/O

read mode

- Byte program time: 9us (typical)

- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ;

0.7s(typ.) /block (64K-byte per block); 14s(typ.) /chip

․Low Power Consumption

․NC/SIO3

- NC pin or serial data Input/Output for 4 x I/O read mode

․PACKAGE

- 8-pin SOP (200mil)

-

Low active read current: 25mA(max.) at 104MHz and

10mA(max.) at 33MHz

- Low active programming current: 20mA (max.)

- Low active erase current: 20mA (max.)

- Low standby current: 25uA (max.)

․Typical 100,000 erase/program cycles

․20 years data retention

2. GENERAL DESCRIPTION

The GPR25L1603E are 16,777,216 bit serial Flash memory, which

is configured as 2,097,152 x 8 internally. When it is in two or four

I/O read mode, the structure becomes 8,388,608 bits x 2 or

4,194,304 bits x 4. The GPR25L1603E feature a serial peripheral

interface and software protocol allowing operation on a simple

3-wire bus. The three bus signals are a clock input (SCLK), a

serial data input (SI), and a serial data output (SO). Serial access

to the device is enabled by CS# input.

1.3. Software Features

․Input Data Format

- 1-byte Command code

․Advanced Security Features

When it is in two I/O read mode, the SI pin and SO pin become

SIO0 pin and SIO1 pin for address/dummy bits input and data

output. When it is in four I/O read mode, the SI pin, SO pin, WP#

- Block lock protection

The BP0-BP3 status bit defines the size of the area to be

software protection against program and erase instructions

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pin and NC pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3

pin for address/dummy bits input and data output.

to indicate the status of the chip. The status read command can

be issued to detect completion status of a program or erase

operation via WIP bit.

The GPR25L1603E provides sequential read operation on whole

chip.

Advanced security features enhance the protection and security

functions, please see security features section for more details.

When the device is not in operation and CS# is high, it is put in

standby mode and draws less than 25uA (typical:1uA) DC current.

The GPR25L1603E utilizes proprietary memory cell, which reliably

stores memory contents even after 100,000 program and erase

cycles.

After program/erase command is issued, auto program/erase

algorithms which program/erase and verify the specified page or

sector/block locations will be executed. Program command is

executed on byte basis, or page (256 bytes) basis, and erase

command is executes on sector (4K-byte), or block (64K-byte), or

whole chip basis.

To provide user with ease of interface, a status register is included

Table 1. Additional Feature Comparison

Additional Protection and Security

Read Performance

Identifier

Features

Flexible Block 512-bit 2 I/O Read 4 I/O Read

RES

REMS

REMS2

REMS4

RDID

Protection

(BP0- BP3)

V

secured

OTP

V

(command: (command: (command: (command: (command:

Part Name

GPR25L1603E

AB hex)

90 hex)

C2 24 (hex) C2 24 (hex) C2 24 (hex)

(if ADD=0) (if ADD=0) (if ADD=0)

EF hex)

DF hex)

9F hex)

C2 24 15

(hex)

V

24 (hex)

3. PIN CONFIGURATIONS

3.1. 8-PIN SOP (200mil)

4. PIN DESCRIPTION

Symbol

CS#

Description

Chip Select

SI/SIO0

Serial Data Input (for 1 x I/O)/ Serial Data

Input & Output (for 2xI/O or 4xI/ O read mode)

Serial Data Output (for 1 x I/O)/ Serial Data

Input & Output (for 2xI/O or 4xI/ O read mode)

Clock Input

SO/SIO1

SCLK

WP#/SIO2

Write protection: connect to GND or Serial

Data Input & Output (for 4xI/O read mode)

NC pin (Not connect) or Serial Data Input &

Output (for 4xI/O read mode)

NC/SIO3

VCC

GND

+ 3.3V Power Supply

Ground

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5. BLOCK DIAGRAM

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6. DATA PROTECTION

During power transition, there may be some false system level

signals which result in inadvertent erasure or programming. The

device is designed to protect itself from these accidental write

cycles.

the (BP3, BP2, BP1, BP0) bits and SRWD bit. If the system goes

into four I/O read mode, the feature of HPM will be disabled.

Table 2. Protected Area Sizes

Status bit

Protect Level

16Mb

The state machine will be reset as standby mode automatically

during power up. In addition, the control register architecture of

the device constrains that the memory contents can only be

changed after specific command sequences have completed

successfully.

BP3 BP2 BP1 BP0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0 (none)

1 (1block, protected block 31th)

2 (2blocks, protected block 30th-31th)

3 (4blocks, protected block 28th-31th)

4 (8blocks, protected block 24th-31th)

5 (16blocks, protected block 16th-31th)

6 (32blocks, protected all)

In the following, there are several features to protect the system

from the accidental write cycles during VCC power-up and

power-down or from system noise.

• Valid command length checking: The command length will be

checked whether it is at byte base and completed on byte

boundary.

7 (32blocks, protected all)

8 (32blocks, protected all)

9 (32blocks, protected all)

• Write Enable (WREN) command: WREN command is required to

set the Write Enable Latch bit (WEL) before other command to

change data. The WEL bit will return to reset stage under

following situation:

10 (16blocks, protected block 0th-15th)

11 (24blocks, protected block 0th-23th)

12 (28blocks, protected block 0th-27th)

13 (30blocks, protected block 0th-29th)

14 (31blocks, protected block 0th-30th)

15 (32blocks, protected all)

- Power-up

- Write Disable (WRDI) command completion

- Write Status Register (WRSR) command completion

- Page Program (PP, 4PP) command completion

- Sector Erase (SE) command completion

II. Additional 512-bit secured OTP for unique identifier: to

provide 512-bit one-time program area for setting device unique

serial number - Which may be set by factory or system customer.

Please refer to table 3. 512-bit secured OTP definition.

- Security register bit 0 indicates whether the chip is locked by

factory or not.

- Block Erase (BE) command completion

- Chip Erase (CE) command completion

• Deep Power Down Mode: By entering deep power down mode,

the flash device also is under protected from writing all commands

except Release from deep power down mode command (RDP)

and Read Electronic Signature command (RES).

• Advanced Security Features: there are some protection and

security features which protect content from inadvertent write and

hostile access.

- To program the 512-bit secured OTP by entering 512-bit secured

OTP mode (with ENSO command), and going through normal

program procedure, and then exiting 512-bit secured OTP mode

by writing EXSO command.

- Customer may lock-down the customer lockable secured OTP by

writing WRSCUR(write security register) command to set customer

lock-down bit1 as "1". Please refer to table of "security register

definition" for security register bit definition and table of "512-bit

I. Block lock protection

- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0)

bits to allow part of memory to be protected as read only. The

protected area definition is shown as table of "Protected Area

Sizes", the protected areas are more flexible which may protect

various area by setting value of BP0-BP3 bits.

secured OTP definition" for address range definition.

Note: Once lock-down whatever by factory or customer, it cannot be

changed any more. While in 512-bit secured OTP mode, array access is

not allowed.

Please refer to table of "protected area sizes".

- The Hardware Protected Mode (HPM) use WP#/SIO2 to protect

Table 3. 512-bit Secured OTP Definition

Address range

xxxx00~xxxx0F

xxxx10~xxxx3F

Size

Standard Factory Lock

ESN (electrical serial number)

N/A

Customer Lock

128-bit

384-bit

Determined by customer

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6.1. Memory Organization

Table 4. Memory Organization

Block

Sector

511

:

Address Range

Block

Sector

255

:

Address Range

1FF000h

1FFFFFh

:

0FF000h

:

0FFFFFh

:

31

15

:

496

495

:

1F0000h

1EF000h

:

1F0FFFh

1EFFFFh

:

240

239

:

0F0000h

0EF000h

:

0F0FFFh

0EFFFFh

:

30

29

28

27

26

25

24

23

22

21

20

19

18

17

14

13

12

11

10

9

480

479

:

1E0000h

1DF000h

:

1E0FFFh

1DFFFFh

:

224

223

:

0E0000h

0DF000h

:

0E0FFFh

0DFFFFh

:

464

463

:

1D0000h

1CF000h

:

1D0FFFh

1CFFFFh

:

208

207

:

0D0000h

0CF000h

:

0D0FFFh

0CFFFFh

:

448

447

:

1C0000h

1BF000h

:

1C0FFFh

1BFFFFh

:

192

191

:

0C0000h

0BF000h

:

0C0FFFh

0BFFFFh

:

432

431

:

1B0000h

1AF000h

:

1B0FFFh

1AFFFFh

:

176

175

:

0B0000h

0AF000h

:

0B0FFFh

0AFFFFh

:

416

415

:

1A0000h

19F000h

:

1A0FFFh

19FFFFh

:

160

159

:

0A0000h

09F000h

:

0A0FFFh

09FFFFh

:

400

399

:

190000h

18F000h

:

190FFFh

18FFFFh

:

144

143

:

090000h

08F000h

:

090FFFh

08FFFFh

:

8

384

383

:

180000h

17F000h

:

180FFFh

17FFFFh

:

128

127

:

080000h

07F000h

:

080FFFh

07FFFFh

:

7

368

367

:

170000h

16F000h

:

170FFFh

16FFFFh

:

112

111

:

070000h

06F000h

:

070FFFh

06FFFFh

:

6

352

351

:

160000h

15F000h

:

160FFFh

15FFFFh

:

96

95

:

060000h

05F000h

:

060FFFh

05FFFFh

:

5

336

335

:

150000h

14F000h

:

150FFFh

14FFFFh

:

80

79

:

050000h

04F000h

:

050FFFh

04FFFFh

:

4

320

319

:

140000h

13F000h

:

140FFFh

13FFFFh

:

64

63

:

040000h

03F000h

:

040FFFh

03FFFFh

:

3

304

303

:

130000h

12F000h

:

130FFFh

12FFFFh

:

48

47

:

030000h

02F000h

:

030FFFh

02FFFFh

:

2

288

287

:

120000h

11F000h

:

120FFFh

11FFFFh

:

32

31

:

020000h

01F000h

:

020FFFh

01FFFFh

:

1

272

271

110000h

10F000h

110FFFh

10FFFFh

16

15

:

010000h

00F000h

:

010FFFh

00FFFFh

:

16

0

2

002000h

001000h

000000h

002FFFh

001FFFh

000FFFh

1

256

100000h

100FFFh

0

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7. DEVICE OPERATION

1. Before a command is issued, status register should be checked

to ensure device is ready for the intended operation.

2. When incorrect command is inputted to this LSI, this LSI

becomes standby mode and keeps the standby mode until next

CS# falling edge. In standby mode, all SO pins of this LSI

should be High-Z.

5. For the following instructions: RDID, RDSR, RDSCUR, READ,

FAST_READ, 2READ, 4READ, RES, REMS, REMS2, and

REMS4 the shifted-in instruction sequence is followed by a

data-out sequence. After any bit of data being shifted out, the

CS# can be high. For the following instructions: WREN, WRDI,

WRSR, SE, BE, CE, PP, 4PP, RDP, DP, ENSO, EXSO, and

WRSCUR, the CS# must go high exactly at the byte boundary;

otherwise, the instruction will be rejected and not executed.

6. During the progress of Write Status Register, Program, Erase

operation, to access the memory array is neglected and not

affect the current operation of Write Status Register, Program,

Erase.

3. When correct command is inputted to this LSI, this LSI becomes

active mode and keeps the active mode until next CS# rising

edge.

4. Input data is latched on the rising edge of Serial Clock(SCLK)

and data shifts out on the falling edge of SCLK. The difference

of Serial mode 0 and mode 3 is shown as Figure 1.

Figure1. Serial Modes Supported

Note:

CPOL indicates clock polarity of Serial master,

-CPOL=1 for SCLK high while idle,

-CPOL=0 for SCLK low while not transmitting.

CPHA indicates clock phase.

The combination of CPOL bit and CPHA bit decides which Serial mode is supported.

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8. COMMAND DESCRIPTION

Table 5. Command Set

Command WREN

WRDI

RDID

(read

RDSR (read WRSR (write READ

FAST READ 2READ (2 x 4READ (4 x

(byte)

(write

status

(read

data)

(fast

read I/O

read

enable)

disable)

identification) register)

register)

data)

command) command)

Note1

Note2

1st byte

2nd byte

06 (hex)

04 (hex)

9F (hex)

05 (hex)

01 (hex)

Values

03 (hex)

AD1

0B (hex)

BB (hex)

EB (hex)

AD1

ADD(2)

ADD(4) &

Dummy(4)

(A23-A16)

AD2

3rd byte

4th byte

AD2

ADD(2) &

Dummy(2)

(A15-A8)

AD3

(A7-A0)

5th byte

Action

Dummy

sets

the resets the outputs JEDEC to read out to write new n

bytes n bytes read n bytes

n bytes read

(WEL) write (WEL) write ID:

enable latch enable latch Manufacturer

1-byte the values values of the read out out until CS# read out

out by 4 x

of the status status register until CS# goes high

by

2

x

I/O I/O until CS#

CS# goes high

bit

ID

&

2-byte register

goes high

until

Device ID

goes high

Command 4PP

(quad SE

(sector BE

erase)

(block CE

erase)

(chip PP

(page DP

(Deep RDP (Release RES

(read

(byte)

page

erase)

program)

power down) from

power down)

AB (hex)

deep electronic ID)

program)

38 (hex)

AD1

1st byte

2nd byte

3rd byte

4th byte

Action

20 (hex)

D8 (hex)

AD1

60 or C7 (hex)

02 (hex)

AD1

B9 (hex)

AB (hex)

AD1

AD2

AD3

x

AD2

x

AD3

x

quad input to to erase the to erase the to erase whole to program the enters

deep release from to read out

program the selected

selected page sector

selected block chip

selected page power down deep

power 1-byte Device

mode down mode

ID

Command Release Read REMS (read REMS2 (read REMS4 (read ENSO (enter EXSO

(exit RDSCUR

WRSCUR

(byte)

Enhanced

electronic

ID for 2x I/O ID for 4x I/O secured OTP) secured OTP) (read security (write

manufacturer mode)

& device ID)

mode)

register)

security

register)

1st byte

2nd byte

3rd byte

4th byte

Action

FFh (hex)

90 (hex)

EF (hex)

DF (hex)

B1 (hex)

C1 (hex)

2B (hex)

2F (hex)

x

X

x

ADD ^{(Note 3)}

All

these output

the output

the to enter the to exit the to read value to

set

the

commands

Manufacturer Manufacturer Manufacturer 512-bit

512-bit

of

security lock-down bit

as "1" (once

lock-down,

FFh, 00h, AAh ID & Device ID ID & Device ID ID & Device ID secured OTP secured OTP register

or 55h will mode mode

escape the

cannot

be

performance

enhance

mode

update)

Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O.

Note 2: The count base is 4-bit for ADD(4) and Dummy(4) because of 4 x I/O.

Note 3: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.

Note 4: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode.

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8.1. Write Enable (WREN)

It is recommended to check the Write in Progress (WIP) bit

before sending a new instruction when a program, erase, or

write status register operation is in progress.

The Write Enable (WREN) instruction is for setting Write Enable

Latch (WEL) bit. For those instructions like PP, 4PP, SE, BE,

CE, and WRSR, which are intended to change the device

content, should be set every time after the WREN instruction

setting the WEL bit.

The sequence of issuing RDSR instruction is: CS# goes

low→sending RDSR instruction code→Status Register data out

on SO (see Figure 12)

The definition of the status register bits is as below:

The sequence of issuing WREN instruction is: CS# goes low→

sending WREN instruction code→CS# goes high. (see Figure 9)

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates

whether the device is busy in program/erase/write status

register progress. When WIP bit sets to 1, which means the

device is busy in program/erase/write status register progress.

When WIP bit sets to 0, which means the device is not in

progress of program/erase/write status register cycle.

8.2. Write Disable (WRDI)

The Write Disable (WRDI) instruction is for resetting Write

Enable Latch (WEL) bit.

The sequence of issuing WRDI instruction is: CS# goes

low→sending WRDI instruction code→CS# goes high. (see

Figure 10)

WEL bit. The Write Enable Latch (WEL) bit, a volatile bit,

indicates whether the device is set to internal write enable latch.

When WEL bit sets to 1, which means the internal write enable

latch is set, the device can accept program/ erase/write status

register instruction. When WEL bit sets to 0, which means no

internal write enable latch; the device will not accept

The WEL bit is reset by following situations:

- Power-up

- Write Disable (WRDI) instruction completion

- Write Status Register (WRSR) instruction completion

- Page Program (PP) instruction completion

- Quad Page Program (4PP) instruction completion

- Sector Erase (SE) instruction completion

- Block Erase (BE) instruction completion

- Chip Erase (CE) instruction completion

program/erase/write status register instruction.

The

program/erase command will be ignored if it is applied to a

protected memory area.

BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1,

BP0) bits, non-volatile bits, indicate the protected area(as

defined in table 2) of the device to against the program/erase

instruction without hardware protection mode being set. To

write the Block Protect (BP3, BP2, BP1, BP0) bits requires the

Write Status Register (WRSR) instruction to be executed.

Those bits define the protected area of the memory to against

Page Program (PP), Sector Erase (SE), Block Erase (BE) and

Chip Erase(CE) instructions (only if all Block Protect bits set to 0,

the CE instruction can be executed).

8.3. Read Identification (RDID)

The RDID instruction is for reading the manufacturer ID of

1-byte and followed by Device ID of 2-byte. The Manufacturer

ID is C2(hex), the memory type ID is 24(hex) as the first-byte

device ID, and the individual device ID of second-byte ID are

listed as table of "ID Definitions". (see table 7)

The sequence of issuing RDID instruction is: CS# goes

low→sending RDID instruction code→24-bits ID data out on

SO→ to end RDID operation can use CS# to high at any time

during data out. (see Figure 11.)

QE bit. The Quad Enable (QE) bit, non-volatile bit, performs

Quad when it is reset to "0" (factory default) to enable WP# or is

set to "1" to enable Quad SIO2 and SIO3.

SRWD bit. The Status Register Write Disable (SRWD) bit,

non-volatile bit, which is set to "0" (factory default). The SRWD

bit is operated together with Write Protection (WP#/SIO2) pin for

providing hardware protection mode. The hardware protection

mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low

stage. In the hardware protection mode, the Write Status

Register (WRSR) instruction is no longer accepted for execution

and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0)

are read only.

While Program/Erase operation is in progress, it will not decode

the RDID instruction, so there's no effect on the cycle of

program/erase operation which is currently in progress. When

CS# goes high, the device is at standby stage.

8.4. Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The

Read Status Register can be read at any time (even in

program/erase/write status register condition) and continuously.

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Status Register

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

SRWD (status

register write

protect)

QE

BP3

BP2

BP1

BP0

WEL

(write enable

latch)

WIP

(Quad Enable)

(level of

(write in

protected block) protected block) protected block) protected block)

progress bit)

1=write

1=status

1=Quad Enable

0=not Quad

Enable

1=write enable

0=not write

enable

(note 1)

register write

disable

operation

0=not in write

operation

volatile bit

Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit

volatile bit

Note 1: Please refer to the "Table 2. Protected Area Sizes".

8.5. Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status

Register Bits. Before sending WRSR instruction, the Write

Enable (WREN) instruction must be decoded and executed to set

the Write Enable Latch (WEL) bit in advance. The WRSR

instruction can change the value of Block Protect (BP3, BP2, BP1,

BP0) bits to define the protected area of memory (as shown in

table 2). The WRSR also can set or reset the Quad enable (QE)

bit and set or reset the Status Register Write Disable (SRWD) bit in

accordance with Write Protection (WP#/SIO2) pin signal, but has

no effect on bit1(WEL) and bit0 (WIP) of the status register. The

WRSR instruction cannot be executed once the Hardware

Protected Mode (HPM) is entered.

The sequence of issuing WRSR instruction is: CS# goes

low→sending WRSR instruction code→Status Register data on

SI→ CS# goes high. (see Figure 13)

The CS# must go high exactly at the byte boundary; otherwise, the

instruction will be rejected and not executed. The self-timed

Write Status Register cycle time (tW) is initiated as soon as Chip

Select (CS#) goes high. The Write in Progress (WIP) bit still can

be check out during the Write Status Register cycle is in progress.

The WIP sets 1 during the tW timing, and sets 0 when Write Status

Register Cycle is completed, and the Write Enable Latch (WEL) bit

is reset.

Table 6. Protection Modes

Mode

Software protection mode Status register can be written in (WEL WP#=1 and SRWD bit=0, or The protected area cannot be

(SPM) bit is set to "1") and the SRWD, WP#=0 and SRWD bit=0, or program or erase.

BP0-BP3, QE bits can be changed WP#=1 and SRWD=1

Hardware protection mode The SRWD, BP0-BP3, QE of status WP#=0, SRWD bit=1

Status register condition

WP# and SRWD bit status

Memory

The protected area cannot be

program or erase.

(HPM)

register bits cannot be changed

Note:

1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2.

As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).

Software Protected Mode (SPM):

- When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3, BP2, BP1,

BP0 and QE. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM).

- When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP3, BP2, BP1, BP0 and QE. The

protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM)

Note:

If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status

Register and not be executed.

Hardware Protected Mode (HPM):

- When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the

protected area is protected by software protected mode by BP3, BP2, BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification.

Note:

To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered. If the WP#/SIO2 pin is permanently

connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP3, BP2, BP1, BP0.

If the system goes into four I/O read mode, the feature of HPM will be disabled.

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8.6. Read Data Bytes (READ)

any time during data out (see Figure 16 for 2 x I/O Read Mode

Timing Waveform).

The read instruction is for reading data out. The address is

latched on rising edge of SCLK, and data shifts out on the falling

edge of SCLK at a maximum frequency fR. The first address can

be at any location. The address is automatically increased to the

next higher address after each byte data is shifted out, so the

whole memory can be read out at a single READ instruction. The

address counter rolls over to 0 when the highest address has been

reached.

While Program/Erase/Write Status Register cycle is in progress,

2READ instruction is rejected without any impact on the

Program/Erase/Write Status Register current cycle.

8.9. 4 x I/O Read Mode (4READ)

The 4READ instruction enable quad throughput of Serial Flash in

read mode. A Quad Enable (QE) bit of status Register must be

set to "1" before sending the 4READ instruction. The address is

latched on rising edge of SCLK, and data of every four bits

(interleave on 4 I/O pins) shift out on the falling edge of SCLK at a

maximum frequency fQ. The first address can be at any location.

The address is automatically increased to the next higher address

after each byte data is shifted out, so the whole memory can be

read out at a single 4READ instruction. The address counter rolls

over to 0 when the highest address has been reached. Once

writing 4READ instruction, the following address/dummy/data out

will perform as 4-bit instead of previous 1-bit.

The sequence of issuing READ instruction is: CS# goes low→

sending READ instruction code→ 3-byte address on SI→data out

on SO→to end READ operation can use CS# to high at any time

during data out. (see Figure 14)

8.7. Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The

address is latched on rising edge of SCLK, and data of each bit

shifts out on the falling edge of SCLK at a maximum frequency fC.

The first address can be at any location. The address is

automatically increased to the next higher address after each byte

data is shifted out, so the whole memory can be read out at a

single FAST_READ instruction. The address counter rolls over to

0 when the highest address has been reached.

The sequence of issuing 4READ instruction is: CS# goes low→

sending 4READ instruction→ 24-bit address interleave on SIO3,

SIO2, SIO1 & SIO0→ 6 dummy cycles→data out interleave on

SIO3, SIO2, SIO1 & SIO0→ to end 4READ operation can use CS#

to high at any time during data out (see Figure 17 for 4 x I/O Read

Mode Timing Waveform).

The sequence of issuing FAST_READ instruction is: CS# goes

low→sending FAST_READ instruction code→ 3-byte address on

SI→1-dummy byte address on SI→data out on SO→ to end

FAST_READ operation can use CS# to high at any time during

data out. (see Figure 15)

Another sequence of issuing 4 READ instruction especially useful

in random access is: CS# goes low→sending

4 READ

instruction→24-bit address interleave on SIO3, SIO2, SIO1 &

SIO0 →performance enhance toggling bit P[7:0]→ 4 dummy

cycles →data out interleave on SIO3, SIO2, SIO1 and SIO0 till

CS# goes high →CS# goes low (reduce 4 Read instruction)

→24-bit random access address (see Figure 18 for 4x I/O read

enhance performance mode timing waveform).

While Program/Erase/Write Status Register cycle is in progress,

FAST_READ instruction is rejected without any impact on the

Program/Erase/Write Status Register current cycle.

8.8. 2 x I/O Read Mode (2READ)

In the performance-enhancing mode (Note of Figure. 18), P[7:4]

must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh

can make this mode continue and reduce the next 4READ

instruction. Once P[7:4] is no longer toggling with P[3:0]; likewise

P[7:0]=FFh,00h,AAh or 55h. And afterwards CS# is raised or

issuing FF command (CS# goes high → CS# goes low→sending

0xFF→CS# goes high) instead of no toggling, the system then will

escape from performance enhance mode and return to normal

opertaion. In these cases, tSHSL=15ns(min) will be specified.

While Program/Erase/Write Status Register cycle is in progress,

4READ instruction is rejected without any impact on the

Program/Erase/Write Status Register current cycle.

The 2READ instruction enable double throughput of Serial Flash in

read mode. The address is latched on rising edge of SCLK, and

data of every two bits (interleave on 2 I/O pins) shift out on the

falling edge of SCLK at a maximum frequency fT. The first

address can be at any location. The address is automatically

increased to the next higher address after each byte data is shifted

out, so the whole memory can be read out at a single 2READ

instruction. The address counter rolls over to 0 when the highest

address has been reached. Once writing 2READ instruction, the

following address/dummy/data out will perform as 2-bit instead of

previous 1-bit.

The sequence of issuing 2READ instruction is: CS# goes low→

sending 2READ instruction→ 24-bit address interleave on SIO1 &

SIO0→4 dummy cycles on SIO1 & SIO0→data out interleave on

SIO1 & SIO0→ to end 2READ operation can use CS# to high at

8.10. Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the

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chosen sector to be "1". The instruction is used for any 4K-byte

sector. A Write Enable (WREN) instruction must execute to set

the Write Enable Latch (WEL) bit before sending the Sector Erase

(SE). Any address of the sector (see table 3) is a valid address

for Sector Erase (SE) instruction. The CS# must go high exactly

at the byte boundary (the eighth bit of last address byte been

latched-in); otherwise, the instruction will be rejected and not

executed.

otherwise the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low→

sending CE instruction code→ CS# goes high. (see Figure 23)

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as

Chip Select (CS#) goes high. The Write in Progress (WIP) bit still

can be check out during the Chip Erase cycle is in progress. The

WIP sets 1 during the tCE timing, and sets 0 when Chip Erase

Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

If the chip is protected by BP3, BP2, BP1, BP0 bits, the Chip

Erase (CE) instruction will not be executed. It will be only

executed when BP3, BP2, BP1, BP0 all set to "0".

Address bits [Am-A12] (Am is the most significant address) select

the sector address.

The sequence of issuing SE instruction is: CS# goes low→sending

SE instruction code→3-byte address on SI →CS# goes high. (see

Figure 21)

8.13. Page Program (PP)

The self-timed Sector Erase Cycle time (tSE) is initiated as soon

as Chip Select (CS#) goes high. The Write in Progress (WIP) bit

still can be check out during the Sector Erase cycle is in progress.

The WIP sets 1 during the tSE timing, and sets 0 when Sector

Erase Cycle is completed, and the Write Enable Latch (WEL) bit is

reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the

Sector Erase (SE) instruction will not be executed on the page.

The Page Program (PP) instruction is for programming the

memory to be "0". A Write Enable (WREN) instruction must

execute to set the Write Enable Latch (WEL) bit before sending

the Page Program (PP). The device programs only the last 256

data bytes sent to the device. The last address byte (the 8 least

significant address bits, A7-A0) should be set to 0 for 256 bytes

page program. If A7-A0 are not all zero, transmitted data that

exceed page length are programmed from the starting address

(24-bit address that last 8 bit are all 0) of currently selected page.

If the data bytes sent to the device exceeds 256, the last 256 data

byte is programmed at the request page and previous data will be

disregarded. If the data bytes sent to the device has not

exceeded 256, the data will be programmed at the request

address of the page. There will be no effort on the other data

bytes of the same page.

8.11. Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the

chosen block to be "1". The instruction is used for 64K-byte block

erase operation.

A Write Enable (WREN) instruction must

execute to set the Write Enable Latch (WEL) bit before sending

the Block Erase (BE). Any address of the block (see table 3) is a

valid address for Block Erase (BE) instruction. The CS# must go

high exactly at the byte boundary (the eighth bit of address byte

been latched-in); otherwise, the instruction will be rejected and not

executed.

The sequence of issuing PP instruction is: CS# goes low→sending

PP instruction code→3-byte address on SI→ at least 1-byte on

data on SI→ CS# goes high. (see Figure 19)

The sequence of issuing BE instruction is: CS# goes low

→sending BE instruction code→3-byte address on SI →CS# goes

high. (see Figure 22)

The CS# must be kept to low during the whole Page Program

instruction cycle; The CS# must go high exactly at the byte

boundary( the eighth bit of data being latched in), otherwise the

instruction will be rejected and will not be executed.

The self-timed Block Erase Cycle time (tBE) is initiated as soon as

Chip Select (CS#) goes high. The Write in Progress (WIP) bit still

can be check out during the Sector Erase cycle is in progress.

The WIP sets 1 during the tBE timing, and sets 0 when Sector

Erase Cycle is completed, and the Write Enable Latch (WEL) bit is

reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the

Block Erase (BE) instruction will not be executed on the page.

The self-timed Page Program Cycle time (tPP) is initiated as soon

as Chip Select (CS#) goes high. The Write in Progress (WIP) bit

still can be check out during the Page Program cycle is in progress.

The WIP sets 1 during the tPP timing, and sets 0 when Page

Program Cycle is completed, and the Write Enable Latch (WEL) bit

is reset. If the page is protected by BP3, BP2, BP1, BP0 bits, the

Page Program (PP) instruction will not be executed.

8.12. Chip Erase (CE)

8.14. 4 x I/O Page Program (4PP)

The Chip Erase (CE) instruction is for erasing the data of the

whole chip to be "1". A Write Enable (WREN) instruction must

execute to set the Write Enable Latch (WEL) bit before sending

the Chip Erase (CE). The CS# must go high exactly at the byte

boundary (the eighth bit of instruction code been latched-in),

The Quad Page Program (4PP) instruction is for programming the

memory to be "0". A Write Enable (WREN) instruction must

execute to set the Write Enable Latch (WEL) bit and Quad Enable

(QE) bit must be set to "1" before sending the Quad Page Program

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(4PP). The Quad Page Programming takes four pins: SIO0,

SIO1, SIO2, and SIO3 as address and data input, which can

improve programmer performance and the effectiveness of

application of lower clock less than 85MHz. For system with

faster clock, the Quad page program cannot provide more actual

favors, because the required internal page program time is far

more than the time data flows in. Therefore, we suggest that

while executing this command (especially during sending data),

user can slow the clock speed down to 85MHz below. The other

function descriptions are as same as standard page program.

The sequence of issuing 4PP instruction is: CS# goes

low→sending 4PP instruction code→3-byte address on SIO[3:0]→

at least 1-byte on data on SIO[3:0]→ CS# goes high. (see Figure

20)

Chip Select (CS#) must remain High for at least tRES2(max), as

specified in Table 10. AC Characteristics. Once in the Stand-by

Power mode, the device waits to be selected, so that it can receive,

decode and execute instructions. The RDP instruction is only for

releasing from Deep Power Down Mode.

RES instruction is for reading out the old style of 8-bit Electronic

Signature, whose values are shown as table of ID Definitions in

next page. This is not the same as RDID instruction. It is not

recommended to use for new design. For new design, please use

RDID instruction.

The sequence is shown as Figure 25 and Figure 26. Even in

Deep power-down mode, the RDP and RES are also allowed to be

executed, only except the device is in progress of

program/erase/write cycle; there's no effect on the current

program/erase/write cycle in progress.

8.15. Deep Power-down (DP)

The RES instruction is ended by CS# goes high after the ID been

read out at least once. The ID outputs repeatedly if continuously

send the additional clock cycles on SCLK while CS# is at low. If

the device was not previously in Deep Power-down mode, the

device transition to standby mode is immediate. If the device was

previously in Deep Power-down mode, there's a delay of tRES2 to

transit to standby mode, and CS# must remain to high at least

tRES2(max). Once in the standby mode, the device waits to be

selected, so it can be receive, decode, and execute instruction.

The Deep Power-down (DP) instruction is for setting the device on

the minimizing the power consumption (to entering the Deep

Power-down mode), the standby current is reduced from ISB1 to

ISB2).

The Deep Power-down mode requires the Deep

Power-down (DP) instruction to enter, during the Deep

Power-down mode, the device is not active and all

Write/Program/Erase instruction are ignored. When CS# goes

high, it's only in standby mode not deep power-down mode. It's

different from Standby mode.

8.17. Read Electronic Manufacturer ID & Device ID

(REMS), (REMS2), (REMS4)

The sequence of issuing DP instruction is: CS# goes low→sending

DP instruction code→ CS# goes high. (see Figure 24)

Once the DP instruction is set, all instruction will be ignored except

the Release from Deep Power-down mode (RDP) and Read

Electronic Signature (RES) instruction (those instructions allow the

ID being reading out). When Power-down, the deep power-down

mode automatically stops, and when power-up, the device

automatically is in standby mode. For RDP instruction the CS#

must go high exactly at the byte boundary (the latest eighth bit of

instruction code been latched-in); otherwise, the instruction will not

executed. As soon as Chip Select (CS#) goes high, a delay of

tDP is required before entering the Deep Power-down mode.

The REMS, REMS2 & REMS4 instruction is an alternative to the

Release from Power-down/Device ID instruction that provides both

the JEDEC assigned manufacturer ID and the specific device ID.

The REMS4 instruction is recommended to use for

4 I/O

identification and REMS2 instruction is recommended to use for 2

I/O identification.

The REMS, REMS2 & REMS4 instruction is very similar to the

Release from Power-down/Device ID instruction. The instruction

is initiated by driving the CS# pin low and shift the instruction code

"90h" or "EFh" or "DFh" followed by two dummy bytes and one

bytes address (A7~A0). After which, the Manufacturer ID for

(C2h) and the Device ID are shifted out on the falling edge of

SCLK with most significant bit (MSB) first as shown in Figure 27.

The Device ID values are listed in Table 7 of ID Definitions in next

page. If the one-byte address is initially set to 01h, then the

device ID will be read first and then followed by the Manufacturer

ID. The Manufacturer and Device IDs can be read continuously,

alternating from one to the other. The instruction is completed by

driving CS# high.

8.16. Release from Deep Power-down (RDP), Read

Electronic Signature (RES)

The Release from Deep Power-down (RDP) instruction is

terminated by driving Chip Select (CS#) High. When Chip Select

(CS#) is driven High, the device is put in the Stand-by Power mode.

If the device was not previously in the Deep Power-down mode,

the transition to the Stand-by Power mode is immediate. If the

device was previously in the Deep Power-down mode, though, the

transition to the Stand-by Power mode is delayed by tRES2, and

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Table 7. ID Definitions

manufacturer ID

C2

memory type

memory density

15

RDID Command

24

electronic ID

24

RES Command

REMS/REMS2/REMS4/

Command

manufacturer ID

C2

device ID

24

8.18. Enter Secured OTP (ENSO)

goes high.

The ENSO instruction is for entering the additional 512-bit secured

OTP mode. The additional 512-bit secured OTP is independent

from main array, which may use to store unique serial number for

system identifier. After entering the Secured OTP mode, and

then follow standard read or program, procedure to read out the

data or update data. The Secured OTP data cannot be updated

again once it is lock-down.

8.20. Read Security Register (RDSCUR)

The RDSCUR instruction is for reading the value of Security

Register bits. The Read Security Register can be read at any

time (even in program/erase/write status register/write security

register condition) and continuously.

The sequence of issuing RDSCUR instruction is : CS# goes low→

sending RDSCUR instruction → Security Register data out on

SO→CS# goes high.

The sequence of issuing ENSO instruction is: CS# goes

low→sending ENSO instruction to enter Secured OTP mode→

CS# goes high.

The definition of the Security Register bits is as below:

Secured OTP Indicator bit. The Secured OTP indicator bit shows

the chip is locked by factory before ex- factory or not. When it is

"0", it indicates non- factory lock; "1" indicates factory- lock.

Lock-down Secured OTP (LDSO) bit. By writing WRSCUR

instruction, the LDSO bit may be set to "1" for customer lock-down

purpose. However, once the bit is set to "1" (lock-down), the

LDSO bit and the 512-bit Secured OTP area cannot be update any

more. While it is in 512-bit secured OTP mode, main array

access is not allowed.

Please note that WRSR/WRSCUR commands are not acceptable

during the access of secure OTP region, once security OTP is lock

down, only read related commands are valid.

8.19. Exit Secured OTP (EXSO)

The EXSO instruction is for exiting the additional 512-bit secured

OTP mode.

The sequence of issuing EXSO instruction is: CS# goes

low→sending EXSO instruction to exit Secured OTP mode→CS#

Table 8. Security Register Definition

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

x

LDSO

Secured OTP indicator bit

(indicate if lock-down

0 = not lock-down

reserved

0 = non-factory lock

1 = factory lock

1 = lock-down (cannot

program/erase OTP)

volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit

non-volatile bit

8.21. Write Security Register (WRSCUR)

The WRSCUR instruction is for changing the values of Security

Register Bits. Unlike write status register, the WREN instruction

any more.

The sequence of issuing WRSCUR instruction is :CS# goes

low→sending WRSCUR instruction→CS# goes high.

The CS# must go high exactly at the boundary; otherwise, the

instruction will be rejected and not executed.

is not required before sending WRSCUR instruction.

The

WRSCUR instruction may change the values of bit1 (LDSO bit) for

customer to lock-down the 512-bit Secured OTP area. Once the

LDSO bit is set to "1", the Secured OTP area cannot be updated

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9. POWER-ON STATE

The device is at below states when power-up:

- Standby mode (please note it is not deep power-down mode)

- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level:

- VCC minimum at power-up stage and then after a delay of tVSL

- GND at power-down

Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state.

For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read,

write, erase, and program command should be sent after the below time delay:

- tVSL after VCC reached VCC minimum level

The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.

Please refer to the figure of "power-up timing".

Note:

- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF)

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10. ELECTRICAL SPECIFICATIONS

10.1. Absolute Maximum Ratings

Rating

Value

Ambient Operating Temperature

Storage Temperature

Applied Input Voltage

Applied Output Voltage

Industrial grade

-40°C to 85°C

-65°C to 150°C

-0.5V to 4.6V

VCC to Ground Potential

Notice:

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only and functional

operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability.

2. Specifications contained within the following tables are subject to change.

3. During voltage transitions, all pins may overshoot V_SSto -2.0V and V_CCto +2.0V for periods up to 20ns, see Figure 2, and Figure 3.

Figure2.Maximum Negative Overshoot Waveform

Figure3. Maximum Positive Overshoot Waveform

10.2. Capacitance TA = 25℃, f = 1.0 MHz

Symbol

CIN

COUT

Parameter

Input Capacitance

Output Capacitance

Min.

Typ

Max.

Unit

pF

Conditions

VIN = 0V

-

6

8

pF

VOUT = 0V

Figure4. Input Test Waveforms and Measurement Level

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Figure5. Output Loading

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10.3. DC Characteristics (Temperature = -40° C to 85° C for Industrial grade, VCC = 2.7V ~ 3.6V)(Table9)

Symbol

ILI

Parameter

Input Load Current

Notes

Min.

Typ.

Max.

Units

Test conditions

VCC = VCC Max,

VIN = VCC or GND

VCC = VCC Max,

VOUT = VCC or GND

VIN = VCC or GND,

CS# = VCC

1

-

± 2

uA

ILO

Output Leakage Current

VCC Standby Current

1

-

± 2

25

20

uA

ISB1

ISB2

VIN = VCC or GND,

CS# = VCC

Deep Power-down Current

5

f=104MHz,

fQ=85MHz (4

read)

x

I/O

25

mA

SCLK=0.1VCC/0.9VCC,

SO=Open

ICC1

VCC Read

1

-

fT=85MHz (2 x I/O read)

SCLK=0.1VCC/0.9VCC,

SO=Open

20

10

mA

f=33MHz,

SCLK=0.1VCC/0.9VCC,

SO=Open

Program in Progress,

CS# = VCC

ICC2

ICC3

ICC4

ICC5

VCC Program Current (PP)

1

-

20

mA

VCC

Write

Status

Register

Program status register

in progress, CS#=VCC

(WRSR) Current

Erase

in

Progress,

VCC Sector Erase Current (SE)

VCC Chip Erase Current (CE)

1

CS#=VCC

Erase

in

Progress,

CS#=VCC

VIL

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

-

-0.5

0.7VCC

-

0.3VCC

V

VIH

VOL

VCC+0.4

0.4

-

IOL = 1.6mA

IOH = -100uA

VOH

VCC-0.2

Notes:

1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).

2. Typical value is calculated by simulation.

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10.4. AC Characteristics (Temperature = -40° C to 85° C for Industrial grade, VCC = 2.7V ~ 3.6V)(Table10)

Symbol

Alt.

Parameter

Min.

Typ.

Max.

Unit

Clock Frequency for the following instructions:

FAST_READ, SE, BE, CE, DP, RES, RDP,

WREN, WRDI, RDID, RDSR, WRSR

Clock Frequency for PP instructions

fSCLK

fC

fP

D.C.

-

104

MHz

D.C.

-

86

85

33

85

-

MHz

ns

fPSCLK

fRSCLK

fTSCLK

f4P

fR

Clock Frequency for 4PP instructions

Clock Frequency for READ instructions

Clock Frequency for 2READ instructions

Clock Frequency for 4READ instructions

fT

-

fQ

-

fC=104MHz

4.7

13

4.7

13

0.1

5

tCH⁽¹⁾

tCL⁽¹⁾

tCLH

tCLL

Clock High Time (1633E-10G)

fR=33MHz

fC=104MHz

fR=33MHz

-

ns

-

ns

Clock Low Time (1633E-10G)

-

ns

tCLCH⁽²⁾

tCHCL⁽²⁾

tSLCH

tCHSL

tDVCH

tCHDX

tCHSH

tSHCH

Clock Rise Time ⁽³⁾(peak to peak)

Clock Fall Time ⁽³⁾(peak to peak)

-

V/ns

ns

-

tCSS

CS# Active Setup Time (relative to SCLK)

CS# Not Active Hold Time (relative to SCLK)

Data In Setup Time

-

5

-

ns

tDSU

tDH

2

-

ns

Data In Hold Time

5

-

ns

CS# Active Hold Time (relative to SCLK)

CS# Not Active Setup Time (relative to SCLK)

5

-

ns

5

-

ns

Read

15

50

-

ns

tSHSL(3)

tSHQZ(2)

tCLQV

tCSH

tDIS

CS# Deselect Time

Write/Erase/Program

-

ns

2.7V-3.6V

3.0V-3.6V

10

8

ns

Output Disable Time

-

ns

Clock Low to Output Valid 2.7V-3.6V

-

9/8

8/6

-

ns

tV

Loading: 30pF/15pF

3.0V-3.6V

-

ns

tCLQX

tWHSL

tSHWL

tDP⁽²⁾

tHO

Output Hold Time

1

ns

Write Protect Setup Time

Write Protect Hold Time

CS# High to Deep Power-down Mode

20

100

-

ns

-

ns

10

us

CS# High to Standby Mode without Electronic Signature

Read

tRES1⁽²⁾

-

8.8

us

tRES2⁽²⁾

tW

CS# High to Standby Mode with Electronic Signature Read

Write Status Register Cycle Time

Byte-Program

-

8.8

100

300

5

us

ms

us

ms

s

40

9

tBP

tPP

Page Program Cycle Time

1.4

60

0.7

14

tSE

Sector Erase Cycle Time

300

2

tBE

Block Erase Cycle Time

tCE

Chip Erase Cycle Time

30

s

Notes:

1. tCH + tCL must be greater than or equal to 1/ f (fC or fR).

2. Value guaranteed by characterization, not 100% tested in production.

3. tSHSL=15ns from read instruction, tSHSL=50ns from Write/Erase/Program instruction.

4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

5. Test condition is shown as Figure 4 and Figure 5.

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10.5. Timing Analysis

Figure 6. Serial Input Timing

Figure 7. Output Timing

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Figure 8. WP# Setup Timing and Hold Timing during WRSR when SRWD=1

Figure 9. Write Enable (WREN) Sequence (Command 06)

Figure 10. Write Disable (WRDI) Sequence (Command 04)

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Figure 11. Read Identification (RDID) Sequence (Command 9F)

Figure 12. Read Status Register (RDSR) Sequence (Command 05)

Figure 13. Write Status Register (WRSR) Sequence (Command 01)

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Figure 14. Read Data Bytes (READ) Sequence (Command 03)

Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B)

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Figure 16. 2 x I/O Read Mode Sequence (Command BB)

Note:

1. SI/SIO0 or SO/SIO1 should be kept "00" or "11" in the first 2 dummy cycles. In other words, P2=P0 or P3=P1 is necessary.

Figure 17. 4 x I/O Read Mode Sequence (Command EB)

Notes:

1. Hi-impedance is inhibited for the two clock cycles.

2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.

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Figure 18. 4 x I/O Read Enhance Performance Mode Sequence (Command EB)

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Figure 19. Page Program (PP) Sequence (Command 02)

Figure 20. 4 x I/O Page Program (4PP) Sequence (Command 38)

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Figure 21. Sector Erase (SE) Sequence (Command 20)

Note: SE command is 20(hex).

Figure 22. Block Erase (BE) Sequence (Command D8)

Note: BE command is D8(hex).

Figure 23. Chip Erase (CE) Sequence (Command 60 or C7)

Note: CE command is 60(hex) or C7(hex).

Figure 24. Deep Power-down (DP) Sequence (Command B9)

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Figure 25. RDP and Read Electronic Signature (RES) Sequence (Command AB)

Figure 26. Release from Deep Power-down (RDP) Sequence (Command AB)

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Figure 27. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)

Notes:

(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.

(2) Instruction is either 90(hex) or EF(hex) or DF(hex).

Figure 28. Power-up Timing

Note: VCC (max.) is 3.6V and VCC (min.) is 2.7V.

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Table 11. Power-Up Timing

Symbol

Parameter

Min.

Max.

Unit

tVSL(1)

VCC(min) to CS# low

200

-

us

Note: 1. The parameter is characterized only.

10.6. Initial Delivery State

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all

Status Register bits are 0).

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11. OPERATING CONDITIONS

11.1. At Device Power-Up and Power-down

AC timing illustrated in "Figure 29 and Figure 30 are for the supply voltages and the control signals at device power-up and power-down.

If the timing in the figures is ignored, the device will not operate correctly.

During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be selected. The CS# can

be driven low when VCC reach Vcc(min.) and wait a period of tVSL.

Figure 29. AC Timing at Device Power-Up

Symbol

Parameter

Notes

Min.

Max.

Unit

tVR

VCC Rise Time

1

5

500000

us/V

Notes:

1. The value is guaranteed by characterization, not 100% tested in production.

2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC CHARACTERISTICS" table.

Figure 30. Power-Down Sequence

During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.

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12. ERASE AND PROGRAMMING PERFORMANCE

Parameter

Write Status Register Cycle Time

Sector erase Cycle Time

Min.

Typ. (1)

40

Max. (2)

Unit

ms

s

-

100

300

2

60

Block erase Cycle Time

0.7

Chip Erase Cycle Time

14

30

300

5

s

Byte Program Time (via page program command)

Page Program Cycle Time

9

us

1.4

ms

cycles

Erase/Program Cycle

100,000

-

Notes:

1. Typical program and erase time assumes the following conditions: 25°C, 3.3V, and checker board pattern.

2. Under worst conditions of 85°C and 2.7V.

3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.

13. DATA RETENTION

Parameter

Condition

Min.

Max.

UNIT

Data retention

55˚C

20

-

years

14. LATCH-UP CHARACTERISTICS

Parameter

Min.

-1.0V

Max.

Input Voltage with respect to GND on all power pins, SI, CS#

Input Voltage with respect to GND on SO

2 VCC max

VCC + 1.0V

+100mA

-1.0V

Current

-100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

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15. ORDERING INFORMATION

Product Number

Package Type

Package Form - 8-SOP RoHS (Green Package)

GPR25L1603E – HS13x

Note1: Code number is assigned for customer.

Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z).

Note3: Package form number (x = 1 - 9, serial number).

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16. PACKAGE INFORMATION

16.1. Title: Package Outline for SOP 8L (200MIL)

16.2. Dimensions (Inch dimensions are derived from the original mm dimensions)

Symbol

Θ

A

A1

A2

b

C

D

E

E1

e

L

L1

S

Unit

Min.

Nom.

Max.

Min.

-

0.05

0.15

1.70

1.80

0.36

0.41

0.19

0.20

5.13

5.23

7.70

7.90

5.18

5.28

-

0.50

0.65

1.21

1.31

0.62

0.74

0

5

8

0

5

8

mm

-

1.27

2.16

0.20

1.91

0.51

0.25

5.33

8.10

5.38

-

0.80

1.41

0.88

-

0.002

0.006

0.008

0.067

0.071

0.075

0.014

0.016

0.020

0.007

0.008

0.010

0.202

0.206

0.210

0.303

0.311

0.319

0.204

0.208

0.212

-

0.050

-

0.020

0.026

0.031

0.048

0.052

0.056

0.024

0.029

0.035

inch

Nom.

Max.

0.085

REFERENCE

DWG. NO.

REVISION

ISSUE DATE

JEDEC

EIAJ

6110-1406

3

-

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17. DISCLAIMER

The information appearing in this publication is believed to be accurate.

Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the

terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this

publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, GENERALPLUS MAKES NO

WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. GENERALPLUS reserves the right to halt production or alter

the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other

information in this publication are current before placing orders. Products described herein are intended for use in normal commercial

applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support

equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that

application circuits illustrated in this document are for reference purposes only.

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18. REVISION HISTORY

Date

Revision#

Description

Page

May 10, 2013

1.0

Original

38

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型号：	GPR25L1603E-HS13x
厂家：	Generalplus Technology Inc.
描述：	16M-bit [x 1/x 2/x 4] CMOS MXSMIO (Serial Multi I/O) Flash Memory
文件：	总38页 (文件大小：1499K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

GPR25L1603E-HS13x [GENERALPLUS]

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