IC-MQF_技术文档

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 1/37

FEATURES

APPLICATIONS

♦ Optical and magnetic position

sensors

♦ Linear scales

♦ Latency-free sine-to-digital conversion to 4000 angle steps

♦ Input frequency: 200 kHz (x10), 20 kHz (x100), 2 kHz (x1000)

♦ Flexible pin assignment due to signal path multiplexers

♦ PGA inputs for differential and single-ended signals

♦ Variable input resistance for current/voltage conversion

♦ Signal conditioning for offset, amplitude and phase

♦ Controlled 50 mA current source for LED or MR sensor supply

♦ Fault-tolerant RS422 outputs with 50 mA sink/source drive

current

♦ High-resolution angle sensing

♦ Preselectable minimum phase distance for spike-proof counter

stimulus

♦ Zero signal conditioning and electronic index pulse generation

♦ Signal and operation monitoring with conﬁgurable alarm

output, output shutdown and error storage

♦ I²C multimaster interface for in-circuit calibration and

parameters (EEPROM)

PACKAGES

♦ Adjustable overtemperature alarm and shutdown

♦ Supply from 4.3 to 5.5 V, operation from -25(-40) to +100 °C

♦ Reverse-polarity-proof including the sub-system

TSSOP20

BLOCK DIAGRAM

VDDS

VDD

REVERSE POLARITY

PROTECTION

iC-MQF

GNDS

GND

SCL

MONITORING

ERR

C

SERIAL I2C

INTERFACE

CONFIGURATION

REGISTER

SINE-TO-DIGTIAL

CONVERSION

Tw

LineCount

Monitor

Sin/Cos

Monitor

PWRon

Toff

SDA

PHI

PGA INPUT

I/V

SIGNAL PATH MUX

CALIBRATION

DIGITAL DRIVER

OUTPUT

X1

PZ

NZ

PB

NB

PA

NA

x

ZIN

CH0

-

X2

I/V

I/U

x

SIGNAL LEVEL

CONTROLLER

X3

x

CH2

+

X4

x

+

-

x

X5

x

ADJ

CH1

x

X6

x

ACO

http://www.ichaus.com

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 2/37

DESCRIPTION

Interpolator iC-MQF is a non-linear A/D converter tical encoders via the integrated 50 mA driver stage

which digitizes sine/cosine sensor signals using a (output ACO). If MR sensors are connected this

count-safe tracking conversion principle with se- driver stage can also track the power supply of the

lectable resolution and hysteresis. The angle reso- measuring bridges. By tracking the sensor energy

lution per sine period can be set using SELRES; up supply any temperature and aging effects are com-

to 4000 angle steps are possible (see page 27).

pensated for, the input signals stabilized and the ex-

act calibration of the input signals is maintained. This

The angle position is output incrementally by differ- enables a constant accuracy of the interpolation cir-

ential RS422 drivers as an encoder quadrature signal cuit across the entire operating temperature range.

with a zero pulse or, if selected, as a counter signal

for devices compatible with 74HC191 or 74HC193.

If control limits are reached, these can be indicated

at the maskable error pin ERR. Faults such as over-

The zero pulse is generated electronically when an drive, wire breakage, short circuiting, dirt or aging,

enable has been set by the X1/X2 inputs. This pulse for example, can be logged.

can be conﬁgured extensively: both in its relative po-

sition to the input signal with regard to the logic gating iC-MQF includes extensive self-test and system di-

with A and/or B and in its width from 90° to 360° (1/4 agnosis functions which check whether the sensor

to 1 T).

is working properly or not. For all error events the

user can select whether the fault is indicated at the

A preselectable minimum transition distance ensures pin ERR or whether the outputs should shutdown. At

glitch-free output signals and prevents counting er- the same time errors can be stored in the EEPROM

rors which in turn boosts the noise immunity of the to enable failures to be diagnosed at a later stage.

position encoder.

For encoder applications the line count of the code

disc, the sensor signal regarding signal level and fre-

Programmable instrumentation ampliﬁers with se- quency and the operating temperature can be moni-

lectable gain levels allow differential or single-ended, tored, for example, the latter using an adjustable on-

referenced input signals; a external reference can be chip sensor.

used via input X2 as reference voltage for the offset

correction.

Display error pin ERR is bidirectional; a system fault

recognized externally can be recorded and also reg-

The modes of operation differentiate between high istered in the error memory.

impedance (V modes) and low impedance (I modes).

This adaptation of the iC to voltage or current signals iC-MQF is protected against reverse polarity and of-

enables MR sensor bridges or photosensors to be di- fers its monitored supply voltage to the external cir-

rectly connected up to the device. The optical scan- cuit, thus extending the protection to the system (for

ning of low resolution code discs is also supported by load currents up to 20 mA). Reverse polarity protec-

the reference function of input X2; these discs do not tion also covers the short-circuit-proof line drivers so

evaluate tracks differentially but in comparison with a that an unintentional faulty wiring during initial opera-

reference photodiode.

tion is tolerated.

The integrated signal conditioning unit allows signal On being activated the device conﬁguration is loaded

amplitudes and offset voltages to be calibrated ac- via the serial conﬁguration interface from an external

curately and any phase error between the sine and EEPROM and veriﬁed with a CRC. A microcontroller

cosine signals to be corrected. The channel for the can also conﬁgure iC-MQF; the implemented inter-

zero signal can be conﬁgured separately.

face is multimaster-competent and allows direct RAM

access.

A control signal is generated from the conditioned

signals which can track the transmitting LED of op-

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 3/37

CONTENTS

PACKAGING INFORMATION

4

Offset Calibration CH0 . . . . . . . . . . . . . 25

PIN CONFIGURATION TSSOP20 . . . . . .

4

SIGNAL LEVEL CONTROL and SIGNAL

MONITORING

26

27

28

ABSOLUTE MAXIMUM RATINGS

THERMAL DATA

5

SINE-TO-DIGITAL CONVERSION

OUTPUT SETTINGS AND ZERO SIGNAL

ELECTRICAL CHARACTERISTICS

PROGRAMMING

6

Zero Signal Generation . . . . . . . . . . . . 28

Output Driver Conﬁguration . . . . . . . . . . 29

Minimum Transition Distance . . . . . . . . . 29

Signal Filter . . . . . . . . . . . . . . . . . . . 29

12

13

15

REGISTER MAP

SERIAL CONFIGURATION INTERFACE

ERROR MONITORING AND ALARM OUTPUT

30

Example of CRC Calculation Routine . . . . . 15

EEPROM Selection . . . . . . . . . . . . . . 15

I²C Slave Mode (ENSL = 1) . . . . . . . . . . 16

Alarm Output: I/O-pin ERR . . . . . . . . . . 30

Line Count Error . . . . . . . . . . . . . . . . 30

Excessive Temperature Warning . . . . . . . 30

Excessive Temperature Shutdown . . . . . . 31

Driver Shutdown . . . . . . . . . . . . . . . . 31

Error Protocol . . . . . . . . . . . . . . . . . . 31

BIAS CURRENT SOURCE AND

TEMPERATURE SENSOR CALIBRATION

17

Bias Current . . . . . . . . . . . . . . . . . . 17

Temperature Sensor . . . . . . . . . . . . . . 17

REVERSE POLARITY PROTECTION

32

33

OPERATING MODES

18

TEST MODE

Mode ABZ . . . . . . . . . . . . . . . . . . . 18

Mode 191/193 . . . . . . . . . . . . . . . . . 18

Calibration 1, 2, 3, Test 5 . . . . . . . . . . . 19

TEST 6 . . . . . . . . . . . . . . . . . . . . . 19

System Test and Digital Calibration . . . . . . 19

Quick programming in the

single master system . . . . . . . . . . . 34

Quick programming in the

multimaster system . . . . . . . . . . . . 34

GENERAL APPLICATION HINTS

35

INPUT CONFIGURATION AND SIGNAL PATH

MULTIPLEXER

20

APPLICATION NOTES: SIGNAL

CONDITIONING

Current Signals . . . . . . . . . . . . . . . . . 20

Voltage Signals . . . . . . . . . . . . . . . . . 20

Signal Path Multiplexer . . . . . . . . . . . . . 21

35

Signal Conditioning Example 1: . . . . . . . . 35

Photodiode array connected to current

inputs, LED supply with constant

SIGNAL CONDITIONING CH1, CH2

23

current source . . . . . . . . . . . . . . 35

Gain Settings . . . . . . . . . . . . . . . . . . 23

Offset Calibration CH1, CH2 . . . . . . . . . 24

Phase Correction CH1 vs. CH2 . . . . . . . . 24

Signal Conditioning Example 2: . . . . . . . . 36

Encoder supplying 100 mVpp to voltage inputs 36

APPLICATION NOTES: CIRCUIT EXAMPLES

36

SIGNAL CONDITIONING CH0

25

Gain Settings CH0 . . . . . . . . . . . . . . . 25 DESIGN REVIEW: Function Notes

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 4/37

PACKAGING INFORMATION

PIN CONFIGURATION TSSOP20

PIN FUNCTIONS

No. Name Function

1 X1

2 X2

3 X3

4 X4

Signal Input 1 (Index +)

Signal Input 2 (Index -)

Signal Input 3

Signal Input 4

5 VDDS¹⁾Switched Supply Output and Internal

Analog Supply Voltage

(reverse polarity proof, load 20 mA

max.)

6 GNDS¹⁾Switched Ground

(reverse polarity proof)

7 X5

Signal Input 5

8 X6

Signal Input 6

9 ACO

Signal Level Controller,

high-side current source output

Serial Conﬁguration Interface,

data line

Serial Conﬁguration Interface,

clock line

10 SDA

11 SCL

12 NB

13 PB

14 NA

15 PA

16 GND

17 VDD

18 NZ

19 PZ

Incremental Output B-

Incremental Output B+

Incremental Output A-

Incremental Output A+

Ground

+4.3...5.5 V Supply Voltage

Incremental Output Z-

Incremental Output Z+

Error Signal (In/Out) / Test Mode Trig-

ger Input

20 ERR

1) It is advisable to connect a bypass capacitor of at least 100 nF close to the chip’s analog supply terminals.

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 5/37

ABSOLUTE MAXIMUM RATINGS

Beyond these values damage may occur; device operation is not guaranteed.

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Max.

G001 V()

Voltage at VDD, PA, NA, PB, NB, PZ,

NZ, SCL, SDA, ACO

-6

6

V

G002 V()

G003 V()

G004 V()

Voltage at ERR

-6

8

6

V

Pin-Pin Voltage

Voltage at X1...X6, SCL, SDA

-0.3

VDDS +

0.3

G005 I(VDD)

G006 I()

Current in VDD

-20

-50

400

50

mA

kV

Current in VDDS, GNDS

Current in X1...X6, SCL, SDA, ERR

Current in PA, NA, PB, NB, PZ, NZ

Current in ACO

G007 I()

-20

20

G008 I()

-100

100

20

G009 I(ACO)

G010 Vd()

G011 Ptot

G012 Tj

ESD Susceptibility at all pins

Permissible Power Dissipation

Junction Temperature

HBM 100 pF discharged through 1.5 kΩ

2

300

150

mW

°C

-40

G013 Ts

Storage Temperature

°C

THERMAL DATA

Item Symbol

No.

Parameter

Conditions

Unit

°C

Min. Typ. Max.

-25 100

T01 Ta

Operating Ambient Temperature Range

(extended range to -40 °C on request)

T02 Rthja

Thermal Resistance Chip to Ambient

80

K/W

All voltages are referenced to pin GNDS unless otherwise stated.

All currents ﬂowing into the device pins are positive; all currents ﬂowing out of the device pins are negative.

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 6/37

ELECTRICAL CHARACTERISTICS

Operating Conditions: VDD = 4.3 ... 5.5 V, T_j= -40 °C ... 125 °C, IBN calibrated to 200 µA, unless otherwise stated

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

Total Device

001

V(VDD)

Permissible Supply Voltage

Supply Current

Load current I(VDDS) to 10 mA

Load current I(VDDS) to 20 mA

4.3

4.5

5.5

V

002

I(VDD)

Tj = -40...125 °C, no load

Tj = 27 °C, no load

25

mA

18

003 I(VDDS)

004 Vcz()hi

005 Vc()hi

Permissible Load Current VDDS

Clamp-Voltage hi at all pins

-20

0

mA

V

11

1.5

Clamp-Voltage hi at Inputs SCL, Vc()hi = V() - V(VDD), I() = 1 mA

SDA

0.4

0.3

V

006 Vc()hi

007 Vc()lo

Clamp-Voltage hi at Inputs

X1...X6

Vc()hi = V() - V(VDD), I() = 4 mA

1.2

V

Clamp-Voltage lo at all pins

I() = -4 mA

-1.2

-1

-0.3

1

V

008 Irev(VDD) Reverse-Polarity Current VDD vs. V(VDD) = −5.5V...−4.3 V

mA

GND

Signal Conditioning, Inputs X1...X6 (CH1, CH2: i = 12, CH0: I = 0)

101

102

Vin()sig

Iin()sig

Permissible Input Voltage Range

Permissible Input Current Range

Ri() = 0x01

0.75

0

VDDS

− 1.5

VDDS

V

Ri() = 0x09

Ri(0) = 0; BIASi = 0

Ri(0) = 0; BIASi = 1

-300

10

-10

300

µA

103 Iin()

Input Current

Ri() = 0x01

-0.5

95

0.5

µA

%

104 Vout(X2)

Output Voltage at X2

MUX = 0x20...0x2F, I(X2) = 0, referenced to

VREFin12

100

27

105

105 Vin(X2)

106 Rin(X2)

Permissible Input Voltage at X2 MUX = 0x30...0x3F

0.5

20

VDDS

− 2

35

V

Input Resistance at X2

MUX = 0x30...0x3F, R0(3:0) = 0x01, R12(3:0) =

kΩ

0x01

107

Rin()

Input Resistance vs. VREFin

Tj = 27 °C;

Ri(3:0) = 0x09

Ri(3:0) = 0x00

Ri(3:0) = 0x02

Ri(3:0) = 0x04

Ri(3:0) = 0x06

16

1.1

1.6

2.2

3.2

20

1.6

2.3

3.2

4.6

24

2.1

3.0

4.2

6.0

kΩ

108 TC(Rin)

Temperature Coefﬁcient of Rin

0.15

%/K

109

VREFin() Reference Voltages

Ri(0) = 0, BIASi = 1

Ri(0) = 0, BIASi = 0

1.35

2.25

1.5

2.5

1.65

2.75

V

VREFin0, VREFin12

110

G0, G12

Selectable Gain Factors

MODE=0x05, Ri(3) = 0, GRi and GFi = 0x0

MODE=0x05, Ri(3) = 0, GRi and GFi = max.

6

300

MODE=0x05, Ri(3) = 1, GRi and GFi = 0x0

MODE=0x05, Ri(3) = 1, GRi and GFi = max.

1.5

75

111

112

Gdiff

Relative Gain Ratio CH1 vs. CH2

GF2 = 0x10, GF1 = 0x0

GF2 = 0x10, GF1 = 0x7FF

39

255

%

∆G

Step Width Of Fine Gain

Adjustment

for CH0

for CH1

for CH2

1.06

1.0009

1.06

113 INL(Gi)

114

Integral Linearity Error of Gain

Adjustment

-1.06

1.06

Vin()diff

Recommended Differential Input

Voltage

Vin()diff = V(PCHx) - V(NCHx);

Ri(3) = 0

Ri(3) = 1

20

80

1000

4000

mVpp

115 Vin()os

116

Input Offset Voltage

referred to side of input

25

µV

VOScal

Offset Calibration Range

referenced to the selected source (VOS0 resp.

VOS12), mode Calibration 2;

ORi = 00

ORi = 01

ORi = 10

ORi = 11

±100

±200

±600

±1200

%V()

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 7/37

ELECTRICAL CHARACTERISTICS

Operating Conditions: VDD = 4.3 ... 5.5 V, T_j= -40 °C ... 125 °C, IBN calibrated to 200 µA, unless otherwise stated

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

117 ∆OF0

118 ∆OF12

119 INL(OFi)

CH0 Offset Calibration Step

Width

referenced to the selected source VOS0;

OR0 = 0x0

3.2

%

CH1/2 Offset Calibration Step

Width

referenced to the selected source VOS12;

OR12 = 0x0

0.79

Integral Linearity Error of Offset limited test coverage (guaranteed by design)

Calibration

-5

5

LSB

120 PHI12

Phase Error Calibration Range

CH1 vs. CH2

±10.4

0.02

°

121 ∆PHI12

Phase Error Calibration Step

Width

122 INL(PHI12) Integral Linearity Error of Phase limited test coverage (guaranteed by design)

Calibration

-0.8

200

0.8

1.8

°

123 ﬁn()

Sine-To-Digital Conversion

201 AAabs Absolute Angle Accuracy

Permissible Maximum Input Freq. analog signal path

kHz

referenced to 360° input signal, ideal waveform,

quasi static signals, adjusted signal condition-

ing, SELHYS = 0

0.9

°

202

AArel

Relative Angle Accuracy

referenced to output period T (see Fig. 1), ideal

waveform, quasi static signals;

at 4 edges per period

10

15

30

50

%

at 200 edges per period

at 500 edges per period

at 1000 edges per period

at 2000 edges per period

1.7

3.5

7

14

28

at 4000 edges per period

203 AAR

Repeatability

see 201; VDD = const., T_j= const.

0.1

°

204 ﬁn()max

Maximum Input Frequency for

Sine-To-Digital Conversion

MTD = 0x01, IPF < 10;

refer to Figure 2 for dependencies

200

kHz

Line Driver Outputs PA, NA, PB, NB, PZ, NZ

501

Vs()hi

Saturation Voltage hi

Vs() = VDD - V();

SIK(1:0) = 00, I() = -1.2 mA

SIK(1:0) = 01, I() = -4 mA

SIK(1:0) = 10, I() = -20 mA

SIK(1:0) = 11, I() = -50 mA

200

400

700

mV

502

503

Vs()lo

Isc()hi

Saturation Voltage lo

SIK(1:0) = 00, I() = 1.2 mA

SIK(1:0) = 01, I() = 4 mA

SIK(1:0) = 10, I() = 20 mA

SIK(1:0) = 11, I() = 50 mA

200

400

700

mV

Short-Circuit Current hi

V() = 0 V;

SIK(1:0) = 00

SIK(1:0) = 01

SIK(1:0) = 10

SIK(1:0) = 11

-4

-12

-60

-150

-1.2

-4

-20

-50

mA

504

505

506

Isc()lo

tr()

Short-Circuit Current lo

Rise Time

V() = VDD;

SIK(1:0) = 00

SIK(1:0) = 01

SIK(1:0) = 10

SIK(1:0) = 11

1.2

4

20

50

4

12

60

150

mA

RL = 100 Ω to GND;

SSR(1:0) = 00

SSR(1:0) = 01

SSR(1:0) = 10

SSR(1:0) = 11

5

20

50

20

40

140

350

ns

tf()

Fall Time

RL = 100 Ω to VDD;

SSR(1:0) = 00

SSR(1:0) = 01

SSR(1:0) = 10

SSR(1:0) = 11

5

30

50

20

40

140

350

ns

507 Ilk()tri

508 IIk()rev

509 Rin()cal

Leakage Current

TRIHL(1:0) = 11 (tristate)

reversed supply voltage

Op. modes Calibration 1, 2, 3

20

100

2.5

100

µA

kΩ

Leakage Current

Test Signal Source Impedance

4

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 8/37

ELECTRICAL CHARACTERISTICS

Operating Conditions: VDD = 4.3 ... 5.5 V, T_j= -40 °C ... 125 °C, IBN calibrated to 200 µA, unless otherwise stated

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

510 I()cal

Permissible Test Signal Load

Op. modes Calibration 1, 2, 3

-3

3

µA

511

tclk()lo

Clock Signal Low-Pulse Duration

for CP, CPD, CPU

Op. mode Mode 191/193;

MTD = 0x03

MTD = 0x04

MTD = 0x05

MTD = 0x06

MTD = 0x07

MTD = 0x08

MTD = 0x09

MTD = 0x0A

MTD = 0x0B

MTD = 0x0C

MTD = 0x0D

MTD = 0x0E

MTD = 0x0F

50

62.5

75

ns

87.5

100

150

200

300

400

500

600

700

800

512 tw()hi

513 t_AB

Duty Cycle

referenced to output period T, see Figure 1

see Figure 1

50

25

%

Phase Shift A vs. B

Minimum Phase Distance

514

t_MTD

edge to edge, see Figure 1, CFGOSZ cali-

brated;

MTD = 0x01

MTD = 0x02

MTD = 0x03

MTD = 0x04

MTD = 0x05

MTD = 0x06

MTD = 0x07

MTD = 0x08

MTD = 0x09

MTD = 0x0A

MTD = 0x0B

MTD = 0x0C

MTD = 0x0D

MTD = 0x0E

45

65

90

75

100

135

170

200

230

260

390

ns

110

130

150

175

260

345

515

685

860

1030

1200

1370

520

780

1040

1300

1560

1820

2080

MTD = 0x0F

515

∆t_MTD

Minimum Phase Distance

Variation

VDD = 4.3...5.5 V, Tj = 27 °C, variation vs.

VDD = 5 V;

-10

10

%

VDD = 5 V, Tj = -40...125 °C, variation vs.

-5

15

%

Tj = 27 °C;

Signal Level Controller ACO

601

Vs()hi

Saturation Voltage hi

Vs() = VDD - V();

ACOT(1:0) = 0x2,ACOR(1:0) = 0x0,

ACOS(4:0) = 0x1F, I() = -5 mA

ACOT(1:0) = 0x2,ACOR(1:0) = 0x1,

ACOS(4:0) = 0x1F, I() = -10 mA

ACOT(1:0) = 0x2,ACOR(1:0) = 0x2,

ACOS(4:0) = 0x1F, I() = -25 mA

ACOT(1:0) = 0x2,ACOR(1:0) = 0x3,

ACOS(4:0) = 0x1F, I() = -50 mA

1

V

1

1.2

602

Isc()hi

Short-Circuit Current hi

V() = 0 ... VDD - 1 V;

ACOT(1:0) = 0x2,ACOR(1:0) = 0x0,

ACOS(4:0) = 0x1F

ACOT(1:0) = 0x2,ACOR(1:0) = 0x1,

ACOS(4:0) = 0x1F

ACOT(1:0) = 0x2,ACOR(1:0) = 0x2,

-10

-20

-50

-5

mA

-10

-25

ACOS(4:0) = 0x1F

V() = 0 ... VDD - 1.2 V;

ACOT(1:0) = 0x2,ACOR(1:0) = 0x3,

-100

-50

mA

ACOS(4:0) = 0x1F

603 It()min

604 It()max

Control Range Monitoring 1:

lower limit

referenced to range ACOR(1:0)

3

%Isc

Control Range Monitoring 2:

upper limit

90

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 9/37

ELECTRICAL CHARACTERISTICS

Operating Conditions: VDD = 4.3 ... 5.5 V, T_j= -40 °C ... 125 °C, IBN calibrated to 200 µA, unless otherwise stated

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

605 Vt()min

Signal Level Monitoring 1:

lower limit

referenced to Vscq()

40

%Vpp

606 Vt()max

Signal Level Monitoring 2:

upper limit

130

Bias Current Source and Reference Voltages

801

IBN

Bias Current Source

Calibration 1, I(NB) vs. VDDS;

CFGIBN = 0x0

110

µA

CFGIBN = 0xF

IBN calibrated at T = 25 °C

370

220

180

1.2

45

200

1.25

50

802 VBG

Internal Bandgap Reference

Reference Voltage

1.3

55

V

803 VPAH

804 V05

%VDDS

mV

Reference Voltage V05

Reference Voltage V025

450

500

50

550

805 V025

%V05

Power-Down-Reset

901 VDDon

Turn-on Threshold VDD, Power- increasing voltage at VDD

Up-Enable

3.6

3.0

0.4

4.0

3.5

4.3

3.8

V

902 VDDoff

Turn-off Threshold VDD, Power- decreasing voltage at VDD

Down-Reset

903 VDDhys

Hysteresis

Error Signal Input/Output, Pin ERR

B01 Vs()lo

B02 Isc()lo

Saturation Voltage lo

versus GND, I() = 4 mA

0.4

8

V

Short-Circuit Current lo

versus GND, V(ERR) ≤ VDD

versus GND, V(ERR) > VTMon

L state

Z state

4

5

mA

B03

Isc()

Low-Side Current Source For

Data Output

2

0

mA

B04 Vt()hi

B05 Vt()lo

B06 Vt()hys

B07 Ipu()

Input Threshold Voltage hi

Input Threshold Voltage lo

Input Hysteresis

versus GND

2

V

versus GND

0.8

300

-400

Vt()hys = Vt()hi − Vt()lo

V() = 0...VDD − 1 V, EPU = 1

Vpu() = VDD − V(), I() = -5 µA, EPU = 1

increasing voltage at ERR

500

mV

µA

V

Input-Pull-Up-Current

Pull-Up-Voltage

-300

-200

0.4

B08 Vpu()

B09 VTMon

Test Mode Turn-on Threshold

VDD +

2

V

B10 VTMoff

B11 VTMhys

Test Mode Turn-off Threshold

decreasing voltage at ERR

VDD +

0.5

V

Test Mode Threshold Hysteresis VTMhys = VTMon − VTMoff

Data Output Signal Frequency

0.15

0.3

B12

fclk()

ENFAST = 0

ENFAST = 1

120

480

160

640

200

800

kHz

B13 tp(ERR)in Process Delay for System Error upon power up (VDD > VDDon)

Message at ERR

10

ms

Reverse Polarity Protection and Supply Switches VDDS, GNDS

C01

Vs()

Saturation Voltage vs. VDD

Vs(VDDS) = VDD − V(VDDS);

I(VDDS) = -10...0 mA

150

250

mV

I(VDDS) = -20...-10 mA

C02

Vs()

Saturation Voltage vs. GND

Vs(GNDS) = V(GNDS) − GND;

I(GNDS) = 0...10 mA

150

200

mV

I(GNDS) = 10...20 mA

C03 C()

Backup Capacitor Analog Supply

VDDS vs. GNDS

100

nF

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 10/37

ELECTRICAL CHARACTERISTICS

Operating Conditions: VDD = 4.3 ... 5.5 V, T_j= -40 °C ... 125 °C, IBN calibrated to 200 µA, unless otherwise stated

Item Symbol

No.

Parameter

Conditions

Unit

Min.

Typ.

Max.

Serial Conﬁguration Interface SCL, SDA

D01 Vs()lo

D02 Isc()lo

D03 Vt()hi

D04 Vt()lo

D05 Vt()hys

D06 Ipu()

D07 Vpu()

Saturation Voltage lo

Short-Circuit Current lo

Input Threshold Voltage hi

Input Threshold Voltage lo

Input Hysteresis

I = 4 mA

400

75

2

mV

mA

V

4

0.8

300

-600

V

Vt()hys = Vt()hi − Vt()lo

V() = 0...VDDS − 1 V

500

mV

µA

V

Input Pull-Up Current

Pull-Up Voltage

-300

-60

0.4

Vpu() = VDDS − V(), I() = -5 µA

D08

fclk()

Clock Frequency at SCL

ENFAST = 0

ENFAST = 1

60

240

80

320

100

400

kHz

D09

tbusy()cfg Duration of Startup Conﬁguration

IBN not calibrated, EEPROM access without

read failure, time to outputs operational;

ENFAST = 0

36

24

48

34

ms

ENFAST = 1

D10

D11

tbusy()err End Of I2C Communication;

IBN not calibrated;

Time Until I2C Slave Is Enabled V(SDA) = 0V

4

indef.

45

12

ms

V(SCL) = 0V or Arbitration Lost

no EEPROM

CRC ERROR

135

285

95

tp()

Start Of Master Activity On I2C

Protocol Error

SCL without clock signal: V(SCL) = constant;

IBN not calibrated

IBN calibrated to 200 µA

25

64

80

240

150

µs

Temperature Monitoring

E01

VTs

Temperature Sensor Voltage

VTs() = VDDS − V(PA),

Calibration 3, without Load;

Tj = -40 °C

740

620

460

770

650

520

790

670

540

mV

Tj = 27 °C

Tj = 100 °C

E02 TCs

E03

Temp. Co. Temperature Sensor

Voltage

-1.8

mV/K

VTth

Temperature Warning Activation

Threshold

VTth() = VDDS - V(NA), Tj = 27 °C,

Calibration 3, without Load;

CFGTA(3:0) = 0x0

260

470

310

550

360

630

mV

CFGTA(3:0) = 0xF

E04 TCth

E05

Temp. Co. Temperature Warning

Activation Threshold

0.06

%/K

Tw

Warning Temperature

CFGTA(3:0) = 0x0

CFGTA(3:0) = 0xF

125

140

65

°C

80

25

E06 Thys

Warning Temperature Hysteresis 80 °C < T_j< 125 °C

10

5

15

°C

E07 ∆T

Relative Shutdown Temperature ∆T = Toff − Tw

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 11/37

t

AB

MTD

t

whi

AArel

Figure 1: Deﬁnition of relative angle error and minimum phase distance.

100

MTD=0x1 (50 ns)

MTD=0x2 (75 ns)

MTD=0x3 (100 ns)

MTD=0x4 (120 ns)

MTD=0x5 (150 ns)

MTD=0x6 (175 ns)

MTD=0x7 (200 ns)

MTD=0x8 (300 ns)

MTD=0x9 (400 ns)

MTD=0xA (600 ns)

MTD=0xB (800 ns)

MTD=0xC (1.0 µs)

MTD=0xD (1.2 µs)

MTD=0xE (1.4 µs)

MTD=0xF (1.6 µs)

10

1

0,1

1

2

4

5

8

10

20

25

40

50

100 125 200 250 500 1000

Interpolation Factor IPF

Figure 2: Maximum input frequency depending on interpolation factor.

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 12/37

PROGRAMMING

Register Map, Overview . . . . . . . . . . . . . . . . . . . Page 13 Signal Level Controller . . . . . . . . . . . . . . . . . . . . Page 26

ACOT(1:0): Controller Operating Modes

Serial Conﬁguration Interface . . . . . . . . . . . . . Page 15

ENFAST:

ENSL:

I²C Fast Mode

ACOR(1:0): Output Current Range

I²C Slave Mode

ACOS(4:0): Setpoint (relates to ACOT)

CHKSUM:

CRC of chip conﬁguration data

(address range 0x00 to 0x2F)

Chip Release

Sine-To-Digital Conversion . . . . . . . . . . . . . . . . Page 27

CHPREL:

END:

SELRES:

SELHYS:

Converter Resolution

Converter Hysteresis

Conﬁguration Enable

Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 17

Quadrature Output Logic . . . . . . . . . . . . . . . . . . Page 28

CFGABZ: Output Logic

CFGZPOS: Zero Signal Positioning

ENZFF: Zero Signal Synchronization

CFGIBN:

CFGTA:

Bias Current

Temperature Monitoring

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18

MODE: Operating Mode

Input Conﬁguration

and Signal Path Multiplexer . . . . . . . . . . . . . . . Page 20

Output Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 29

SIK:

Output Short-Circuit Current

Output Slew Rate

R12:

I/V Mode and Input Resistance CH1,

SSR:

CH2

TRIHL:

MTD:

Output Drive Mode

BIAS12:

R0:

BIAS0:

MUX:

Reference Voltage CH1, CH2

I/V Mode and Input Resistance CH0

Reference Voltage CH0

Input Multiplexer

Minimum Transition Distance

Noise Filter

ENF:

CFGOSZ:

Calibration of MTD Oscillator

Signal Conditioning CH1, CH2 (X3...X6) . . . Page 23

Error Monitoring and Alarm Output . . . . . . . Page 30

GR12:

GF1:

Gain Range CH1, CH2 (coarse)

Gain Factor CH1 (ﬁne)

EMTD:

Min. Indication Time Alarm Output ERR

I/O Logic Alarm Output ERR

Pull-Up Enable Alarm Output ERR

Error Mask Alarm Output ERR

Line Count Reference

GF2:

Gain Factor CH2 (ﬁne)

EPH:

VOS12:

VDC1:

VDC2:

OR1:

Offset Reference Source CH1, CH2

Intermediate Voltage CH1

Intermediate Voltage CH2

Offset Range CH1 (coarse)

Offset Factor CH1 (ﬁne)

EPU:

EMASKA:

LINECNT:

EMASKO:

PDMODE:

EMASKE:

ERR1:

OF1:

Error Mask Driver Shutdown

Driver Activation

OR2:

OF2:

Offset Range CH2 (coarse)

Offset Factor CH2 (ﬁne)

Error Mask EEPROM Savings

Error Protocol: First Error

Error Protocol: Last Error

Error Protocol: History

PH12:

Phase Correction CH1 vs. CH2

Signal Conditioning CH0 (X1, X2) . . . . . . . . . Page 25

ERR2:

GR0:

GF0:

VOS0:

OR0:

OF0:

Gain Range CH0 (coarse)

Gain Factor CH0 (ﬁne)

Offset Reference Source CH0

Offset Range CH0 (coarse)

Offset Factor CH0 (ﬁne)

ERR3:

Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 33

EMODE: Test Mode

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 13/37

REGISTER MAP

Register Map

Addr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Calibration

0x00

0

ENFAST

CFGIBN(3:0)

CFGTA(4:0)

0x01

Operating Mode

0x02 END

Input Conﬁguration

ENSL

0

ENZFF

MODE(3:0)

0x03

0x04

0x05

0x06

ENF

MUX(6:0)

0

1

BIAS0

BIAS12

1

VOS0(1:0)

VOS12(1:0)

R0(3:0)

R12(3:0)

0

1

0

Signal Conditioning CH0

0x07

0x08

0x09

0

GR0(2:0)

OR0(1:0)

0

GF0(4:0)

OF0(5:0)

Signal Conditioning CH1, CH2

0x0A

GF1(3:0)

0

GR12(2:0)

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0

GF1(10:4)

0

GF2(4:0)

VDC1(7:0)

VDC2(3:0)

OF1(3:0)

0

VDC1(9:8)

OR1(1:0)

0

VDC2(9:4)

OR2(1:0)

OF1(10:4)

OF2(7:0)

PH12(3:0)

0

OF2(10:8)

0

PH12(9:4)

Signal Level Controller

0x15

0x16

ACOR(1:0)

ACOS(4:0)

0

ACOT(1:0)

Error Monitoring and Alarm Output

0x17

EMASKA(7:0)

0

0x18

0x19

0x1A

0x1B

0x1C

0

EMTD(2:0)

EPU

0

EMASKA(9:8)

EMASKO(9:8)

EMASKE(9:8)

EMASKO(7:0)

PDMODE

EPH

0

EMASKE(7:0)

0

EMODE(2:0)

Zero Signal Output

0x1D

0x1E

CFGABZ(7:0)

CFGZPOS(7:0)

Sine-To-Digital-Conversion, Minimum Phase Distance

0x1F

0x20

MTD(3:0)

SELHYS(3:0)

SELRES(7:0)

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 14/37

Register Map

Addr

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x21

0

SELRES(14:8)

Output Driver Settings

0x22

0

SIK(1:0)

SSR(1:0)

TRIHL(1:0)

Line Counter

0x23

LINECNT(7:0)

0x24

0

LINECNT(13:8)

Sine-To-Digital-Conversion, Calibration

0x25

0

CFGOSZ(2:0)

Reserved

0x26

0

0x27

0x28

0x29

free for OEM data

0x2A

0x2B

0x2C

0x2D

0x2E

Check Sum

0x2F

CHKSUM(7:0) of EEPROM data

[CHPREL(7:0), refer to Table 7]

Error Register

0x30

0x31

0x32

ERR1(7:0)

ERR2(5:0)

ERR1(9:8)

ERR3(3:0)

ERR2(9:6)

0x33

0

ERR3(9:4)

Notes

The device RAM initially contains random data following power-on.

Table 4: Register layout (EEPROM)

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 15/37

SERIAL CONFIGURATION INTERFACE

ENSL

Code

0

Adr 0x02, bit 6

The serial conﬁguration interface consists of the two

pins SCL and SDA and enables read and write ac-

cess to an EEPROM with an I²C interface. The readout

clock rate can be selected using ENFAST.

Function

Normal operation

I²C Slave Mode Enable (Device ID 0x55)

1

Table 6: I²C Slave Mode

ENFAST

Code

0

Adr 0x00, bit 4

Function

Regular clock rate, f(SCL) approx. 80 kHz

High clock rate, f(SCL) approx. 320 kHz

Example of CRC Calculation Routine

1

Notes

For in-circuit programming bus lines SCL and SDA

require pull-up resistors.

For line capacitances to 170 pF, adequate values

are:

unsigned char ucDataStream

int iCRCPoly 0x11D ;

unsigned char ucCRC=0;

int 0;

= 0;

=

i

=

4.7 kΩ with clock frequency 80 kHz

2 kΩ with clock frequency 320 kHz

ucCRC = 1; / / s t a r t value ! ! !

for ( iReg

= 0; iReg <47; iReg ++)

The pull-up resistors may not be less than 1.5 kΩ.

To separate the signals a ground line between SCL

and SDA is recommended.

iC-MQF requires a supply voltage during EEPROM

programming (5 V to VDD).

{

ucDataStream

for ( i =0; i <=7; i ++)

i f ( (ucCRC & 0x80 ) != ( ucDataStream & 0x80 ) )

ucCRC = (ucCRC << 1) iCRCPoly ;

else

ucCRC = (ucCRC << 1 ) ;

ucDataStream ucDataStream << 1;

= ucGetValue ( iReg ) ;

{

^

Table 5: I²C Fast Mode

=

}

Once the supply has been switched on, the iC-MQF

outputs are high impedance (tristate) until a valid con-

ﬁguration is read out from the EEPROM using device

ID 0x50.

EEPROM Selection

The following minimal requirements must be fulﬁlled:

Bit errors in the 0x00 to 0x2F memory section are

pinpointed by the CRC deposited in register CHK-

SUM(7:0) (address 0x2F in the EEPROM; the CRC

polynomial used is "’1 0001 1101"’ with a start value

of "1").

• Operation from 3.3 to 5 V, I²C interface

• At least 512 bits, 64x8

(address range used is 0x00 to 0x3F)

• Support of Page Write with Pages of at least 4

bytes. Otherwise, errors can not be saved to the

EEPROM (EMASKE = 0x0).

If the conﬁguration data is not conﬁrmed by the CRC,

the readin process is repeated. If no valid conﬁgura-

tion data is available after a fourth readin, iC-MQF ter-

minates EEPROM access and switches to I²C slave

mode. This switch takes place after 150 ms at the lat-

est (see Electrical Characteristics, D11), for example if

no EEPROM is connected.

• Device ID 0x50 "1010 000", no occupation of

0x55 (A2...A0 = 0). Otherwise, iC-MQF can not

be accessed via 0x55 in I²C slave mode.

Bit ENSL decides (for devices loading a valid conﬁg- Recommended devices:

uration from the EEPROM register) whether the I²C M24C01W, ST M24C02 (2K), ROHM BR24L01A-W,

slave function is enabled or not. BR24L02-W

Atmel AT24C01C, ST

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 16/37

I²C Slave Mode (ENSL = 1)

Register

Read access via I²C slave mode (ENSL = 1)

In this mode iC-MQF behaves like an I²C slave with the

device ID 0x55 and the conﬁguration interface permits

write and read accesses to iC-MQF’s internal registers.

RAM Addr Content

0x00-0x21 Conﬁguration data

(see EEPROM addresses 0x00-0x21)

0x22-0x2A Not available

0x2B-0x2E Conﬁguration data

For chip release veriﬁcation purposes an identiﬁcation

value is stored under ROM address 0x2F; a write ac-

cess to this address is not permitted.

(see EEPROM addresses 0x2B-0x2E)

Chip release CHPREL(7:0)

0x30-0x33 Conﬁguration data

(see EEPROM addresses 0x30-0x33)

0x2F

CHPREL

Code

Adr 0x2F, bit 7:0 (ROM)

Chip Release

iC-MQ F2

0x34-0x3A Not available

0x3B-0x3E Conﬁguration data

0x22

(see EEPROM addresses 0x2B-0x2E)

0x23

iC-MQ F3

0x3F

Chip release CHPREL(7:0)

0x40-0x43 Current error memory* (only active when enabled

by EMASKE; messages will be transferred to

EEPROM Addresses 0x30-0x33)

Table 7: Chip Release

0x44-0x7F Not available

END

Code

0

Adr 0x02, bit 7

Function

Notes

*) Upon changing enable register EMASKE, a

double restart of Sin/D conversion (2x END: 0→1)

is essential for the correction of RAM contents.

Sin/D converter and line driver disabled

(RAM conﬁguration data invalid)

1

Restart of Sin/D conversion, line driver active

(RAM conﬁguration data valid)

Table 9: RAM Read Access

Register

Write access via I²C slave mode (ENSL = 1)

Table 8: Conﬁguration Enable

RAM Addr Access and conditions

0x00

0x01

Changes possible, no restrictions

For programming iC-MQF via I²C addresses 0x00 to

0x2E need to be written. In doing so, bit 7 of address

0x02 must be set zero initially (END = 0), until all reg-

isters have been conﬁgured. Finally, a restart requires

END = 1 to be written without changing other bits of

address 0x02.

Changes possible

(wrong entries for CFGIBN can limit functions)

0x02

Changes to bits 6:0 are permitted only when Sin/D

conversion is halted (END = 0, ie. bit 7);

Restarting Sin/D conversion by changing END (bit

7) is permitted only with no changes of operating

mode (bits 6:0 remain as set)

0x03-0x16 Changes possible, no restrictions

Addr 0x02

END = 0

0x17

Changes to bits 7:4 and 2:0 are permitted

(ENSL, bit 3 must be kept 1)

bit 7 = 0

0x18

Changes possible, no restrictions

Write registers

Configuration

0x00 ... 0x2E

0x19-0x21 Changes possible when Sin/D conversion is halted

(END = 0)

0x2B-0x2E Changes possible, no restrictions

0x2F-0x3F No write access permitted

0x40-0x43 No write access permitted

0x44-0x7F Not available

Addr 0x02

END = 1

bit 7 = 1

Figure 3: Programming via I²C. END is altered by

changing only bit 7 of address 0x02 and

leaving bits 6:0 unchanged.

Table 10: RAM Write Access

Notice: The converter function should be halted by

END = 0 for the deletion of errors saved in the EEP-

ROM (Dev-ID 0x50, Addresses 0x30-0x33). Other-

wise active errors could be transferred to the EEP-

ROM again (from addresses 0x40-0x43 if enabled by

EMASKE).

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 17/37

BIAS CURRENT SOURCE AND TEMPERATURE SENSOR CALIBRATION

Bias Current

state (from low to high) should be generated with the

The calibration of the bias current source in operation help of an external pull-up resistor at pin ERR.

mode Calibration 1 (see Table 13) is prerequisite for

adherence to the given electrical characteristics and

also instrumental in the determination of the chip tim-

ing (e.g. clock frequency at SCL). The IBN bias current

is measured by connecting pin VDDS and pin NB with

a 10 kΩ resistor. The setpoint is 200 µA which is equiv-

alent to a voltage drop of 2 V.

Example: VTs(T₁) is ca. 650 mV, measured from

VDDS versus PA, with T₁= 25 °C; -

The necessary reference voltage VTth(T₁) is then cal-

culated. The required warning temperature T₂, tem-

perature coefﬁcients TCs and TCth (see Electrical

Characteristics, Section E) and measurement value

VTs(T₁) are entered into this calculation:

Notice: The measurement delivers a false reading

when outputs are tristate (due to a conﬁguration er-

ror after cycling power, for instance).

VTs(T₁) + TCs · (T₂− T₁)

VTth(T₁) =

1 + TCth · (T₂− T₁)

CFGIBN

Code k

0x0

Adr 0x00, bit 3:0

31

39−k

IBN ∼

79 %

81 %

84 %

86 %

88 %

91 %

94 %

97 %

Code k

0x8

IBN ∼

100 %

103 %

107 %

111 %

115 %

119 %

124 %

129 %

39−k

Example: For T₂= T₁+ 100 K VTth(T₁) must be pro-

grammed to 443 mV.

0x1

0x9

0x2

0xA

0xB

0xC

0xD

0xE

0xF

0x3

Reference voltage VTth(T₁) is provided for a high

impedance measurement (10 MΩ) at output pin NA

(measurement against VDDS) and must be set to the

calculated value by programming CFGTA(3:0).

0x4

0x5

0x6

0x7

Example: Altering VTth(T₁) from 310 mV (measured

with CFGTA(3:0)= 0x0) to 443 mV is equivalent to

143 %, the closest value for CFGTA is 0x9;

Table 11: Bias Current

Temperature Sensor

The temperature monitoring is calibrated in operating

mode Calibration 3.

CFGTA

Code k

0x0

Adr 0x01, bit 4:0

65+3k

VTth ∼

65

65+3k

65

Code k

0x8

VTth ∼

137 %

142 %

146 %

151 %

155 %

160 %

165 %

169 %

100 %

105 %

109 %

114 %

118 %

123 %

128 %

132 %

0x1

0x9

The voltage VTs, at which the warning message is

generated, is determined ﬁrst. A voltage ramp from

VDDS towards GNDS is applied to pin PA until pin ERR

displays the warning message. The following settings

are required for this measurement: EMASKA = 0x20,

EMTD = 0x00 and EPH = 0x00.

0x2

0xA

0xB

0xC

0xD

0xE

0xF

0x3

0x4

0x5

0x6

0x7

0x10-0x1F reserved

The signal at pin ERR switches from tristate to low (on

reaching the warning threshold VTs) and then from

low to tristate (on overshooting the threshold of the

overtemperature self protection which is not relevant

to calibration). To avoid confusion a clear change of

Notes

With CFGTA = 0xF Toff is 80 °C typ.,

with CFGTA = 0x0 Toff is 155 °C typ.

Table 12: Temperature Monitoring

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 18/37

OPERATING MODES

iC-MQF has various modes of operation, for which the coder quadrature signal with a zero pulse. Only in

functions of outputs PA, NA, PB, NB, PZ, NZ and ERR these modes are the line drivers and the reverse po-

are altered.

larity protection feature active.

Two operating modes can be selected for the out- In order to condition the input signals and to cali-

put of the angle position in normal operation. Mode brate and test iC-MQF Calibration and Test modes

191/193 provides control signals for devices compati- are available. Digital and analog test signals are pro-

ble with 74HC191 or 74HC193, whereas in Mode ABZ vided; the latter must always be measured at high load

the angle position is output incrementally as an en- impedance.

MODE(3:0)

Code

0x00

0x0F

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

Addr. 0x02; bit 3:0

Operating Mode

Mode ABZ

Mode 191/193

Calibration 1

Calibration 2

res. *

Pin PA

A

Pin NA

not(A)

CPU

res.

Pin PB

B

Pin NB

not(B)

nU/D

IBN

Pin PZ

Z

Pin NZ

not(Z)

nPL

Pin ERR

ERR

res.

CPD

res.

PCH1

res.

PSIN

X4

CP

MR

res.

PCH0

VDC1

res.

NCH0

VDC2

res.

NCH1

res.

PCH2

res.

NCH2

res.

res. *

res.

Test 5

NSIN

X6

PCOS

X3

NCOS

X5

res.

Test 6 (MUX=0x40)

Calibration 3

res. *

X1

X2

res.

VTs

res.

A₄

VTth

res.

VTTFE

VTTSE

ERR

res. *

res.

A₈

res.

B₄

res.

B₈

res.

Z_In

res.

TP1

res.

ERR

res.

System Test

res. *

res.

res. *

Hints

*) Test function for iC-Haus device test only.

Table 13: Operating Modes

Mode 191/193

Mode ABZ

PA

Signal

CPD

CPU

CP

Description

In Mode ABZ A/B signals are generated and output via

PA, NA, PB and NB. A conﬁgurable zero signal is pro-

vided at pins PZ and NZ. The differential RS422 line

drivers are active; a Nx pin supplies a complementary

signal which is the inversion of pin Px.

Clock Down Pulse

Clock Up Pulse

Clock Pulse

NA

PB

NB

PZ

nU/D

MR

Count Direction (0: up, 1: down)

Asynch. Master Reset (active high)

Signal is ’1’ if index position is reached,

otherwise ’0’.

Mode 191/193

In Mode 191/193 the output pins provide control sig-

nals for counter devices compatible with 74HC191 or

74HC193 according to the following table. The driving

capability (SIK) and the slew rate (SSR) of the output

drivers must be selected so that the clock pulses can

be output with a short low pulse according to the cho-

sen minimum phase distance (see Electrical Charac-

teristics, 511).

NZ

nPL

Asynch. Parallel Load Input (active low) /

Reset (active low)

Signal is ’0’ if index position is reached,

otherwise ’1’.

Table 14: Operating mode for counter devices compat-

ible with 74HC191 or 74HC193.

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 19/37

Calibration 1, 2, 3, Test 5

System Test and Digital Calibration

These modes are used to condition the input signals This mode enables the signal conditioning to be ad-

and calibrate iC-MQF. In mode Calibration 1 the user justed using comparated sine and cosine signals. At a

can measure the IBN bias current and the zero chan- resolution of 8 the interpolator generates a switchpoint

nel analog signals are available (PCH0 and NCH0) (for every 45 degrees. The objective of the calibration pro-

zero channel calibration see page 25).

cedure is a pulse duty cycle of exactly 50% respec-

tively for A₄, B₄und A₈, B₈.

In mode Test 5 the conditioned sine and cosine signals

are output (PSIN, NSIN, PCOS and NCOS). In mode

Calibration 2 the conditioned sine and cosine signals

are output with a gain which is reduced by factor 6

(PCH1, NCH1, PCH2 and NCH2). The intermediate

potentials VDC1 and VDC2 are provided on Pin PZ

and Pin NZ if VOS12 is set to 0x3. (For a description

of the calibration process, see page 23).

System Test

PA

Signal

A₄

Description

Offset CH1

NA

A₈

Phase deviation from 90° between

CH1 and CH2

PB

NB

B₄

B₈

Offset CH2

Amplitude deviation between

CH1 and CH2

PZ

NZ

Z_In

Digital zero signal, unmasked

In mode Calibration 3 the internal temperature moni-

toring signals are provided. Calibration of the bias cur-

rent source and temperature monitoring is described

on page 17.

TP1

Veriﬁcation of line count (pulses) between

two zero pulses

Low signal: veriﬁcation running (state after

power on reset)

High signal: veriﬁcation ﬁnished

An error messaging at ERR is valid after the

second zero signal (enable required).

TEST 6

The following settings are required for mode System Test:

MODE = 0x0B, SELRES = 0x0002, SELHYS = 0xF,

CFGABZ(7:4) = ’0000’

The input voltages at the pins X3 to X6 can be checked

in mode Test 6. The following settings are required

here:

Table 15: Digital Calibration Signals

• MUX = 0x40

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 20/37

INPUT CONFIGURATION AND SIGNAL PATH MULTIPLEXER

All input stages are conﬁgured as instrumentation am- Voltage Signals

pliﬁers and thus directly suitable for differential input In V mode an optional voltage divider can be selected

signals. Referenced input signals can be processed; which reduces unacceptably large input amplitudes to

input X2 can be conﬁgured as a reference input. Both ca. 25 %. The circuitry is equivalent to the resistor

current and voltage signals can be processed, se- chain in I mode; the pad wiring resistor is considerably

lected using R12 and R0.

larger here, however.

R12

Addr 0x05, bit 3:0

R0

Addr 0x04, bit 3:0

Code

–000

–010

–100

–110

1—1

0—1

Nominal Rin() Internal Rui()

I/V Mode

1.7 kΩ

2.5 kΩ

3.5 kΩ

4.9 kΩ

20 kΩ

1.6 kΩ

2.3 kΩ

3.2 kΩ

4.6 kΩ

5 kΩ

current input

voltage input 4:1*

voltage input 1:1

high

1 MΩ

impedance

Notes

When using X2 as reference input for single-ended

signals use R12 = R0.

Figure 4: Signal conditioning input circuit.

*) VREFin is the voltage divider’s footpoint. Input

currents may be positive or negative (Vin > VREFin,

or Vin < VREFin)

Current Signals

In I Mode an input resistor Rin() becomes active at

each input pin, converting the current signal into a volt-

age signal. Input resistance Rin() consists of a pad

wiring resistor and resistor Rui() which is linked to the

adjustable bias voltage source VREFin().

Table 16: I/V Mode and Input Resistance

BIAS12

BIAS0

Code

0

Addr 0x05, bit 6

Addr 0x04, bit 6

Function

The table besides shows the possible selections, with

Rin() giving the typical resulting input resistance (see

Electrical Characteristics for tolerances). The input re-

sistor should be set in such a way that intermediate

potentials VDC1 and VDC2 lie between 125 mV and

250 mV (veriﬁable in mode Calibration 2).

VREFin = 2.5 V

for low-side current sinks (e.g. photodiodes with

common anode at GNDS)

1

VREFin = 1.5 V

for high-side currrent-sources (e.g. photodiodes

with common cathode at VDDS)

for voltage sources versus ground

(e.g. iC-SM2, Wheatstone sensor bridges)

for voltage sources with low-side reference

(e.g. iC-LSHB, when using BIASEX = 11)

NB. The input circuit is not suitable for back-to-back

photodiodes.

Notes

When using X2 as reference input for single-ended

signals use BIAS12 = BIAS0.

Table 17: Reference Voltage

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 21/37

Signal Path Multiplexer

for index channel CH0 are always connected to the

The Pins X2 to X6 are assigned to the internal chan- pins X1 and X2.

nels CH1 and CH2 according to Table 18, the signals

MUX(6:0)

Adr 0x03, bit 6:0

Code

Function

PCH0i

X1

NCH0i

X2

PCH1i

X4

NCH1i

PCH2i

NCH2i

MUX(2:0)

Adr 0x03, bit 2:0

any

Fixed assignment

0

Differential input conﬁguration

Single crossing

X6

X5

X3

X2

X3

X5

X3

X5

X6

X2

2

3

Double crossing

4

Single-ended input conﬁguration

Single crossing

7

MUX(3)

Adr 0x03, bit 3

0

Default assignment

Index signal inversion

Adr 0x03, bit 5:4

→ PCH0o

→ NCH0o

→ PCH0o

1

MUX(5:4)

0

2

Default assignment

X2

X2 Output function:

internal VREF_inis output to X2

VREF_in→X2

3

X2 Reference function:

external VREF_exsupplies X2 and

replaces internal VREFin

X2←VREF_ex

MUX(6:0)

Adr 0x03, bit 6:0

Function

Code

Pin PZ

X1

Pin NZ

X2

Pin PA

PCH1o

X4

Pin NA

NCH1o

X6

Pin PB

PCH2o

X3

Pin NB

NCH2o

X5

Default assignment

0x40

TEST 6 (MODE = 0x6)

OpAmp bypass function

Notes re. MUX(6:0)

Settings which are not explicitly speciﬁed may lead to an undesired chip function.

Table 18: Input Multiplexer Function, Input Signal Mode, and Reference Selection

5V

VDDS= 4.25 V

4V

3V

2V

1V

VCM 3.75 V

2.75 V

+IN

VCM 2.625 V

VCM

+IN

-IN

VIN 1 V max.

VIN 250 mV max.

VCM 1.125 V

1 V

VCM 0.75 V

GNDS 0.25 V

V-Mode 1:1

V-Mode 4:1

VREFin 1.5 V

VREFin 1.5 V or 2.5 V

NB: VREFin is referenced to GNDS.

Figure 5: Permissible common mode range and maximum input signal for lowest gain (GR12 = 0x0,

GF1, GF2 = 0x00); left side: voltage input 1:1, right side: voltage input 4:1.

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 22/37

5V

VDDS= 4.25 V

4V

VCM 3.75 V

VIN 1 V max.

3V

2V

1V

2.75 V

+IN

VCM

VCM 2.25 V

-IN

VCM 1.75 V

1.75 V

VCM 0.75 V

1 V

GNDS 0.25 V

V-Mode 4:1

VREFex 0.5 V

(BIASEX = 11)

V-Mode 4:1

VREFex 0.75 V

(BIASEX = 11)

V-Mode 4:1

VREFex 1.5 V

(BIASEX = 11)

- or -

VREFex 2.5 V

(BIASEX = 11)

- or -

VREFin 1.5 V

VREFin 2.5 V

NB: VREFex and VREFin are referenced to GNDS.

Figure 6: Permissible common mode range for voltage input 4:1 in dependancy to the reference voltage.

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 23/37

SIGNAL CONDITIONING CH1, CH2

GR12

Code

0x0

Adr 0x0a, bit 2:0

It is recommended to use operating mode Test 5 for

the calibration of the sine signals. The sine signals are

also available in operating mode Calibration 2 for rea-

sons of compatibility to iC-MQ, but the amplitudes are

smaller (approx. 50% with respect to operating mode

Test 5).

Range R12=0x9

3.0

12.0

24.6

31.8

40.2

52.2

63.0

79.2

96.0

0x1

6.0

0x2

7.8

0x3

10.2

13.2

15.6

19.8

24.0

0x4

0x5

Alternatively, characteristic digital test signals are

available for offset, amplitude and phase conditioning

in operating mode System Test.

0x6

0x7

Notes

Valid for all operation modes except for

Calibration 2 (reduces gain to 1/6).

Gain Settings

The gain is set in four steps:

Table 19: Gain Range CH1, CH2 (coarse)

1. The sensor supply controller is shut down and the

constant current source for the ACO output is set to

a suitable output current (register ACOT = 0x2, ACOR

and ACOS values close to the later operating point).

GF2

Code

0x00

0x01

...

Adr 0x0c, bit 4:0

Factor

1.00

1.06

6.25^GF2

31

2. The coarse gain GR12 is selected so that differential

signal amplitudes of ca. 6 Vpp are produced in opera-

tion mode Test 5 (signal PSIN versus NSIN and PCOS

versus NCOS).

0x1F

6.25

Table 20: Fine Gain Factor CH2

3. Using ﬁne gain factor GF2 the cosine signal ampli-

tude is then adjusted to exactly 6 Vpp.

GF1

Adr 0x0b, bit 6:0, Adr 0x0a, bit 7:4

Code

0x000

0x001

...

Factor

1.0

4. The sine signal amplitude can then be adjusted to

the cosine signal amplitude via ﬁne gain factor GF1.

1.0009

GF1

1984

6.25

0x7FF

6.6245

This results in a total gain of GR12 * GFi for differential

input signals.

Table 21: Fine Gain Factor CH1

1.5

6

iC-MQF

Test 5

Px

Nx

VPNx

R0

VPx

VNx

GND

Figure 7: Deﬁnition of 6 Vpp signal. Termination R0

must be high-ohmic during all Test and

Calibration modes.

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 24/37

Offset Calibration CH1, CH2

The offset calibration range for CH1 and CH2 is set

In order to calibrate the offset the reference source using OR1 and OR2. Both sine and cosine signals are

must ﬁrst be selected using VOS12. Two ﬁxed voltages then calibrated using factors OF1 and OF2. The cal-

and two dependent sources are available for this pur- ibration target is reached when the DC fraction of the

pose. The ﬁxed voltage sources should be selected for differential signals PCHi versus NCHi is zero.

external sensors which provide stable, self-regulating

signals.

OR1

OR2

Code

0x0

Addr 0x10, bit 1:0

Addr 0x10, bit 3:2

So that photosensors can be operated in optical en-

coders iC-MQF tracks changes in offset voltages via

the signal-dependent source VDC when used in con-

junction with the controlled sensor current source for

LED supply (pin ACO). The VDC potential automati-

cally tracks higher DC photocurrents. To this end inter-

mediate potentials VDC1 and VDC2 must be adjusted

to a minimal AC ripple using the selectable k factor (this

calibration must be repeated when the gain setting is

altered).

Range

x1

0x1

x2

0x2

x6

0x3

x12

Table 24: Offset Range CH1, CH2

OF1

OF2

Code

0x000

0x001

...

Addr 0x11, bit 6:0; Addr 0x10, bit 7:4

Addr 0x13, bit 2:0; Addr 0x12, bit 7:0

Factor

Code

0x400

0x401

...

Factor

0

The feedback of pin voltage V(ACO) fulﬁlls the same

task as source VDC when MR bridge sensors are sup-

plied by the controlled sensor current source or by sup-

ply VDDS.

0

0.00098

+ Code / 1023

− 0.00098

− (Code - 1024)

/ 1023

0x3FF

1

0x7FF

− 1

VOS12

Code

0x0

Addr 0x05, bit 5:4

Type of source

Table 25: Offset Factors CH1, CH2

Feedback of ACO pin voltage: V(ACO)/20

for supply-dependent differential voltage signals

for Wheatstone sensor bridges

Phase Correction CH1 vs. CH2

The phase shift between CH1 and CH2 can be ad-

justed using parameter PH12. Following phase cal-

ibration other calibration parameters may have to be

readjusted (those as amplitude compensation, inter-

mediate potentials and offset voltages).

to measure VDDS

0x1, 0x2

Fixed reference: V05 of 500 mV, V025 of 250 mV

for single-ended current or voltage signals

for single-ended or differential stabilized signals

(regulated sensor or waveform generator)

0x3

Self-tracking sources VDC1, VDC2 (125...250 mV)

for differential current signals

PH12

Code

0x000

0x001

...

Addr 0x14, bit 5:0; Addr 0x13, bit 7:4

for differential voltage signals*

Correction angle

0 °

Code

0x200

0x201

...

Correction angle

0 °

Notes

*) Requires MUX(5:4) = 3 and the sensor’s

reference connected to input X2; refer to Elec.

Char. No. 105 for acceptable input voltage).

+ 0.0204 °

− 0.0204 °

− 10.42 ° ·

+ 10.42 ° ·

Table 22: Offset Reference Source CH1, CH2

PH12 /511

(PH12 - 512) /511

0x1FF

+ 10.42 °

0x3FF

− 10.42 °

VDC1

Addr 0x0E, bit 1:0; Addr 0x0D, bit 7:0

Addr 0x0F, bit 5:0; Addr 0x0E, bit 7:4

VDCi = (1 − k) · VPi + k · VNi

k = 1/3

VDC2

Code

0x000

0x001

...

Table 26: Phase Correction CH1 vs. CH2

k = 0.3386

k = 1/3 + 1/3 · Code/1023

k = 0.5000 (center setting)

...

0x200

...

0x3FF

Notes

k = 2/3

Adjustment is required only if VOS12 = 0x3

Table 23: Intermediate Voltages CH1, CH2

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 25/37

SIGNAL CONDITIONING CH0

The voltage signals needed to calibrate the zero chan- Offset Calibration CH0

nel are available in mode Calibration 1. The relative The offset reference source is selected with VOS0.

phase position of the ungated zero signal Zin com- The offset compensation is set with OR0 and OF0 (see

pared to A and B can be determined in mode System Offset Calibration CH1 and CH2 for further informa-

Test.

tion).

Gain Settings CH0

The CH0 gain is set in the following steps:

VOS0

Code

0x0

Addr 0x04, bit 5:4

Source

0.05 · V(ACO)

0.5 V

1. The sensor supply controller is shut down and the

constant current source for the ACO output is set to

the same values as during the calibration of CH1 and

CH2 (registers ACOT, ACOR and ACOS).

0x1

0x2

0.25 V

0x3

VDC1

Table 29: Offset Reference Source CH0

2. The coarse gain is selected so that a differential sig-

nal amplitude of ca. 1 Vpp is produced internally (sig-

nal PCH0 versus NCH0).

OR0

Code

0x0

Addr 0x07, bit 1:0

Range

x1

3. GF0 then permits ﬁne gain adjustment to 1 Vpp. The

total gain is accrued from GR0 x GF0.

0x1

x2

0x2

x6

0x3

x12

GR0

Code

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

Addr 0x07, bit 6:4

Range R0 = 0x9

Table 30: Offset Range CH0 (coarse)

0.5

1.0

1.3

1.7

2.2

2.6

3.3

4.0

2.0

4.1

OF0

Code

0x00

0x01

...

Addr 0x09, bit 5:0

5.3

Factor

Code

0x20

0x21

...

Factor

6.7

0

8.7

0.0322

+ Code /31

1

− 0.0322

− (Code - 32 ) /31

− 1

10.5

13.2

16.0

0x1F

0x3F

Table 31: Offset Factor CH0 (ﬁne)

Table 27: Gain Range CH0

GF0

Code

0x00

0x01

...

Addr 0x08, bit 4:0

Factor

1.00

1.06

6.25^GF0

31

0x1F

6.25

Table 28: Fine Gain Factor CH0

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 26/37

SIGNAL LEVEL CONTROL and SIGNAL MONITORING

iC-MQF’s signal level controller can keep the input sig- set and phase correction values without interference

nals for the sine-to-digital converter constant, regard- by signal level controlling.

less of temperature and aging effects, when using con-

trol output ACO for tracking the sensor supply.

Addr 0x15, bit 5:1

ACOS (4:0)

ACOR(1:0) presets the output current range of pin

ACO, the control’s highside current source output, and

ACOT(1:0) deﬁnes its control mode.

Code

0x00

0x01

...

Square control ACOT = 00

Vpp() ≈ 1800 mV (60 %)

Vpp() ≈ 1830 mV (61 %)

...

77

≈ 1800 mV _{77−(1.25∗Code)}

The resulting internal signal amplitude and the con-

trol’s operating range are both monitored and thus can

be used for error messaging.

0x19

...

Vpp() ≈ 3000 mV (98 %)

...

0x1F

Vpp() ≈ 3600 mV (120 %)

Addr 0x15, bit 7:6

Table 34: Square Control Setpoint (internal sin/cos

signal amplitude)

ACOR (1:0)

Code

00

Function

5 mA - Range

10 mA - Range

25 mA - Range

50 mA - Range

01

10

11

Table 32: ACO Output Current Range (applies for con-

trol modes and constant current source)

Addr 0x16, bit 1:0

ACOT (1:0)

Code

00

Function

Sine/cosine square control

Sum control

01

10

Constant current source

Not permitted (device test only)

11

Figure 8: Signal monitoring and test signals in

Test 5 mode (example for ACOS(4:0) =

0x19).

Table 33: ACO Output Control Mode

Notice: Excessive input signals or internal signal clipping

can interfere control operation, so that the preset operating

point may not be reached (upon power up) or maintained

(upon disturbances). Use Control Error 2 and Signal Error 1

for monitoring and conﬁgure EMASKA accordingly.

Signal monitoring and limits

ADJ (4:0)

0x00

0x01

...

Vt()min ... max

0.72 V...2.34 V

0.732 V...2.38 V

...

ADJ (4:0)

0x19

...

Vt()min ... max

1.2 V ...3.9 V

...

The standard control mode is square control which

uses (sine² + cosine²) to adjust the ACO output current.

ACOS(4:0) determines the internal signal amplitudes

within the closed-loop control and, simultaneously, the

amplitude monitoring thresholds. The ideal setpoint

here is 3 Vpp referred to the sin/cos test signals avail-

able in operating mode Test 5.

0x1F

1.44 V...4.68 V

Notes

All values nominal, see also Elec. Char. Nos. 605,

606

Table 35: Signal Monitoring

The signal monitoring thresholds are tracked accord-

ing to ACOS (4:0) and ﬁt for square control mode.

When using sum control mode a different operating

point can be required for which the monitoring thresh-

olds may not be suitable. In this case signal monitoring

With sum control mode selected, the DC references

(VDC1 + VDC2) are used to adjust the output current

of pin ACO.

The constant current source is intended for signal con- should be disabled via the error mask (see EMASKA

ditioning purposes, i.e. for the adjustment of gain, off- etc.).

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 27/37

Addr 0x15, bit 5:1

ACOS (4:0)

Code

0x00

ACOS (4:0)

Code

0x00

Sum control ACOT = 01

VDC1 + VDC2 ≈ 245 mV

VDC1 + VDC2 ≈ 249 mV

...

Constant current source ACOT = 10

I(ACO) ≈ 3.125% Isc(ACO)

I(ACO) ≈ 6.25% Isc(ACO)

0x01

77

...

≈ 245mV _{77−(1.25∗Code)}

...

≈ 3.125% ∗ (Code + 1) ∗ Isc(ACO)

0x1F

I(ACO) ≈ 100% Isc(ACO)

See Elec. Char. No. 602 for Isc(ACO)

0x1F

VDC1 + VDC2 ≈ 490 mV

Notes

Table 36: Sum Control Setpoint (DC average)

Table 37: Current Source Setpoint (ACO output cur-

rent)

SINE-TO-DIGITAL CONVERSION

SELRES

Addr 0x21, bit 6:0; Addr 0x20, bit 7:0

iC-MQF’s converter resolution is selected with SEL-

RES. For a resolution of 4, four angle steps per in-

put signal period are generated so that the switching

frequency at the A and B output matches the sine fre-

quency at the input.

Value

STEP

IPF

ﬁn()max

Angle Steps

Per Period

Interpolation

Factor

Permissible Input

Frequency

(@ MTD)

0x0001

0x0002

0x0004

0x0005

0x0008

0x000A

0x0014

0x0019

0x0028

0x0032

0x0064

0x007D

0x00C8

0x00FA

0x01F4

0x03E8

Notes

4

1

200 kHz (0x1)

166 kHz (0x1)

133 kHz (0x1)

83 kHz (0x1)

66 kHz (0x1)

20 kHz (0x4*)

16 kHz (0x4*)

7.1 kHz (0x6*)

5.7 kHz (0x6*)

2.5 kHz (0x7*)

0.8 kHz (0x8*)

8

2

The programmable converter hysteresis is determined

by SELHYS. It is set in multiples of the increment size

and may have a maximum of 45° of the input signal

period.

16

4

20

5

32

8

40

10

20

25

40

50

100

125

200

250

500

1000

80

SELHYS

Code

0x0

Addr 0x1F, bit 3:0

100

160

200

400

500

800

1000

2000

4000

Function

nearly none

0.09°

Code

Function

2.0°

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

0x1

4.0°

0x2

0.18°

6.0°

0x3

0.36°

8.0°

0x4

0.45°

10.0°

11.25°

22.5°

45°

0x5

0.72°

0x6

1.0°

0x7

1.5°

Other settings are not allowed.

*) Recommended MTD setting, refer to Design

Review page 36.

Table 39: Converter Hysteresis

Table 38: Converter Resolution

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 28/37

OUTPUT SETTINGS AND ZERO SIGNAL

The interpolation factor IPF determines the number of Zero Signal Generation

A/B signal cycles per input signal period. These A/B The generation of the zero signal is dependant on the

signal cycles are counted in the internal register POS, internal signal Z_Inwhich is produced by comparing the

which can be used to blank the zero pulse.

calibrated CH0 input signals. The offset calibration of

CH0 inﬂuences the width of the Z_Insignal. The correct

POS is set to 0 if the input sine/cosine phase angle is position of Z_Inshould be checked before conﬁguring

zero degrees, its maximum value is POS_max= IPF-1. the zero signal blanking logic. This is possible by com-

The internal A/B signal cycle adheres to the following paring the Z_Insignal with the PA/PB signals in Mode

pattern:

ABZ: Z_Inis displayed on pin ERR if EMASKA = 0x010

and EMTD = 0x0 is programmed.

A 1 1 0 0

B 1 0 0 1

Table 40: Internal A/B Signal Cycle

Inversions and reversals can be selected for the output

of the A/B/Z signals and the zero signal can be blanked

with any combination of the internal A and B signal by

programming parameter CFGABZ.

Figure 10: Signal path from Z_Into PZ/NZ

CFGABZ

Addr 0x1D, bit 7:0

Bit

7

Function and Description

The blanking of the Z_Insignal by CFGZPOS is relative

to the internal A/B cycle count POS. Multiple settings

of CFGZPOS are possible at high resolutions, choose

a setting which centers the output signal PZ in relation

to Z_In. Attention: Programming CFGZPOS to a cycle

count larger than POS_maxleads to undetermined zero

signal prevention.

Output inversion for channel A: PA<>NA

PA = P1i xor CFGABZ(7)

6

5

4

Output inversion for channel B: PB<>NB

PB = P2i xor CFGABZ(6)

Output inversion for index channel: PZ<>NZ

PZ = P0i xor CFGABZ(5)

Exchange of the A/B signals

0: P1i = A, P2i = B

1: P1i = B, P2i = A

CFGZPOS Addr 0x1E, bit 7:0

Zero Signal Blanking CFGABZ(3:0)

Enable for A = 1, B = 1

Bit

7

Description

3

2

1

0

0: Mask not used

Enable for A = 1, B = 0

1: Mask Enable

(zero signal blanking with POS enabled)

Enable for A = 0, B = 0

Enable for A = 0, B = 1

(6:0)

For IPF < 200:

blanking of Z_Inif POS = CFGZPOS(6:0)

For IPF≥ 200:

Table 41: Output Logic

blanking of Z_Inif POS = 8 * CFGZPOS(6:0)

Table 42: Zero Signal Positioning

ENZFF

Addr 0x02, bit 4

Code

Description

0

1

Zero signal output with state change of P0i

Zero signal output synchronized with A/B signal

Table 43: Zero Signal Synchronization

Figure 9: Signal Path from A and B to PA/NA and

PB/NB

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 29/37

CFGOSZ

Code k

0x0

Addr 0x25, bit 2:0

Output Driver Conﬁguration

Code k

0x4

The output drivers can be used as push-pull, lowside

or highside drivers; the mode of operation is deter-

mined by TRIHL(1:0).

140 %

130 %

120 %

110 %

105 %

100 %

92 %

n/a

0x1

0x5

0x2

0x6

0x3

0x7

The slew rate can be set using SSR to suit the length

of the cable. Lower slew rates are used to avoid steep

edges when transmitting via short wires, but can re-

sult in a limiting of the maximum permissible output

frequency. (For example, this frequency is 300 kHz at

a slew rate of 300 ns if the RS422 speciﬁcation is to be

adhered to. (the tolerances in Electrical Characteris-

tics, numbers 506/507, must be observed)).

Table 47: Calibration of MTD Oscillator

The calibration must be executed in Mode 191/193

with register MTD(3:0) = 0x0F. Apply a sine signal at

the inputs X3 to X6 and observe the length of the low

pulses at pin PB. The setting of CFGOSZ is correct if

the observed tclk()lo is close to the nominal value of

Elec. Char. no. 511.

The short-circuit current can be set by SIK and can be

minimized when connecting to on board logic or to an

external 24 V line driver. If the outputs are used as

RS422-compatible 5 V drivers, it is recommended that

SIK = 11 to keep the power dissipation of iC-MQF low.

MTD

Code

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

Note

Addr 0x1F, bit 7:4

Mode ABZ: t_MTD

not available

50 ns

Mode 191/193: tclk()lo

not available

50 ns

75 ns

TRIHL

Code

00

Addr 0x22, bit 1:0

100 ns

Function

125 ns

62.5 ns

150 ns

75 ns

Push-pull operation

175 ns

87.5 ns

01

Highside driver mode (P channel open drain)

Lowside driver mode (N channel open drain)

Not permitted

200 ns

100 ns

10

11

300 ns

150 ns

400 ns

200 ns

Table 44: Output Drive Mode

600 ns

300 ns

800 ns

400 ns

1.0 µs

500 ns

SSR

Code

00

Addr 0x22, bit 3:2

Function

1.2 µs

600 ns

1.4 µs

700 ns

Nominal value 12 ns

Nominal value 25 ns

Nominal value 80 ns

Nominal value 220 ns

See Elec. Char. 505/ 506

1.6 µs

800 ns

01

All timing speciﬁcations are nominal values, see

Elec. Char. 514 for tolerances.

10

11

Note

Table 48: Minimum Transition Distance

Table 45: Output Slew Rate

If CFGOSZ(2:0) is set correctly, the minimum tran-

sition distance of the output signals can be preset

by MTD(3:0). This setting limits the maximum possi-

ble output frequency to ensure a safe transmission to

counters, which permit only a low input frequency and

thus cannot debounce spikes. The conﬁguration of the

RS422 output drivers (with regard to the driver current

and slew rate) and the cable length must be taken into

account when choosing the minimum edge distance.

SIK

Code

00

Addr 0x22, bit 5:4

Function

typ. 2 mA, linking logic or driver ICs

typ. 8 mA

01

10

typ. 40 mA

11

typ. 100 mA, recommended for RS422

See Elec. Char. 503/ 504

Note

Table 46: Output Short-Circuit Current

Signal Filter

Minimum Transition Distance

Register CFGOSZ(2:0) calibrates the timing of t_MTD

the minimum transition distance in Mode ABZ, and

tclk()lo, the low pulse duration of the clock signals in

Mode 191/193 (see Elec.Char., no. 511 and no. 514).

ENF

Code

0

Addr 0x03, bit 7

,

Function

Disabled

1

Noise limiting signal ﬁlter enabled (default)

Table 49: Noise Filter

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 30/37

ERROR MONITORING AND ALARM OUTPUT

EMASKA

Addr 0x18, bit 1:0; Addr 0x17, bit 7:0

Error event

iC-MQF monitors the input signals, the internal inter-

polator and the sensor supply controller via which the

input signal levels are stabilized. If the sensor supply

tracking unit reaches its control limits this can be inter-

preted as an end-of-life message, for example.

Bit

9

Line count error (wrong count of sine periods

between two zero pulses)

8

Temporal tracking error (out-of-sync: position output

differs from actual angle, e.g. after cycling power)

7

Loss of tracking (excessive input frequency)

6 *

Conﬁguration error

(SDA or SCL pin error, no acknowledge signal from

EEPROM or invalid check sum)

Three separate error masks stipulate whether error

events are signaled as an alarm via I/O pin ERR (mask

EMASKA), whether they cause the RS422 line drivers

to shutdown or not (mask EMASKO) or whether they

are stored in the EEPROM (mask EMASKE).

5

4

Excessive temperature warning

Ungated index enable signal Z_In

(comparated X1/X2 inputs for CFGABZ and

CFGZPOS adjustment, at EMTD = 0x0)

3

2

1

0

Control error 2: range at max. limit

Control error 1: range at min. limit

Signal error 2: clipping

Alarm Output: I/O-pin ERR

Signal error 1: loss of signal (poor differential

amplitude**, wrong s/c phase)

Pin ERR is operated by a current-limited open-drain

output driver and has an internal pull-up which can be

disabled. The ERR pin also acts as an input for exter-

nal system error messaging and for switching iC-MQF

to test mode for which a voltage of larger than VTMon

must be applied (see page 33). Interpretation of an

external system error message and the phase of the

message output is conﬁgured by EPH, the minimum

indication time by EMTD.

Code

1

Function

Enable: event changes state of pin ERR

(if EMASKO does not disable the output function).

0

Disable: event does not affect pin ERR.

Notes

*) Pin ERR can not pull low on conﬁguration error,

use high-active error logic instead (EPH = 1);

**) Also due to excessive input signals or internal

signal clipping.

Table 53: Error Mask Alarm Output ERR

EPH

Code

0

Addr 0x1A, bit 4

State on error

active low

State w/o error

Line Count Error

high impedance,

with input function for a

low-active system error;

Line count monitoring is particularly interesting for en-

coder systems. iC-MQF counts the number of sine cy-

cles between two adjacent zero pulses and compares

it to the reference value LINECNT. In case of a devi-

ation the line count error is set. The check is paused

if the direction of rotation changes, and is restarted on

the next zero pulse. During mode System Test signal

TP1 indicates when a ﬁrst line count check has ﬁn-

ished.

1

high impedance

active low

Table 50: I/O Logic, Alarm Output ERR

EMTD

Code

0x0

Addr 0x18, bit 6:4

Indication Time

0 ms

Code

0x4

0x5

0x6

0x7

Indication Time

50 ms

LINECNT

Code

Addr 0x24, bit 5:0; Addr 0x23, bit 7:0

0x1

12.5 ms

25 ms

62.5 ms

75 ms

Function Value

Line Count (CPR)

0x2

0x0000

...

0

1

0x3

37.5 ms

87.5 ms

...

Code + 1

16384

0x3FFF

Example

16383

Table 51: Min. Indication Time, Alarm Output ERR

Code disc of 256 CPR → LINECNT = 255

Table 54: Line Count Reference

EPU

Code

0

Addr 0x1A, bit 5

Function

Excessive Temperature Warning

No internal pull-up

If the temperature warning threshold is exceeded, an

excessive temperature message is generated which is

processed in the temperature monitor block (T_wcorre-

sponds to T₂).

1

Internal 300 µA pull-up current source active

Table 52: Pull-Up Enable, Alarm Output ERR

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 31/37

Exceeding the temperature warning threshold can be Error Protocol

signaled at pin ERR or used to shut down the line Out of the errors enabled by EMASKE both the ﬁrst

drivers (via mask EMASKO). The temperature warn- (under ERR1) and last error (under ERR2) which occur

ing is deleted when the temperature drops below T_w

-T_hys

after the iC-MQF is turned on are stored in the EEP-

ROM.

.

Excessive Temperature Shutdown

If the temperature shutdown threshold T_off= T_w+ ∆ T

The EEPROM also has a memory area in which all oc-

curring errors can be stored (ERR3). Only the fact that

is exceeded the line drivers are shut down independent an error has occurred can be recorded, with no infor-

of EMASKO.

mation as to the time and count of appearance of that

error given. Error recording can be used to statistically

evaluate the causes of system failure, for example.

Driver Shutdown

EMASKE

Addr 0x1C, bit 1:0; Addr 0x1B, bit 7:0

Error event

PDMODE

Addr 0x1A, bit 6

Bit

Code

Function

9

Line count error

—

0

1

Driver shutdown terminates with the error event

Permanent driver shutdown until cycling power

8

7

Loss of tracking

—

6

Table 55: Driver Activation

5

Excessive temperature warning

System error

4

EMASKO

Addr 0x1A, bit 1:0; Addr 0x19, bit 7:0

Error event

3

Control error 2

Bit

9

2

Control error 1

Line count error (wrong count of sine periods

between two zero pulses)

1

Signal error 2

0

Signal error 1

8

Temporal tracking error (out-of-sync: position output

differs from actual angle, e.g. after cycling power)

Code

Function

1

0

Enable: event will be latched

Disable: event will not be latched

7

Loss of tracking (excessive input frequency)

6 *

Conﬁguration error (ROM bit ﬁx on 1)

SDA or SCL pin error, no acknowledge signal from

EEPROM or invalid check sum

Table 57: Error Mask EEPROM Savings

5

4

Excessive temperature warning

System error: I/O pin ERR pulled to low by an

external error signal (only permitted with EPH = 0)

ERR1

ERR2

ERR3

Bit

Addr 0x31, bit 1:0; Addr 0x30, bit 7:0

Addr 0x32, bit 3:0; Addr 0x31, bit 7:2

Addr 0x33, bit 5:0; Addr 0x32, bit 7:4

Error Event

3

2

1

0

Control error 2: range at max. limit

Control error 1: range at min. limit

Signal error 2: clipping

6:0

Assignation according to EMASKE

Signal error 1: loss of signal (poor differential

amplitude**, wrong s/c phase)

Code

Function

Code

1

Function

0

1

No event

Enable: event resets pin ACO to the 5 mA range,

tristates the line driver outputs and pin ERR (i.e.

low-active error messages can not be displayed)

Registered error event

Table 58: Error Protocol

0

Disable: output functions remain active

Notes

*) The conﬁguration error is always enabled.

**) Also due to excessive input signals or internal

signal clipping.

Table 56: Error Mask Driver Shutdown

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 32/37

REVERSE POLARITY PROTECTION

iC-MQF is protected against a reversal of the supply The following pins are also reverse polarity protected:

voltage and has short-circuit-proof, error-tolerant line PA, NA, PB, NB, PZ, NZ, ERR, VDD, GND and ACO.

drivers. A defective device cable or one wrongly con-

nected is tolerated by iC-MQF. All circuitry components Conditions: This is based on the condition that GNDS

which draw the monitored supply voltage from VDDS only receives load currents from VDDS. The maxi-

and GNDS are also protected.

mum voltage difference between GNDS and another

pin should not exceed 6 V, the exception here being

pin ERR (see Test Mode page 33).

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 33/37

TEST MODE

EMODE

Addr 0x1C, bit 6:4

iC-MQF switches to test mode if a voltage larger

than VTMon is applied to pin ERR (precondition:

EMODE(0) = 1). In response iC-MQF transmits its

conﬁguration settings as current-modulated data us-

ing I/O pin ERR either directly from the RAM (for

EMODE(2) = 1) or after re-reading the EEPROM (for

EMODE(2) = 0). If the voltage at pin ERR falls below

VTMoff, test mode is terminated and data transmission

aborted.

Code 2:0

Function during test

mode

Function following test

mode

000

010

Normal operation

Repeated read out of

EEPROM

001

Transmission of error

and EEPROM OEM

data (address range

0x24 to 0x7F)

Repeated read out of

EEPROM

011

101

Transmission of

EEPROM contents

(0x0-0x7F)

Repeated read out of

EEPROM

The clock rate for the data output is determined by

ENFAST. Two clock rates can be selected: 780 ns for

ENFAST = 1 or 3.125 µs for ENFAST = 0 (see Electri-

cal Characteristics, B12, for clock frequency and toler-

ances).

Transmission of error

and RAM OEM data

(ENSL = 1, address

range 0x3B to 0x43)

Repeated read out of

EEPROM

111

Transmission of RAM

contents (0x0-0x7F)

(ENSL = 1)

Repeated read out of

EEPROM

Data is output in Manchester code via two clock pulses

per bit. To this end the lowside current source switches

between a Z state (OFF = 0 mA) and an L state (ON =

2 mA).

100

110

Not allowed

Table 59: Test Mode

The bit information lies in the direction of the current

source switch:

VP

U23-B

VP LM393

VP

Zero bit: change of state Z → L (OFF to ON)

7

8

6

VP

C21

100nF

C22

100nF

-

U22-S

AD8029

VN

U23-S

LM393

GND

7

One bit: Change of state L → Z (ON to OFF)

5

+

4

JP4

R24

470

ERR

Transmission consists of a start bit (a one bit), 8 data

bits and a pause interval in Z state (the timing is iden-

tical with an EEPROM access via the I²C interface).

max. 5V

VDD

M22

IRLML6401

C24

VP

R26

100pF

100k

R23

2K

C26

100nF

R28

51k

U22-A

U23-A

LM393

R25

2k

2

D21

LL4148

-

M21

6

2

DATA_ON

AD8029

NDIS

-

2N7002

3

1

DATA_OUT

+

3

Example: byte value = 1000 1010

Transmission including the start bit: 1 1000 1010

In Manchester code: LZ LZZL ZLZL LZZL LZZL

8

+

R21

475k

8

4

R27

100k

U21

LM285

VP

5

C25

100nF

R22

365k

VDD

C23

100nF

dra_mq1d_error_schem

Decoding of the data stream:

Figure 11: Example circuit for the decoding and

conversion of the current-modulated sig-

nals to logic levels.

ZZZZZZ LZ LZ ZL ZL ZL LZ ZL LZ ZL ZZZZZZ

Pause 1 1 0 0 0 1 0 1 0 Pause

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 34/37

Quick programming in the

single master system

Quick programming in the

multimaster system

For the purpose of signal conditioning it is possible to Fast programming of iC-MQF, byte for byte, is possible

reprogram iC-MQF quickly. If test mode is quit and with a multimaster-competent programming device. To

EMODE(1:0) = 00, iC-MQF reads the conﬁguration this end the integrated I²C slave mode must be en-

data in again.

abled by ENSL; iC-MQF then reacts to the device ID

0x55.

In operating modes Mode ABZ, System Test and Mode

191/193 the content of the EEPROM is read in its en-

tirety. For other modes the address area is limited to

0x0-0x31 so that the conﬁguration time for either cali-

bration or IC testing is shortened.

If no EEPROM is connected, iC-MQF automatically

sets the I²C slave mode enable (after a maximum of

150 ms, see Electrical Characteristics, D11) and deac-

tivates the digital section (ENSL = 1 and END = 0 are

set). Any number of bytes can be written at any one

time; the received data is accepted directly into the

If the setup is switched to test mode during the readin RAM register. After programming END = 1 must be

procedure, readin is aborted and only repeated once set to restart sine-to-digital conversion in the selected

test mode has been terminated.

mode of operation.

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 35/37

GENERAL APPLICATION HINTS

Refer to the datasheet of iC-MQ.

APPLICATION NOTES: SIGNAL CONDITIONING

Regarding a description of the principle signal conditioning procedure refer to the datasheet of iC-MQ.

Signal Conditioning Example 1:

Photodiode array connected to current inputs, LED supply with constant current source

Step

1.

Operating Mode

Calibration and Signal

Presets

VOS12= 0x3, GF1= 0x400, VDC1= 0x200, OF1= 0x0, GF2= 0x10, VDC2= 0x200, OF2= 0x0

Example: LED current approx. 6.25 mA

ACOT(1:0)= 0x2 (constant current source), ACOR(1:0)= 0x3 (range 50 mA), ACOS(4:0)= 0x04

(value 12.5)

2.

Calibration of Channel 1:

Test 5

Parameter GR12: Adjust the diff. signal at PA vs. NA to approx. 6 Vpp amplitude

Parameter GF1: Adjust the diff. signal at PA vs. NA to exactly 6 Vpp amplitude

Parameter VDC1: Minimize the AC fraction of VDC1 at PZ (ripple < 10 mVpeak)

Parameter OR1, OF1: Minimize the DC fraction of the diff. signal PA vs. NA (< 5 mVdc)

Calibration of Channel 2:

Test 5

Calibration 2

Test 5

3.

4.

Test 5

Parameter GF2: Adjust the diff. signal at PB vs. NB to exactly 6 Vpp amplitude

Parameter VDC2: Minimize the AC fraction of VDC2 at NZ (ripple < 10 mVpeak)

Parameter OR2, OF2: Minimize the DC fraction of the diff. signal PB vs. NB (< 5 mVdc)

Calibration 2

Test 5

System Test

1. Iteration, Calibration of Channel 1 vs. Channel 2:

Parameter OF1: Adjust duty ratio of A₄at PA to 50 %

Parameter OF2: Adjust duty ratio of B₄at PB to 50 %

Parameter PH12: Adjust duty ratio of A₈at NA to 50 %

Parameter GF1: Adjust duty ratio of B₈at NB to 50 %

5.

6.

Calibration 2

System Test

Repeated Adjustment of Intermediate Voltages, VDC1 and VDC2:

Parameter VDC1: Minimize the AC fraction of VDC1 at PZ

Parameter VDC2: Minimize the AC fraction of VDC2 at NZ

2. Iteration, Calibration of Channel 1 vs. Channel 2:

Parameter OF1: Adjust duty ratio of A₄at PA to 50 %

Parameter OF2: Adjust duty ratio of B₄at PB to 50 %

Parameter PH12: Adjust duty ratio of A₈at NA to 50 %

Parameter GF1: Adjust duty ratio of B₈at NB to 50 %

Table 60: Conditioning example 1

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 36/37

Signal Conditioning Example 2:

Encoder supplying 100 mVpp to voltage inputs

Step

1.

Operating Mode

Calibration and Signal

Presets

VOS12= 0x1, GF1= 0x400, OF1= 0x0, GF2= 0x10, OF2= 0x0

2.

Calibration of Channel 1:

Test 5

Parameter GR12: Adjust the diff. signal at PA vs. NA to approx. 6 Vpp amplitude

Parameter GF1: Adjust the diff. signal at PA vs. NA to exactly 6 Vpp amplitude

Parameter OR1, OF1: Minimize the DC fraction of the diff. signal PA vs. NA (< 5 mVdc)

Calibration of Channel 2:

Test 5

3.

4.

Test 5

Parameter GF2: Adjust the diff. signal at PB vs. NB to exactly 6 Vpp amplitude

Parameter OR2, OF2: Minimize the DC fraction of the diff. signal PB vs. NB (< 5 mVdc)

Test 5

System Test

Calibration of Channel 1 vs. Channel 2:

Parameter OF1: Adjust duty ratio of A₄at PA to 50 %

Parameter OF2: Adjust duty ratio of B₄at PB to 50 %

Parameter PH12: Adjust duty ratio of A₈at NA to 50 %

Parameter GF1: Adjust duty ratio of B₈at NB to 50 %

Table 61: Conditioning example 2

APPLICATION NOTES: CIRCUIT EXAMPLES

Refer to the datasheet of iC-MQ.

DESIGN REVIEW: Function Notes

iC-MQF 3

No.

1

Function, Parameter/Code

SELRES, MTD

Description and Application Notes

Recommended settings for resolution and minimum transition distance:

STEP 400: t_MTD≥ 125 ns (MTD 0x4)

STEP 800, 1000: t_MTD≥ 175 ns (MTD 0x6)

STEP 2000: t_MTD≥ 200 ns (MTD 0x7)

STEP 4000: t_MTD≥ 300 ns (MTD 0x8)

2

EMASKA, EMASKO, EMASKE

Error monitoring is not operational for:

temporal tracking error, and loss of tracking

Table 62: Notes on chip functions regarding iC-MQF chip release 3.

iC-Haus expressly reserves the right to change its products and/or speciﬁcations. An info letter gives details as to any amendments and additions made to the

relevant current speciﬁcations on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by

email.

Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.

iC-Haus does not warrant the accuracy, completeness or timeliness of the speciﬁcation and does not assume liability for any errors or omissions in these

materials.

The data speciﬁed is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, ﬁtness

for a particular purpose or of any other nature are made hereunder with respect to information/speciﬁcation or the products to which information refers and no

guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of

the product.

iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade

mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.

iC-MQF PROGRAMMABLE 12-BIT

Sin/Cos INTERPOLATION IC WITH RS422 DRIVER

Rev A1, Page 37/37

ORDERING INFORMATION

Type

Package

Options

Order Designation

iC-MQF

TSSOP20

iC-MQF TSSOP20

iC-MQF TSSOP20 ET -40/100

temperature range -40 °C to +100 °C

Evaluation Board

iC-MQF EVAL MQ1D

For technical support, information about prices and terms of delivery please contact:

iC-Haus GmbH

Tel.: +49 (0) 61 35 - 92 92 - 0

Fax: +49 (0) 61 35 - 92 92 - 192

Web: http://www.ichaus.com

E-Mail: sales@ichaus.com

Am Kuemmerling 18

D-55294 Bodenheim

GERMANY

Appointed local distributors: http://www.ichaus.com/sales_partners


型号：	IC-MQF
厂家：	IC-HAUS GMBH
描述：	PROGRAMMABLE 12-BIT Sin/Cos INTERPOLATION IC WITH RS422 DRIVER 可编程的12位正弦/余弦插值用IC RS422驱动器驱动器
文件：	总37页 (文件大小：754K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IC-MQF [ICHAUS]

相关型号：

IC-MQTSSOP20

IC-MR

IC-MSA

IC-MSB

IC-MSB2

IC-MSB2EVALMSB1D

IC-MSB2TSSOP20

IC-MSBEVALMSB1D

IC-MSBTSSOP20

IC-MSBTSSOP20-TP

IC-MU

IC-MU_13