ICS83940DYI-01T [ICSI]
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER; 低偏移， 1 - TO- 18 LVPECL - TO- LVCMOS / LVTTL扇出缓冲器
| 型号： | ICS83940DYI-01T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER |
| 文件： | 总13页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS83940I-01
Integrated
Circuit
Systems, Inc.
L
OW
SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
FEATURES
GENERAL DESCRIPTION
• 18 LVCMOS/LVTTL outputs, 23Ω typical output impedance
• Selectable LVCMOS_CLK or LVPECL clock inputs
The ICS83940I-01 is a low skew, 1-to-18
ICS
LVPECL-to-LVCMOS/LVTTL Fanout Buffer and a
member of the HiPerClockS™ family of High Per-
formance Clock Solutions from ICS. The
ICS83940I-01 has two selectable clock inputs.
HiPerClockS™
• LVCMOS_CLK supports the following input types:
LVCMOS or LVTTL
The PCLK, nPCLK pair can accept LVPECL, CML or SSTL
input levels. The single ended clock input accepts LVCMOS
or LVTTL input levels. The low impedance LVCMOS/LVTTL
outputs are designed to drive 50Ω series or parallel termi-
nated transmission lines.The effective fanout can be increased
from 18 to 36 by utilizing the ability of the outputs to drive two
series terminated lines.
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Part-to-part skew: 750ps (maximum)
• Full 3.3V, 2.5V or mixed 3.3V, 2.5V supply modes
• -40°C to 85°C ambient operating temperature
The ICS83940I-01 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes. Guar-
anteed output and part-to-part skew characteristics make the
ICS83940I-01 ideal for those clock distribution applications de-
manding well defined performance and repeatability.
• Pin compatible with the MPC940L in single supply
applications
BLOCK DIAGRAM
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
Q6
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
GND
CLK_SEL
Q7
Q8
LVCMOS_CLK
CLK_SEL
PCLK
PCLK
0
nPCLK
18
VDDO
Q9
ICS83940I-01
Q0:Q17
1
LVCMOS_CLK
Q10
Q11
GND
nPCLK
VDD
VDDO
9
10 11 12 13 14 15 16
32-Lead LQFP
Y Pacakge
7mm x 7mm x 1.4mm package body
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
83940DYI-01
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REV. A MARCH 1, 2004
1
PRELIMINARY
ICS83940I-01
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 12, 17, 25
GND
Power
Power supply ground.
3
LVCMOS_CLK
Input Pulldown Clock input. LVCMOS / LVTTL interface levels.
Clock select input. Selects LVCMOS / LVTTL clock
Input Pulldown input when HIGH. Selects PCLK, nPCLK inputs
when LOW. LVCMOS / LVTTL interface levels.
4
CLK_SEL
5
6
PCLK
Input Pulldown Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
nPCLK
Input
VDD/2 default when left floating.
7
VDD
Power
Power
Core supply pins.
8, 16, 21, 29
VDDO
Output supply pins.
9, 10, 11, 13, 14, Q17, Q16, Q15, Q14, Q13,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Output
Clock outputs. LVCMOS / LVTTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
6
pF
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
51
KΩ
18
28
Ω
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
PCLK, nPCLK
Selected
LVCMOS_CLK
De-selected
Selected
0
1
De-selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK_SEL LVCMOS_CLK
PCLK
nPCLK
Q0:Q17
LOW
0
0
—
—
0
1
1
0
Differential to Single Ended
Differential to Single Ended
Non Inverting
Non Inverting
HIGH
Biased;
NOTE 1
Biased;
NOTE 1
0
0
—
—
0
1
LOW
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
HIGH
0
0
1
1
—
—
0
Biased; NOTE 1
0
1
HIGH
LOW
LOW
HIGH
Single Ended to Single Ended
Single Ended to Single Ended
Inverting
Inverting
Biased; NOTE 1
—
—
—
—
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
83940DYI-01
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2
PRELIMINARY
ICS83940I-01
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
3.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.3V to VDD + 0.3V
-0.3V to VDDO + 0.3V
20mA
I
Outputs, VO
Input Current, IIN
StorageTemperature, T
-40°C to 125°C
STG
83940DYI-01
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REV. A MARCH 1, 2004
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PRELIMINARY
ICS83940I-01
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
TABLE 4A. DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
PCLK, nPCLK
2.4
VDD
0.8
V
V
Input Low Voltage
VPP
Peak-to-Peak Input Voltage
500
1000
mV
Input Common Mode Voltage;
NOTE 1, 2
VCMR
PCLK, nPCLK
V
DD - 1.4
VDD - 0.6
200
V
IIN
Input Current
µA
V
VOH
VOL
IDD
Output High Voltage
Output Low Voltage
Core Supply Current
IOH = -20mA
IOL = 20mA
2.4
0.5
25
V
mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40° TO 85°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
250
MHz
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
ns
tpLH
Propagation Delay
Propagation Delay
ns
ns
ns
tpLH
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
ps
ps
ns
ns
ns
ns
ps
ps
ns
ꢀ
Output Skew;
NOTE 3, 5
Measured on
rising edge @VDDO/2
tsk(o)
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
Part-to-Part Skew;
NOTE 6
tsk(pp)
tsk(pp)
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 4, 5
Measured on
rising edge @VDDO/2
tsk(pp)
tR, tF
Output Rise/Fall Time
0.5 to 2.4V
f < 134MHz
134MHz ≤ f ≤ 250MHz
0.3
45
40
1.1
55
60
50
50
odc
Output Duty Cycle
ꢀ
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
83940DYI-01
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REV. A MARCH 1, 2004
4
PRELIMINARY
ICS83940I-01
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
PCLK, nPCLK
2.4
VDD
0.8
V
V
Input Low Voltage
VPP
Peak-to-Peak Input Voltage
300
1000
mV
Input Common Mode Voltage;
NOTE 1, 2
VCMR
PCLK, nPCLK
VDD - 1.4
VDD - 0.6
200
V
IIN
Input Current
µA
V
VOH
VOL
IDD
Output High Voltage
Output Low Voltage
Core Supply Current
IOH = -20mA
IOL = 20mA
1.8
0.5
25
V
mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40° TO 85°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
250
MHz
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
ns
tpLH
Propagation Delay
Propagation Delay
ns
ns
ns
tpLH
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
ps
ps
ns
ns
ns
ns
ps
ps
ns
ꢀ
Output Skew;
NOTE 3, 5
Measured on
rising edge @VDDO/2
tsk(o)
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
Part-to-Part Skew;
NOTE 6
tsk(pp)
tsk(pp)
tsk(pp)
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 4, 5
Measured on
rising edge @VDDO/2
tR, tF
odc
Output Rise/Fall Time
Output Duty Cycle
0.5 to 1.8V
0.3
45
1.2
55
f < 134MHz
50
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
83940DYI-01
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REV. A MARCH 1, 2004
5
PRELIMINARY
ICS83940I-01
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
TABLE 4C. DC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = -40° TO 85°
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
2
VDD
0.8
V
V
Input Low Voltage
Peak-to-Peak
Input Voltage
Input Common Mode Voltage;
NOTE 1, 2
VPP
PCLK, nPCLK
PCLK, nPCLK
300
1000
mV
V
VCMR
V
DD - 1.4
VDD - 0.6
200
IIN
Input Current
µA
V
VOH
VOL
IDD
Output High Voltage
Output Low Voltage
Core Supply Current
IOH = -12mA
IOL = 12mA
1.8
0.5
25
V
mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = -40° TO 85°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
200
MHz
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
ns
Propagation Delay;
tpLH
ns
ns
ns
Propagation Delay;
tpLH
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
ps
ps
ns
ns
ns
ns
ns
ns
ns
ꢀ
Output Skew;
NOTE 3, 5
Measured on
rising edge @VDDO/2
tsk(o)
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
Part-to-Part Skew;
NOTE 6
tsk(pp)
tsk(pp)
tsk(pp)
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 4, 5
Measured on
rising edge @VDDO/2
tR, tF
odc
Output Rise/Fall Time
Output Duty Cycle
0.5 to 1.8V
0.3
45
1.2
55
f < 134MHz
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
83940DYI-01
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REV. A MARCH 1, 2004
6
PRELIMINARY
ICS83940I-01
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
1.25V 5ꢀ
1.65V 5ꢀ
2.05V 5ꢀ
SCOPE
SCOPE
,
VDD
VDD
VDDO
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V 5ꢀ
VDD
SCOPE
,
VDD
nPCLK
VDDO
VPP
VCMR
Cross Points
Qx
LVCMOS
GND
PCLK
GND
-1.25V 5ꢀ
2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
VDDO
VDDO
Qx
Qy
2
Qx
2
PART 2
Qy
VDDO
2
VDDO
2
tsk(o)
tsk(pp)
PART-TO-PART SKEW
OUTPUT SKEW
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PRELIMINARY
ICS83940I-01
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
VDDO
2
LVCMOS_CLK
nPCLK
PCLK
VDDO
2
Q0:Q17
➤
tPD
➤
PROPAGATION DELAY
1.8V
1.8V
2.4V
tF
2.4V
tR
0.5V
0.5V
0.5V
0.5V
Clock
Outputs
Clock Outputs
tR
tF
2.5V OUTPUT RISE/FALL TIME
3.3V OUTPUT RISE/FALL TIME
VDDO
2
Q0:Q17
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
odc & tPERIOD
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PRELIMINARY
ICS83940I-01
Integrated
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Systems, Inc.
L
OW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
PCLK
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS83940I-01
Integrated
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L
OW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other here are examples only. If the driver is from another vendor,
differential signals. Both VSWING and VOH must meet the VPP use their termination recommendation. Please consult with
and VCMR input requirements. Figures 2A to 2E show interface the vendor of the driver component to confirm the driver ter-
examples for the HiPerClockS PCLK/nPCLK input driven by mination requirements.
the most common driver types.The input interfaces suggested
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
R1
120
R2
120
PCLK/nPCLK
FIGURE 2A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY AN SSTL DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
Zo = 50 Ohm
R3
1K
R4
1K
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
LVDS
PCLK
PCLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R1
1K
R2
1K
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 2E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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REV. A MARCH 1, 2004
PRELIMINARY
ICS83940I-01
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83940I-01 is: 819
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OW
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KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
83940DYI-01
www.icst.com/products/hiperclocks.html
12
REV. A MARCH 1, 2004
PRELIMINARY
ICS83940I-01
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
250 per tray
1000
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS83940DYI-01
ICS83940DYI-01T
ICS83940DYI-01LF
ICS83940DI01
ICS83940DI01
ICS83940DI01L
32 Lead LQFP
32 Lead LQFP on Tape and Reel
32 Lead "Lead Free" LQFP
250 per tray
32 Lead "Lead Free" LQFP on
Tape and Reel
ICS83940DYI-01LFT
ICS83940DI01L
1000
-40°C to 85°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
83940DYI-01
www.icst.com/products/hiperclocks.html
REV. A MARCH 1, 2004
13
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