ICS9177-01CF52 [ICSI]
High Frequency System Clock Generator; 高速系统时钟发生器
| 型号： | ICS9177-01CF52 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | High Frequency System Clock Generator |
| 文件： | 总8页 (文件大小：318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9177
High Frequency System Clock Generator
General Description
Features
•
•
Provides output frequencies up to 175 Mhz
The ICS9177 is a multiple output clock generator ideal for
high speed processor system applications. A single high-
speedinternalVCOisutilizedtoderiveuptofoursimultaneous
clock output frequencies. This enables output clock skew
matching and the minimization of clock jitter. The internal
VCO operates up to 350 MHz providing edge skew matched
output clocks.
Internal VCO is divided into four skew-matched output
frequencies (Out A, B, C, D)
•
•
External clock feedback provides input to output skew
matching
Differential PECL clock output pair provided for high
speed output (Out A)
•
•
•
•
12 TTL clock outputs (for Out B, C, D)
Single 5 volt power supply voltage
Internal loop filters
One differential PECL (Positive ECL) output pair provides a
high speed processor clock. 12 TTL clock outputs are also
provided for other system functions, such as bus clocks. Input
selection pins are used to select the TTL output clock
frequencies.
52-pin QFP package
For information about ICS9177 customization optics, please
contact ICS.
Block Diagram
Pin Configuration
52-Pin QFP
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9177RevB060297P
ICS9177
Pin Description
PIN
NUM-
BER
PIN
NUM-
BER
PIN
NAME
PIN
TYPE
DESCRIPTION
TYPE
DESCRIPTION
NAME
GND
28
29
30
31
32
COUT2
COUT1
VCC
OUTPUT
OUTPUT
1
2
TTL - 25 MHz output clock
REFCLK INPUT from external oscillator
external PLL Feedback path
FBCLK
GND
3
INPUT from one of the OutC
outputs
COUT0
TTL - 25 MHz output clock
TTL - 12.5 MHz output
clock
PLL divider mode control
INPUT
33
DOUT0
4
5
DSEL1#
(Contains internal pull-up
34
35
GND
NC
DSEL0#
TESTEN
INPUT
resistors)
6
INPUT Test mode ENABLE pin
ECL - 100 MHz, 75 MHz or
50 MHz based on DSEL(1:0)
pins
36
37
AOUT1
AOUT0
OUTPUT
OUTPUT
7
TSTCLK INPUT External Test Clk
8
NC
38
39
NC
9
VCC
GND
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
ECL+5V
(same as
VCC)
PCOUT1 OUTPUT
PCOUT0 OUTPUT
GND
TTL - Group 2
Programmable clock outputs
40
41
42
NC
NC
VCC
ANALO-
G +5V
PBOUT1 OUTPUT
PBOUT0 OUTPUT
VCC
43
TTL - Group 1
Programmable clock outputs
ANALO-
G +5V
44
45
46
47
48
49
50
AGND
GND
Programmable clock Group
C select
PAOUT1 OUTPUT
PAOUT0 OUTPUT
VCC
TTL - Group 0
Programmable clock outputs
PCSEL1
PCSEL0
PBSEL1
PBSEL0
PASEL1
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Programmable clock Group
B select
GND
RESETL
BOUT1
BOUT0
VCC
INPUT Low true divider reset pin
Programmable clock Group
A select
OUTPUT
TTL - 50 MHz output clock
OUTPUT
51
52
PASEL0
VC
GND
*Internal pull-up resistor
2
ICS9177
Typical System Usage
Example of System Block Diagram - Clocking
FunctionTables
Table 1: Primary Function Table Typical System Usage
REF IN
(MHx)
OUT
A
OUT
B
OUT
C
OUT
D
DSEL1# DSEL0#
RSTL
TEST
f1
DESCRIPTION
25
25
0
0
0
1
1
1
0
0
200 MHz
300 Mhz
f/4
f/4
f/4
f/6
f/8
f/16
f/24
Mode 0 - 1/1
Mode 1 - 3/2
f/12
200/264
MHz
33
1
0
1
0
f/2
f/4
f/8
f/16
Mode 2 - 2/1
25
-
1
X
0
1
X
0
1
0
1
1
1
1
0
X
1
X
1
1
1
1
0
Mode 3 - A ll 1
Reset Mode
Test Mode 0
Test Mode 1
Test Mode 2
Test Mode 3
X
0
0
0
-
TCLK
TCLK
TCLK
TCLK
f/2
f/2
f/1
f/2
f/2
f/3
f/2
f/2
f/4
f/6
f/4
f/2
f/8
f/12
f/8
f/2
-
0
1
1
-
1
0
1
-
1
1
1
Table 2: CLOCK SELECT Blocks Function Table
PxSEL
1
PxSEL
0
Function of CLOCK SELECT Blocks
0
0
1
1
0
1
0
1
Both outputs at the same frequency as Out B.
Both outputs at the same frequency as Out C.
Both outputs at the same frequency as Out D.
Both outputs disabled in the high state.
Note: x=A, B, or C. (See Figure 1.)
3
ICS9177
Clock OutputTiming Diagrams
1:1 frequency ratio - Mode 0
3:2 frequency ratio - Mode 1
2:1 frequency ratio - Mode 2
Note: The arrow indicates the point where the clock sequence starts to repeat.
4
ICS9177
Absolute Maximum Ratings
Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -.05V to VDD +.05V
Ambient operating temperature . . . . . . . . . . . . . . . . 0°C to +70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Power Supply Specifications (Total Power consumption: approximately 750 mw)
Table 3: DC Specifications
Supply
VDD
I(typ)
I(max)
V(min)
4.75V
V(typ)
5V
V(max)
5.25V
150 mA
200 mA
AC/DC Input Specification
Table 4: AC Specification of Inputs
Pin Type
All
Vih(min)
2V
Vil(max)
0.8V
tr
3
tf
3
Note: tr and tf are typical values for input
AC/DC Characteristics
Table 5: AC Specification type Out A.pecl Pins (CPUCLK)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
3.87
2.63
38.7
26.3
TYP
MAX
4.67
3.19
46.7
31.9
1
UNITS
volts
volts
ma
1
Output High Voltage
Voh
Vol
Ioh
Iol
Output Low Voltage 1
Output High Current
Output Low Current
Rise Time 10-90%
ma
tr
ns
Fall Time 10-90%
tf
1
ns
Duty cycle at 100 MHz 2, 3
dcyc
45
55
%
Test Load Conditions: 100Ω, 15 pF.
Note 1: The pecl levels are standard 10 kHz positive ECL values as shown in the table above.
Note 2: Pin skew and Duty cycle are measured at the signal swing mid-point.
Note 3: The skew and duty cycle numbers reflect the recommended clock distribution method shown in Figure 2
5
ICS9177
Table 6: AC Specification type Out B.ttl Pins (50 MHz)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
2.4
0
TYP
MAX
UNITS
volts
volts
mA
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time 10-90%
Fall Time 10-90%
Voh
Vol
Ioh
Iol
tr
3.2
5
0.3
0.8
16
24
3
mA
1
1
2
2
ns
tf
3
ns
Pin skew to other OutB.ttl
signals 1
tsk
250
500
ps
Duty cycle at 1.5V
dcyc
tdly
45
55
.5
%
ns
2
Delay from OutA.pecl signals
.2
Skew associated with above
delay 3
tdlyskw
±0.5
ns
Test Load Conditions: 500Ω, 15 pF.
Note 1: Pin skew is measured from the earliest rising edge of the group to the latest rising edge of the group.
Note 2: Delay is the intrinsic delay between the TTL drivers switching and the PECL driver switching. This is measured from
the OutA.pecl signal at the signal swing mid-point to max output of the OutB.ttl signal’s rising edge
Table 7: AC Specification type Out C.ttl Pins (25 MHz)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time 10-90%
Fall Time 10-90%
SYMBOL
TEST CONDITIONS
MIN
2.4
0
TYP
MAX
UNITS
volts
volts
mA
Voh
Vol
Ioh
Iol
tr
3.2
5
0.3
0.8
16
24
3
mA
1
1
2
2
ns
tf
3
ns
Pin skew to other OutC.ttl
signals 1
tsk
250
500
ps
Duty cycle at 1.5V
Spread to OutB.ttl signals 2
dcyc
tspb
45
55
%
ps
500
Test Load Conditions: 500Ω, 15 pF.
Note 1: Pin skew is measured from the earliest rising edge of the group to the latest rising edge of the group.
Note 2: Spread is the absolute difference between the rising edge of any OutC.ttl signal and the rising edge of any OutB.ttl
signal
6
ICS9177
Table 8: AC Specification type Out D.ttl Pins (12.5 MHz)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time 10-90%
Fall Time 10-90%
SYMBOL
TEST CONDITIONS
MIN
2.4
0
TYP
5
MAX
3.2
UNITS
volts
volts
mA
Voh
Vol
Ioh
Iol
tr
0.8
0.3
16
24
3
mA
1
1
2
2
ns
tf
3
ns
Pin skew to other OutD.ttl
signals
tsk
500
250
ps
Duty cycle at 1.5V
dcyc
tdly
45
55
.5
%
ns
1
Delay from OutA.pecl signals
Skew associated with above
delay 2
tdlyskw
±1.3
ns
Test Load Conditions: 500W, 15 pF.
Note 1: Delay is the intrinsic delay between the TTL drivers switching and the PECL driver switching. This is measured from
the OutA.pecl signal at the signal swing mid-point to max output of the OutD.ttl signal’s rising edge
7
ICS9177
52-Pin QFP Package
LEAD COUNT
44L
52L
64L
2.0
80L
100L
64L
80L
100L
BODY THICKNESS
FOOTPRINT (BODY+)
2.70
3.20
DIMENSIONS TOLERANCE
A
A1
D
MAX.
MAX.
±0.25
2.45
0.25
3.40
0.25
13.20
10.0
13.20
10.0
0.70
0.80
17.20
14.00
17.20
14.00
0.88
17.20
14.00
23.20
20.00
0.88
D1
E
±0.10
±0.25
E1
L
±0.10
±0.15/-0.10
BASIC
+0.05
e
1.00
1.00
0.80
0.65
0.30
1.00
0.80
0.65
0.30
b
0.35
0.35
ccc
MAX
0.10
0° - 7°
Ordering Information
ICS9177-01CF52
Example:
ICS XXXX-PPP M X#W
Lead Count & Package Width
Lead Count=1, 2 or 3 digits
W=.3” SOIC or .6” DIP; None=Standard Width
Package Type
F=QFP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=StandardDevice;GSP=Genlock
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
8
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