ICS9248-20 [ICSI]
Pentium/ProTM System Clock Chip; 奔腾/ ProTM系统时钟芯片
| 型号： | ICS9248-20 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Pentium/ProTM System Clock Chip |
| 文件： | 总11页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-20
TM
Pentium/Pro System Clock Chip
General Description
Features
Generates system clocks for CPU, IOAPIC, PCI, plus
The ICS9248-20 is a Clock Synthesizer chip for Pentium and
PentiumPro CPU based Desktop/Notebook systems that will
provide all necessary clock timing.
14.314 MHz REF (0:2), USB, and Super I/O
Supports single or dual processor systems
Supports Spread Spectrum modulation for CPU & PCI
clocks, down spread -0.5%
Skew from CPU (earlier) to PCI clock (rising edges for
100/33.3MHz) 1.5 to 4ns
Two fixed outputs at 48MHz.
Separate 2.5V and 3.3V supply pins
2.5V or 3.3V output: CPU, IOAPIC
3.3V outputs: PCI, REF, 48MHz
No power supply sequence requirements
Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal
Features include four CPU and eight PCI clocks. Three
reference outputs are available equal to the crystal frequency.
Additionally, the device meets the Pentium power-up
stabilization requirement, assuring that CPU and PCI clocks
are stable within 2ms after power-up.
PD# pin enables low power mode by stopping crystal OSC
and PLL stages. Other power management features include
CPU_STOP#, whichstopsCPU(0:3)clocks, andPCI_STOP#,
which stops PCICLK (0:6) clocks.
High drive CPUCLK outputs typically provide greater than 1
V/ns slew rate into 20pF loads. PCICLK outputs typically
provide better than 1V/ns slew rate into 30pF loads while
maintaining 50±5%dutycycle.TheREFclockoutputstypically
provide better than 0.5V/ns slew rates.
48 pin 300 mil SSOP
The ICS9248-20 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Pin Configuration
Block Diagram
48-Pin SSOP
Power Groups
Ground Groups
VDD = Supply for PLL core
VDD1 = REF (0:2), X1, X2
VDD2 = PCICLK_F, PCICLK (0:6)
VDD3 = 48MHz0, 48MHz1
VDDL1 = IOAPIC (0:1)
GND = Ground for PLL core
GND1 = REF (0:2), X1, X2
GND2 = PCICLK_F, PCICLK (0:6)
GND3 = 48MHz0, 48MHz1
GNDL1 = IOAPIC (0:1)
VDDL2 = CPUCLK (0:3)
GNDL2 = CPUCLK (0:3)
Pentium is a trademark on Intel Corporation.
9248-20 Rev B 12/03/98
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
ICS9248-20
Pin Descriptions
PIN NUMBER
PIN NAME
REF (0:2)
GND1
TYPE
OUT
PWR
DESCRIPTION
14.318MHz clock output
Ground for REF outputs
1, 2, 47
3
XTAL_IN 14.318MHz Crystal input, has internal 33pF load
cap and feed back resistor from X2
4
X1
IN
5
X2
GND2
PCICLK_F
PCICLK (0:6)
VDD2
VDD
GND
VDD3
48MHz (0:1)
GND3
OUT
PWR
OUT
OUT
PWR
PWR
PWR
PWR
OUT
PWR
XTAL_OUT Crystal output, has internal load cap 33pF
Ground for PCI outputs
Free Running PCI output
PCI clock outputs. TTL compatible 3.3V
Power for PCICLK outputs, nominally 3.3V
Isolated power for core, nominally 3.3V
Isolated ground for core
Power for 48MHz outputs, nominally 3.3V
48MHz outputs
6, 12, 18
7
8, 10, 11, 13, 14, 16, 17
9, 15
19, 33
20, 32
21
22, 23
24
Ground for 48MHz outputs
Select pin for enabling 100MHz or 66.6MHz
H=100MHz, L=66.6MHz (PCI always synchronous 33.3MHz)
25
SEL100/66.6#
IN
26, 27
28
29
FS (0:1)
SPREAD#
PD#
IN
IN
IN
Frequency Select pins
Enables Spread Spectrum feature when LOW
Powers down chip, active low
30
CPU_STOP#
PCI_STOP#
VDDL2
GNDL2
CPUCLK (3:0)
N/C
IN
IN
PWR
PWR
OUT
-
Halts CPU clocks at logic "0" level when low
Halts PCI Bus at logic "0" level when low
Power for CPU outputs, nominally 2.5V
Ground for CPU outputs.
CPU and Host clock outputs @ 2.5V
Not internally connected
31
37, 41
34, 38
35, 36, 39, 40
42
43
44, 45
46
GNDL1
IOAPIC (0:1)
VDDL1
PWR
OUT
PWR
PWR
Ground for IOAPIC outputs
IOAPIC outputs (14.318MHz) @ 2.5V
Power for IOAPIC outputs, nominally 2.5V
Supply for REF (0:2), X1, X2, nominal 3.3V
48
VDD1
Select Functions
PCI,
PCI_F
48 MHz
IOAPIC
Functionality
CPU
REF
Selection
Tristate
Testmode
HI - Z
TCLK/21
HI - Z
TCLK/61
HI - Z
TCLK1
HI - Z
TCLK1
HI - Z
TCLK/21
Spread Spectrum
Modulated2 Modulated2 14.318MHz 14.318MHz 48.0MHz
SEL 100/66#
FS1
0
FS0
0
Function
Tri-State
Notes:
0
0
0
0
1
1
1
1
1. TCLK is a test clock driven on the X1 (crystal
in pin) input during test mode.
0
1
(Reserved)
1
0
(Reserved)
2. -0.5% modulation down spread from the
selected frequency.
1
1
Active 66.6MHz CPU, 33.3 PCI
Test Mode
0
0
0
1
(Reserved)
1
0
(Reserved)
1
1
Active 100MHz CPU, 33.3 PCI
PB
ICS9248-20
Technical Pin Function Descriptions
VDD(1,2,3)
48MHz (0:1)
This is the power supply to the internal core logic of the
device as well as the clock output buffers for REF(0:2),
PCICLK_F, PCICLK (0:6), 48MHz0, 48MHz1.
This is a fixed frequency Clock output that is typically used to
drive Super I/O devices. Outputs 0 and 1 are defined as
48MHz.
This pin operates at 3.3V volts. Clocks from the listed buffers
that it supplies will have a voltage swing from Ground to this
level. For the actual guaranteed high and low voltage levels
for the Clocks, please consult the DC parameter table in this
data sheet.
IOAPIC (0:1)
This Output is a fixed frequency Output Clock that runs at the
Reference Input (typically 14.31818MHz) . Its voltage level
swing is controlled by VDDL1 and may operate at 2.5 or
3.3volts.
VDDL1,2
REF(0:2)
This is the power supply for the CPUCLK (0:3) and IOAPIC
output buffers. The voltage level for these outputs may be 2.5
or 3.3volts. Clocks from the buffers that each supplies will
have a voltage swing from Ground to this level. For the actual
Guaranteed high and low voltage levels of these Clocks,
please consult the DC parameter table in this Data Sheet.
The REF Outputs are fixed frequency Clocks that run at the
same frequency as the Input Reference Clock X1 or the
Crystal (typically 14.31818MHz) attached across X1 and X2.
PCICLK_F
ThisOutputisequaltoPCICLK(0:6)andisFREERUNNING,
and will not be stopped by PCI_STOP#.
GND (1,2,3)
This is the ground to the internal core logic of the device as
well as the clock output buffers for REF(0:2), PCICLK_F,
PCICLK (0:6), 48MHz 0, 48MHz1.
PCICLK (0:6)
These Output Clocks generate all the PCI timing requirements
for a Pentium/Pro based system. They conform to the current
PCI specification. They run at 33.3 MHz.
GNDL (1,2)
SELECT 100/66.6MHz#
This is the ground for the CPUCLK (0:3) and IOAPIC output
buffers.
This Input pin controls the frequency of the Clocks at the
CPUCLK, PCICLK and SDRAM output pins. If a logic 1
value is present on this pin, the 100MHz Clock will be
selected. If a logic 0 is used, the 66.6MHz frequency will
be selected. The PCI clock is multiplexed to be 33.3MHz for
both select cases. PCI is synchronous at the rising edge of PCI
to the CPU rising edge (with the skew making CPU early).
X1
This input pin serves one of two functions. When the device
is used with a Crystal, X1 acts as the input pin for the
reference signal that comes from the discrete crystal. When
the device is driven by an external clock signal, X1 is the
device input pin for that reference clock. This pin also
implements an internal Crystal loading capacitor that is
connected to ground. With a nominal value of 33pF no
external load cap is needed for a CL=17 to 18pF crystal.
PWR_DWN#
This is an asynchronous active Low Input pin used to Power
Down the device into a Low Power state by not removing the
power supply. The internal Clocks are disabled and the VCO
and Crystal are stopped. Powered Down will also place all
the Outputs in a low state at the end of their current cycle. The
latency of Power Down will not be greater than 3ms.
X2
This Output pin is used only when the device uses a Crystal as
the reference frequency source. In this mode of operation, X2
is an output signal that drives (or excites) the discrete Crystal.
The X2 pin will also implement an internal Crystal loading
capacitor nominally 33pF.
CPU_STOP#
This is a synchronous active Low Input pin used to stop the
CPUCLK clocks in an active low state. All other Clocks
including SDRAM clocks will continue to run while this
function is enabled. The CPUCLKs will have a turn ON
latency of at least 3 CPU clocks.
CPUCLK (0:3)
These Output pins are the Clock Outputs that drive processor
and other CPU related circuitry that requires clocks which are
in tight skew tolerance with the CPU clock. The voltage
swing of these Clocks is controlled by the Voltage level
applied to theVDDL2 pin of the device. See the Functionality
Table for a list of the specific frequencies that are available
for these Clocks and the selection codes to produce them.
PCI_STOP#
This is a synchronous active Low Input pin used to stop the
PCICLK clocks in an active low state. It will not affect
PCICLK_F nor any other outputs.
3
ICS9248-20
Power Management
Clock Enable Configuration
Other Clocks,
REF,
CPU_STOP# PCI_STOP# PWR_DWN#
CPUCLK
PCICLK
IOAPICs,
48 MHz 0
48 MHz 1
Crystal
VCOs
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Low
Low
Low
Low
Stopped
Running
Running
Running
Running
Off
Off
Running
Running
Running
Running
Running
Running
Running
Running
Low
33.3 MHz
Low
100/66.6MHz
100/66.6MHz
33.3 MHz
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up
and power down operations using the PD# select pin will not cause clocks of a shorter or longer pulse than that of the running
clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging
circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
ICS9248-20 Power Management Requirements
Latency
No. of rising edges of free
running PCICLK
SIGNAL
SIGNAL STATE
CPU_ STOP#
0 (Disabled)2
1 (Enabled)1
1
1
1
PCI_STOP#
PD#
0 (Disabled)2
1 (Enabled)1
1
1 (Normal Operation)3
0 (Power Down)4
3ms
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF and IOAPIC will be stopped independent of these.
PB
ICS9248-20
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-20. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a
low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4
CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This
signal is synchronized to the CPUCLKs inside the ICS9248-20.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-20. It is used to turn off the PCICLK (0:6) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-20 internally. The minimum that the PCICLK (0:6) clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK (0:6) clocks. PCICLK (0:6) clocks are stopped in a low state and started with
a full high pulse width guaranteed. PCICLK (0:6) clock on latency cycles are only one rising PCICLK. Clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-20.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
5
ICS9248-20
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the ICS9248-20 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power
on latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are dont care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
PB
ICS9248-20
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
VIL
VSS-0.3
0.8
5
V
IIH
VIN = VDD
0.1
2.0
-100
60
µA
µA
µA
mA
mA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
170
170
Supply Current
Power Down
Supply Current
Input frequency
66
IDD3.3PD
CL = 0 pF; With input address to Vdd or GND
70
600
µA
Fi
VDD = 3.3 V;
11
27
14.318
16
5
MHz
pF
CIN
Logic Inputs
Input Capacitance1
CINX
Ttrans
Ts
X1 & X2 pins
36
5
45
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ms
ns
TSTAB
3
4
TCPU-PCI1 VT = 1.5 V;
1.5
3
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
IDD2.5OP66
IDD2.5OP100
tCPU-PCI2
CONDITIONS
CL = 0 pF; Select @ 66.8 MHz
CL = 0 pF; Select @ 100 MHz
VT = 1.5 V; VTL = 1.25 V
MIN
TYP
16
23
3
MAX UNITS
72
100
4
mA
mA
ns
Supply Current
Skew1
1.5
1Guaranteed by design, not 100% tested in production.
7
ICS9248-20
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP MAX UNITS
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
2.3
0.2
-41
37
V
V
0.4
-19
mA
mA
ns
IOL2B
19
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.25
1
1.6
1.6
1
Fall Time
tf2B
ns
%
1
Duty Cycle
dt2B
48
55
1
Skew
tsk2B
VT = 1.25 V
30
175
200
150
+250
ps
ps
ps
ps
1
Jitter, Cycle-to-cycle tjcyc-cyc2B VT = 1.25 V
150
40
1
Jitter, One Sigma
tj1s2B
VT = 1.25 V
VT = 1.25 V
1
tjabs2B
Jitter, Absolute
-250
140
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew1
Jitter, One Sigma1
Jitter, Absolute1
SYMBOL
VOH4B
VOL4B
IOH4B
CONDITIONS
MIN
2
TYP MAX UNITS
IOH = -18 mA
IOL = 18 mA
VOH = 1.7 V
VOL = 0.7 V
2.2
0.33
-41
37
V
V
0.4
-28
mA
mA
ns
ns
%
IOL4B
29
45
-5
Tr4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.5
1.3
54
2
2
Tf4B
Dt4B
55
250
3
1
tsk4B
VT = 1.25 V
60
ps
%
Tj1s4B
VT = 1.25 V
1
Tjabs4B
VT = 1.25 V
5
%
1Guaranteed by design, not 100% tested in production.
PB
ICS9248-20
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
VOL1
IOH1
IOL1
CONDITIONS
MIN
2.4
TYP MAX UNITS
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
3.1
0.1
-62
57
V
V
0.4
-22
mA
mA
ns
16
45
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.1
50
2
Fall Time1
Duty Cycle1
tf1
2
ns
dt1
55
%
Skew1
Jitter, One Sigma1
Jitter, Absolute1
tsk1
VT = 1.5 V
140
17
500
150
500
ps
tj1s1
tjabs1
VT = 1.5 V
ps
VT = 1.5 V
-500
70
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Jitter, One Sigma1
Jitter, Absolute1
SYMBOL
VOH5
VOL5
IOH5
CONDITIONS
MIN
2.6
TYP MAX UNITS
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
3.1
0.17
-44
42
V
V
0.4
-22
mA
mA
ns
IOL5
29
45
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.4
1.1
53
2
2
tf5
ns
dt5
55
3
%
tj1s5
VT = 1.5 V
1
%
tjabs5
VT = 1.5 V
3
5
%
1Guaranteed by design, not 100% tested in production.
9
ICS9248-20
Electrical Characteristics - 48 MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Frequency Accuracy1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Jitter, One Sigma1
Jitter, Absolute1
SYMBOL
FACC48m
VOH5
VOL5
IOH5
CONDITIONS
MIN
2.6
TYP MAX UNITS
167
ppm
V
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
3
0.14
-44
42
1.2
1.2
52
1
0.4
-22
V
mA
mA
ns
IOL5
16
45
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
4
4
tf5
ns
dt5
55
3
%
tj1s5
VT = 1.5 V
%
tjabs5
VT = 1.5 V
3
5
%
1Guaranteed by design, not 100% tested in production.
PB
ICS9248-20
SSOP Package
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
MAX.
.110
.016
.092
.0135
.0085
MIN.
.620
.720
NOM. MAX.
A
A1
A2
B
AC
AD
.625
.725
.630
.730
48
56
C
.006
D
E
See Variations
.296
.292
.299
e
H
h
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
L
.032
N
See Variations
0°
5°
8°
X
.085
.093
.100
This table in inches
Ordering Information
ICS9248F-20
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
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