ICS9250-18 [ICSI]
Frequency Generator & Integrated Buffers for Celeron & PII/III⑩; 频率发生器和缓冲器集成的赛扬和PII / III⑩
| 型号： | ICS9250-18 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| 文件： | 总15页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9250-18
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
BX, Appollo Pro 133 type of chip setꢀ
Pin Configuration
Output Features:
VDDREF
*FS2/REF1
*PCI_STOP#/REF0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDLIOAPIC
IOAPIC0
IOAPIC_F
GND
CPUCLK_F
CPUCLK1
VDDLCPU
CPUCLK2
GND
CPU_STOP#
SDRAM_F
VDDSDR
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
•
•
•
•
•
•
•
3 - CPUs @2.5V, up to 166MHz.
17 - SDRAM @ 3.3V, up to 166MHz.
7 - PCI @3.3V
2 - IOAPIC @ 2.5V
1 - 48MHz, @3.3V fixed.
1 - 24MHz @ 3.3V
X1
X2
VDDPCI
*MODE/PCICLK_F
*FS3/PCICLK0
GND
2 - REF @3.3V, 14.318MHz.
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
PCICLK5
BUFFERIN
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
Features:
•
•
Up to 166MHz frequency support
Support power management: CPU, PCI, stop and Power
down Mode form I2C programming.
•
•
Spread spectrum for EMI control (± 0.25% center spread)
Uses external 14.318MHz crystal
Key Specifications:
•
•
•
•
CPU – CPU: <175ps
CPU – PCI: 1 - 4ns
PCI – PCI: <500ps
SDRAM15
SDRAM14
GND
SDRAM12
SDRAM13
VDD48
24MHz/FS0*
48MHz/FSI*1
SDRAM - SDRAM: <250ps
SDATA
SCLK
I2C
{
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3ꢀ3V on indicated inputs
** Internal Pull-down resistor of 240K to GND on indicated inputsꢀ
1ꢀ This output is double strengthꢀ
Block Diagram
Functionality
CPU
(MHz)
80.00
75.00
83.31
PCICLK
(MHz)
40.00
37.50
41.65
33.45
34.33
37.34
34.01
33.57
40.00
38.33
36.66
35.00
35.00
37.50
31.00
33.25
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.9
103.00
112.01
68.01
100.7
120.00
114.99
109.99
105.00
140.00
150.00
124.00
133.9
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9250-18 Rev B 9/23/99
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.
ICS9250-18
Pin Configuration
PIN NUMBER
PIN NAME
REF1
FS21
TYPE
OUT
IN
DESCRIPTION
14.318 MHz reference clock output
2
Latched frequency select input. Has pull-up to VDDPCI
14.318MHz reference clock output
REF0
OUT
3
Halts PCICLK [5:1] at logic "0" level when low.
(in mobile, MODE=0)
PCI_STOP#1
IN
4, 10, 23, 26, 34, 42,
48, 53
GND
X1
PWR
IN
Ground.
5
6
14.318MHz input. Has internal load cap, (nominal 33pF).
Crystal output. Has internal load cap (33pF) and feedback
resistor to X1
X2
OUT
OUT
IN
PCICLK_F
MODE1
Free running BUS clock not afected by PCI_STOP#
8
9
Latched input for MODE select. Converts pin 3 to PCI_STOP# when
low for power management.
FS31
IN
Latched frequency select input, pull-down
PCICLK0
OUT
Free running BUS clock not afected by PCI_STOP#
16, 14, 13, 12, 11 PCICLK [5:1]
OUT
PCI Clock Outputs.
17
27
28
BUFFERIN
SDATA
IN
IN
IN
Input for Buffers
Serial data in for serial config port. (I2C)
Clock input for serial config port. (I2C)
SCLK
24MHz
FS01
OUT
IN
24MHz clock output for Super I/O or FD.
30
Latched frequency select input. Has pull-up to VDD4.
48MHz
FS11
OUT
IN
48MHz clock output for USB, 2X strength.
29
Latched frequency select input. Has pull-up to VDD2.
1, 7, 15, 20,
31, 37, 45
24, 25, 32, 33, 18,
19, 21, 22, 35, 36,
38, 39, 40, 41, 43,
44
VDDPCI, VDDREF,
VDDSDR, VDD48
PWR
Nominal 3.3V power supply, see power groups for function.
SDRAM clocks
SDRAM [15:0]
OUT
46
47
SDRAM_F
OUT
IN
Free running SDRAM clock Not affected by CPU_STOP#
Halts CPUCLK [2:1], IOAPIC0, SDRAM [15:0]
clocks at logic "0" level when low.
CPU_STOP#
VDDLCPU,
VDDLIOAPIC
50, 56
PWR
CPU and IOAPIC clock buffer power supply, 2.5V nominal.
55
51, 49
52
IOAPIC0
OUT
OUT
OUT
IOAPIC clock output. (14.318 MHz) Poweredby VDDL1
CPU Output clocks. Powered by VDDL2 (60 or 66.6MHz)
Free running CPU output clock. Not affected ty the CPU_STOP#.
CPUCLK [2:1]
CPUCLK_F
Freerunning IOAPIC clock output. Not affected by the CPU_STOP#
(14.31818 MHz) Powered by VDDL1
54
IOAPIC_F
OUT
Notes:
1: Bidirectional input/output pins, input logic levels are latched at internal power-on-resetꢀ Use 10Kohm resistor
to program logic Hi to VDD or GND for logic lowꢀ
Third party brands and names are the property of their respective owners.
2
ICS9250-18
General Description
The ICS9250-18 is the single chip clock solution for Desktop/designs using BX, Appollo Pro 133 type of chip setsꢀ It provides
all necessary clock signals for such a systemꢀ
Spread spectrum may be enabled through I2C programmingꢀ Spread spectrum typically reduces system EMI by 8dB to
10dBꢀ This simplifies EMI qualification without resorting to board design iterations or costly shieldingꢀ The ICS9250-18
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variationsꢀ
Serial programming I2C interface allows changing functions, stop clock programming and frequency selectionꢀ
Mode Pin - Power Management Input Control
MODE
Pin 3
(Latched Input)
PCI_STOP#
0
(Input)
REF0
(Output)
1
Third party brands and names are the property of their respective owners.
3
ICS9250-18
General I2C serial interface information
The information in this section assumes familiarity with I2C programmingꢀ
For more information, contact ICS for an I2C programming application noteꢀ
How to Write:
Controller (host) sends a start bitꢀ
Controller (host) sends the write address D2(H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bitꢀ
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a timeꢀ
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1ꢀ
The ICS clock generator is a slave/receiver, I2C componentꢀ It can read back the data stored in the latches for
verificationꢀ Read-Back will support Intel PIIX4 "Block-Read" protocolꢀ
2ꢀ
3ꢀ
4ꢀ
5ꢀ
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3ꢀ3V logic levelsꢀ
The data byte format is 8 bit bytesꢀ
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controllerꢀ The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferredꢀ The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytesꢀ The data is loaded until a Stop sequence is issuedꢀ
6ꢀ
At power-on, all registers are set to a default condition, as shownꢀ
Third party brands and names are the property of their respective owners.
4
ICS9250-18
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
CPUCLK
MHz
PCICLK
MHz
Bit2
Bit7
Bit6
Bit5
Bit4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
80.00
75.00
83.31
40.00
37.50
41.65
33.45
34.33
37.34
34.01
33.57
40.00
38.33
36.66
35.00
35.00
37.50
31.00
33.25
33.75
32.50
31.50
39.33
38.66
31.67
30.00
28.34
41.50
40.00
38.75
36.99
36.50
35.99
35.50
34.50
66.9
103.00
112.01
68.01
100.7
120.00
114.99
109.99
105.00
140.00
150.00
124.00
133.9
135.00
129.99
126.00
118.00
115.98
95.00
XXXX
Note1
Bit
2,7, 6:4
90.00
85.01
166.00
160.01
154.99
147.95
145.98
143.98
141.99
138.01
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2, 7:4
Bit 3
Bit 1
Bit 0
0
1
0
0 - Normal
1 - Spread Spectrum Enabled ±0.25% (Center Spread)
0 - Running
1- Tristate all outputs
Note 1ꢀ Default at Power-up will be for latched logic inputs to define frequency as
displayed by Bit 3ꢀ
Note: PWD = Power-Up Default
Third party brands and names are the property of their respective owners.
5
ICS9250-18
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Reserved
Reserved
8
PCICLKF (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
-
Reserved
16
14
13
12
11
9
-
Reserved
46
49
51
52
SDRAM_F (Act/Inact)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK_F (Act/Inact)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
X
1
Latched FS0#
Reserved
-
1
1
1
1
-
Reserved
1
Reserved
29
30
48MHz (Act/Inact)
24MHz (Act/Inact)
X
1
Latched FS1#
Reserved
33, 32,
25, 24
22, 21,
19, 18
39, 38,
36, 35
44, 43,
41, 40
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
SDRAM(12:15) (Act/Inact)
SDRAM (8:11) (Act/Inact)
SDRAM (4:7) (Act/Inact)
SDRAM (0:3) (Act/Inact)
1
Reserved
X
1
Latched FS3#
Reserved
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
X
1
Latched FS2#
Notes:
54
55
-
IOAPIC_F (Act/Inact)
IOAPIC0 (Act/Inact)
Reserved
1ꢀ Inactive means outputs are held LOW and are disabled
1
from switchingꢀ
2ꢀ Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditionsꢀ
1
-
1
Reserved
2
1
REF1 (Act/Inact)
REF0 (Act/Inact)
3
1
Third party brands and names are the property of their respective owners.
6
ICS9250-18
Shared Pin Operation -
Input/Output Pins
These figures illustrate the optimal PCB physical layout
optionsꢀ These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signalsꢀ The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s)ꢀ
The I/O pins designated by (input/output) on the ICS9250-
18 serve as dual signal functions to the deviceꢀ During initial
power-up, they act as input pinsꢀ The logic level (voltage)
that is present on these pins at this time is read and stored
into a 4-bit internal data latchꢀ At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output functionꢀ
In this mode the pins produce the specified buffered clocks
to external loadsꢀ
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potentialꢀ A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating periodꢀ
Figsꢀ 1 and 2 show the recommended means of implementing
this functionꢀ In Figꢀ 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the devices
internal logicꢀ Figsꢀ 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be usedꢀ
Fig. 1
Third party brands and names are the property of their respective owners.
7
ICS9250-18
Fig. 2a
Fig. 2b
Third party brands and names are the property of their respective owners.
8
ICS9250-18
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizerꢀ It is used to turn off the CPUCLKs for low power operationꢀ
CPU_STOP# is synchronized by the ICS9250-18ꢀ All other clocks will continue to run while the CPUCLKs are disabledꢀ The
CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulseꢀ
CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKsꢀ
INTERNAL
CPUCLK
PCICLK (0:5)
CPU_STOP#
PCI_STOP# (High)
IOAPIC0
SDRAM(0:15)
CPUCLK (1:2)
SDRAM_F
CPUCLK_F
Notes:
1ꢀ All timing is referenced to the internal CPUCLKꢀ
2ꢀ CPU_STOP# is an asynchronous input and metastable conditions may existꢀ This signal is synchronized to the
CPUCLKs inside the ICS9250-18ꢀ
3ꢀ IOAPIC output is stopped Glitch Free by CPUSTOP# going lowꢀ
4ꢀ PCI_STOP# is shown in a high (true) stateꢀ
5ꢀ All other clocks continue to run undisturbedꢀ
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9250-18ꢀ It is used to turn off the PCICLK (0:5) clocks for low power operationꢀ
PCI_STOP# is synchronized by the ICS9250-18 internallyꢀ PCICLK (0:5) clocks are stopped in a low state and started with a full
high pulse width guaranteedꢀ PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK
clockꢀ
Notes:
1ꢀ All timing is referenced to the Internal CPUCLK (defined as inside the deviceꢀ)
2ꢀ PCI_STOP# is an asynchronous input, and metastable conditions may existꢀ This signal is required to be synchronized
inside the deviceꢀ
3ꢀ All other clocks continue to run undisturbedꢀ
4ꢀ CPU_STOP# is shown in a high (true) stateꢀ
Third party brands and names are the property of their respective owners.
9
ICS9250-18
Absolute Maximum Ratings
Supply Voltage ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 5ꢀ5 V
Logic Inputs ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ GND 0ꢀ5 V to VDD +0ꢀ5 V
Ambient Operating Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 0°C to +70°C
Case Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 115°C
Storage Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the deviceꢀ These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not impliedꢀ Exposure to absolute maximum rating conditions for extended periods
may affect product reliabilityꢀ
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD +0.3
V
VIL
GND -0.3
0.8
5
V
µA
µA
µA
IIH
VIN = VDD
0.1
2.0
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
-100
150
IDD3.3OP100 Select @ 100MHz; Sdram running
IDD3.3OP133 Select @ 133MHz; Sdram running
180
n/a
16
5
mA
Supply Current
200
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V
12
27
14.318
MHz
pF
CIN
Logic Inputs
CINX
TTrans
TS
X1 & X2 pins
36
1
45
4
pF
Transition Time1
Settling Time1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ms
3
Clk Stabilization1
TStab
4
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
IDD2.5OP100 Select @ 100MHz; Max discrete cap loads
IDD2.5OP133
CONDITIONS
MIN
TYP
13
MAX UNITS
25
mA
25
Supply Current
Select @ 133MHz; Max discrete cap loads
18
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
10
ICS9250-18
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
CONDITIONS
MIN
2
TYP
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
2.3
0.2
-41
37
0.4
-19
V
mA
mA
ns
IOH2B
IOL2B
19
0.4
0.4
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.6
1.6
1
Fall Time
tf2B
1
ns
1
Duty Cycle
dt2B
51
55.5
175
254
250
+250
250
%
1
Skew group1: 1,2 and 1,F
Skew group2: 2, F
tsk2B
VT = 1.25 V
120
ps
1
tsk2B
VT = 1.25 V
ps
1
Jitter, One Sigma
Jitter, Absolute
tj1σ2B
VT = 1.25 V
120
100
150
ps
1
tjabs2B
VT = 1.25 V
-250
ps
1
tjcyc-cyc2B
VT = 1.25 V
Jitter, Cycle-to-cycle
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz, 24MHz,REF0
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
2.9
MAX UNITS
V
IOH = -14 mA
IOL = 6.0 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.25
-42
18
0.4
-20
V
IOH5
mA
mA
IOL5
10
45
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1.1
1
2.5
2.5
ns
ns
Fall Time1
Duty Cycle1
dt5
tj1s5
tjabs5
VT = 1.5 V
50
55
%
ps
ps
Jitter1
VT = 1.5 V, 24, 48MHz
VT = 1.5 V, REF0
100
250
250
800
Jitter1
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
ICS9250-18
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 60 pF for PCI0 & PCI1, CL = 30 pF for other PCIs
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
2.9
0.2
-58
52
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-22
V
IOH1
mA
mA
IOL1
25
45
Rise Time1
Fall Time1
Duty Cycle1
Skew1
tr1
tf1
VOL = 0.8 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.4
50
2.5
2.5
55
ns
ns
%
ps
ps
ps
dt1
tsk1
tj1σ1
tjabs1
VT = 1.5 V
270
50
500
150
500
Jitter, One Sigma1
Jitter, Absolute1
VT = 1.5 V
VT = 1.5 V
200
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL =30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
CONDITIONS
MIN
TYP
MAX UNITS
V
IOH = -28 mA
IOL = 19 mA
VOH = 2.0 V
VOL = 0.8 V
2.4
2.8
0.34
-72
50
VOL1
0.4
-42
V
IOH1
mA
mA
IOL1
33
0.5
0.5
45
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 04 V
VT = 1.5 V
2
ns
ns
%
ps
ps
ps
ns
ps
ps
Fall Time1
Duty Cycle1
2.4
dt1
50
56.3
250
250
410
4.4
Skew(Group1: F,0:4, 8:11)1
Skew(Group2: 5:7, 12:15)1
Skew(Group3: 0, 13)1
Skew(Buferin-Output)1
Jitter, One Sigma1
tsk1
tsk1
tsk1
tsk1
tj1σ1
tjabs1
VT = 1.5 V
130
180
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
3.5
50
VT = 1.5 V
150
250
Jitter, Absolute1
VT = 1.5 V
-250
130
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
ICS9250-18
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH4B
VOL4B
CONDITIONS
MIN
2
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
2.2
0.3
-32
26
0.4
-19
V
IOH4B
mA
mA
IOL4B
19
0.4
0.4
45
Rise Time1
Fall Time1
Duty Cycle1
Tr4B
Tf4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.5
1
1.8
1.6
55
ns
ns
%
ps
ps
Dt4B
51
Jitter, One Sigma1
Jitter, Absolute1
Tj1σ4B
Tjabs4B
VT = 1.25 V
240
619
300
650
VT = 1.25 V
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
13
ICS9250-18
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
tracesꢀ
Ferrite
Bead
Ferrite
Bead
C2
22µF/20V
Tantalum
C2
22µF/20V
Tantalum
VDD
VDD
2) Make all power traces and ground
traces as wide as the via pad for lower
inductanceꢀ
1
56
C3
2
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
3
2.5V Power Route
Clock Load
4
C1
C1
Notes:
5
1) All clock outputs should have a
series terminating resistor, and a 20pF
capacitor to ground between the
resistor and clock pinꢀ Not shown in
all places to improve readibility of
diagramꢀ
1
6
2
7
C3
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2) Optional crystal load capacitors are
recommendedꢀ They should be
included in the layout but not
inserted unless neededꢀ
3.3V Power Route
3.3V Power Route
Ground
Ground
Component Values:
C1 : Crystal load values determined by user
C2 : 22µF/20V/D case/Tantalum
AVX TAJD226M020R
C3 : 100pF ceramic capacitor
C4 : 20pF capacitor
FB = Fair-Rite products 2512066017X1
All unmarked capacitors are 0ꢀ01µF ceramic
Connections to VDD:
= Routed Power
= Ground Connection (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
Third party brands and names are the property of their respective owners.
14
ICS9250-18
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
-
MAX.
.110
.016
.092
.0135
.010
MIN.
.720
NOM. MAX.
.725 .730
A
A1
A2
B
AD
56
C
D
E
See Variations
.296
.292
.299
e
H
h
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
SSOP Package
L
.032
N
See Variations
5°
.093
0°
.085
8°
.100
X
Ordering Information
ICS9250yF-18
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
15
information being relied upon by the customer is current and accurate.
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