ICS8402015I [IDT]
FemtoClock™ Crystal-to-LVDS/LVCMOS Frequency; FemtoClock ™晶体至LVDS / LVCMOS频率
| 型号： | ICS8402015I |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FemtoClock™ Crystal-to-LVDS/LVCMOS Frequency |
| 文件： | 总19页 (文件大小：861K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8402015I
FemtoClock™
Crystal-to-LVDS/LVCMOS Frequency
DATASHEET
General Description
Features
ICS8402015I is a low phase noise Clock Synthesizer
and is a member of the HiPerClockS™family of high
performance clock solutions from IDT. The device
provides three banks of outputs and a reference clock.
Each bank can be enabled by using output enable
• Three banks of outputs:
S
IC
Bank A: three single-ended LVCMOS/LVTTL outputs at 25MHz
or 50MHz
HiPerClockS™
Bank B: three single-ended LVCMOS/LVTTL outputs at 125MHz
Bank C: three differential LVDS outputs at 125MHz
Reference LVCMOS/LVTTL output at 25MHz
pins. A 25MHz or 50MHz, 18pF parallel resonant crystal is used to
generate 25MHz LVCMOS, 125MHz LVCMOS and 125MHz LVDS
outputs. ICS8402015I is packaged in a small, 32-pin VFQFN
package that is optimum for applications with space limitations.
• Crystal input frequency: 25MHz
• Maximum output frequency: 125MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(637kHz - 62.5MHz): 0.373ps (typical) LVDS output
• RMS phase jitter @ 25MHz, using a 25MHz crystal
(12kHz - 1MHz): 0.64ps (typical) LVCMOS output
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Pin Assignment
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
V
DDO_REF
V
DDO_C
24
23
22
21
20
REF_OUT
GND
nQC2
QC2
nC1
GND
QA0
QC1
QA1
QA2
nQC0
QC0
19
18
17
VDDO_A
VDDO_C
9
10 11 12 13 14 15 16
ICS8402015I
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
ICS8402015AKI REVISION A JUNE 25, 2009
1
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Block Diagram
OE1 = Pullup
OE0, OE2 = Pulldown
OE
3
OE[2:0]
LVCMOS - 25MHz or
50MHz
LOGIC
QA0
÷10
÷20
QA1
QA2
25MHz
XTAL_IN
LVCMOS - 125MHz
QB0
OSC
Phase
Detector
VCO
500MHz
XTAL_OUT
QB1
QB2
÷4
÷4
÷20
LVDS - 125MHz
QC0
nQC0
QC1
nQC1
QC2
nQC2
Pulldown
MR
LVCMOS - 25MHz
REF_OUT
ICS8402015AKI REVISION A JUNE 25, 2009
2
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
Type
Description
1
2
VDDO_REF
REF_OUT
Power
Output
Output supply pin for REF_OUT output.
Reference clock output. LVCMOS/LVTTL interface levels.
3, 4, 13, 16,
25, 32
GND
Power
Power supply ground.
5, 6, 7
QA0, QA1, QA2 Output
Single-ended Bank A clock outputs.LVCMOS/LVTTL interface levels.
8
9
VDDO_A
VDDO_B
Power
Power
Power output supply pin for Bank A LVCMOS outputs.
Power output supply pin for Bank B LVCMOS outputs.
10, 11, 12
QB0, QB1, QB2 Output
Single-ended Bank B clock outputs.LVCMOS/LVTTL interface levels.
Master reset, resets the internal dividers. During reset, LVCMOS outputs are pulled
14
MR
Input
Pulldown LOW, and LVDS outputs are pulled LOW and HIGH (QCx pulled LOW, nQCx
pulled HIGH). LVCMOS/LVTTL interface levels.
15
VDD
Power
Power
Output
Output
Output
Power
Core supply pin.
17, 24
18, 19
20, 21
22, 23
26
VDDO_C
Power output supply pin for Bank C LVDS outputs.
Differential Bank C clock outputs. LVDS interface levels.
Differential Bank C clock outputs. LVDS interface levels.
Differential Bank C clock outputs. LVDS interface levels.
Analog supply pin.
QC0, nQC0
QC1, nQC1
QC2, nQC2
VDDA
Output enable and configuration pins. See Table 3.
Pulldown
27, 29
28
OE0, OE2
OE1
Input
Input
Input
LVCMOS/LVTTL interface levels.
Output enable and configuration pin. See Table 3.
LVCMOS/LVTTL interface levels.
Pullup
XTAL_IN,
XTAL_OUT
30, 31
Crystal oscillator interface. XTAL_OUT is the output, XTAL_IN is the input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
Power Dissipation
Capacitance (per output)
CPD
VDD, VDDO_A, VDDO_B, VDDO_C = 3.465V
15
pF
RPULLUP
Input Pullup Resistor
51
51
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
QA[0:2],
Output
ROUT
QB[0:2],
20
Ω
Impedance
REF_OUT
ICS8402015AKI REVISION A JUNE 25, 2009
3
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Function Table
Table 3. OE Function and ConfigurationTable
Inputs
Output Frequency (MHz)
Bank B
B1
Bank A
Bank C
C1
OE2
0
OE1
0
OE0
0
A0
25
A1
Hi-Z
Hi-Z
25
A2
B0
B2
C0
125
125
125
125
125
125
125
Hi-Z
C2
Hi-Z
Hi-Z
Hi-Z
25
Hi-Z
125
Hi-Z
125
Hi-Z
125
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
125
Hi-Z
Hi-Z
Hi-Z
125
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
125
Hi-Z
Hi-Z
Hi-Z
125
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
1
25
0*
0
1*
1
0*
1
25
25
25
125
1
0
0
50
Hi-Z
25
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
125
Hi-Z
125
1
0
1
25
1
1
0
50
50
Hi-Z
Hi-Z
125
1
1
1
Hi-Z
Hi-Z
Hi-Z
*Default
ICS8402015AKI REVISION A JUNE 25, 2009
4
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO_LVCMOS + 0.5V
Outputs, IO (LVCMOS)
Outputs, IO (LVDS)
Continuos Current
Surge Current
10mA
15mA
Operating Temperature Range, TA
Package Thermal Impedance, θJA
Storage Temperature, TSTG
-40°C to +85°C
37°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO_A = VDDO_B = VDDO_C = VDDO_REF = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
Core Supply Voltage
Analog Supply Voltage
V
V
VDDA
VDD – 0.36
3.3
VDD
VDDO_A,
VDDO_B,
VDDO_C,
VDDO_REF
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
Analog Supply Current
30
36
mA
mA
IDDA
IDDO_A,
IDDO_B,
IDDO_C,
IDDO_REF
Total Output Supply Current
Outputs Unused
26
mA
ICS8402015AKI REVISION A JUNE 25, 2009
5
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO_A = VDDO_B = VDDO_REF = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
VIH
VIL
Input High Voltage
Input Low Voltage
2
VDD + 0.3
-0.3
0.8
5
V
OE1
VDD = VIN = 3.465V
µA
µA
µA
µA
Input
High Current
IIH
OE0, OE2, MR
OE1
V
DD = VIN = 3.465V
VDD = 3.465V
150
-150
-5
Input
Low Current
IIL
OE0, OE2, MR
VDD = 3.465V
QA0:QA2,
QB0:QB2,
REF_OUT
Output
High Voltage
VOH
VDDO_REF = 3.3V 5ꢀ, IOH = -12mA
VDDO_REF = 3.3V 5ꢀ, IOL = 12mA
2.6
V
V
QA0:QA2,
QB0:QB2,
REF_OUT
Output
Low Voltage
VOL
0.5
Table 4D. LVDS DC Characteristics, VDD = VDDO_C = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
575
50
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
300
450
∆VOD
VOS
1.325
1.4
1.575
50
∆VOS
IOz
VOS Magnitude Change
High Impedance Leakage
Power Off Leakage
mV
µA
-10
-20
+10
+20
-5
IOFF
µA
IOSD
IOS
Differential Output Short Circuit Current
Output Short Circuit Current
-3.5
-3.5
mA
mA
-5
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Frequency
Fundamental
25
MHz
Ω
Equivalent Series Resistance
Shunt Capacitance
50
7
pF
ICS8402015AKI REVISION A JUNE 25, 2009
6
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 6. AC Characteristics, VDD = VDDO_A = VDDO_B = VDDO_C = VDDO_REF = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
25
Maximum
Units
MHz
MHz
MHz
QA[0:2]
QA[0:1]
QB[0:2]
50
125
fout
Output Frequency
QC[0:2]/
nQC[0:2]
125
25
MHz
MHz
ps
REF_OUT
QA0:QA2,
REF_OUT
25MHz, Integration Range:
12kHz - 1MHz
0.642
RMS Phase Noise
Jitter; NOTE 1
125MHz, Integration Range:
637kHz - 62.5MHz
tjit(Ø)
QB0:QB2
QC0:QC2
0.389
0.373
ps
ps
125MHz, Integration Range:
637kHz - 62.5MHz
QA[0:2], QB[0:2]
QC[0:2]/nQC[0:2]
45
35
ps
ps
Bank Skew;
NOTE 2, 3
tsk(b)
QA[0:2], QB[0:2],
REF_OUT
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
0.425
145
48
1.15
415
52
ns
ps
ꢀ
ꢀ
Output
Rise/Fall Time
tR / tF
QC[0:2]/
nQC[0:2]
QA[0:2], QB[0:2],
REF_OUT
Output
Duty Cycle
odc
QC[0:2]/
nQC[0:2]
48
52
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Please refer to Phase Noise Plots.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
ICS8402015AKI REVISION A JUNE 25, 2009
7
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Parameter Measurement Information
1.65V 5ꢀ
1.65V 5ꢀ
SCOPE
Qx
V
SCOPE
DD,
V
DD,
3.3V 5ꢀ
POWER SUPPLY
V
DDO_C
V
DDO_A,
+
Float GND –
LVDVS
V
DDA
V
DDOL_VB CMODSDA
Qx
nQx
GND
-1.65V 5ꢀ
3.3V LVDS Output Load AC Test Circuit
3.3V LVCMOS Output Load AC Test Circuit
Phase Noise Plot
nQC[0:2]
Qx[0:2]
Phase Noise Mask
nQC[0:2]
Qx[0:2]
tsk(b)
Offset Frequency
f1
f2
Where X = Bank A, Bank B or Bank C outputs
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS Phase Jitter
Bank Skew
VDDO_CMOS
2
nQC{0:2]
QC{0:2]
QA[0:2],
QB[0:2]
tPW
tPW
tPERIOD
tPERIOD
tPW
tPW
odc =
x 100ꢀ
x 100ꢀ
odc =
tPERIOD
tPERIOD
Single-Ended Output Duty Cycle/Pulse Width/Period
Differential Output Duty Cycle/Pulse Width/Period
ICS8402015AKI REVISION A JUNE 25, 2009
8
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Parameter Measurement Information, continued
nQC{0:2]
80ꢀ
tF
80ꢀ
80ꢀ
80ꢀ
tR
VOD
20ꢀ
20ꢀ
20ꢀ
20ꢀ
QA[0:2], QB[0:2]
QC{0:2]
tF
tR
LVCMOS Output Rise/Fall Time
LVDS Output Rise/Fall Time
out
VDD
IOZ
out
out
3.3V 5ꢀ POWER SUPPLY
Float GND
DC Inpu
t
LVDS
_
+
IOSD
DC Input
LVDS
out
IOZ
High Impedance Leakage Current Setup
Differential Output Short Circuit Setup
VDD
VDD
out
➤
out
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/∆ VOD
out
➤
VOS/∆ VOS
➤
Differential Output Voltage Setup
Offset Voltage Setup
ICS8402015AKI REVISION A JUNE 25, 2009
9
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Parameter Measurement Information, continued
VDD
out
IOS
LVDS
DC Input
LVDS
VDD
IOSB
IOFF
out
Power Off Leakage Setup
Output Short Circuit Current Setup
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS8402015I provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD, VDDA, VDDO_A, VDDO_B, VDDO_C, and
VDDO_REF should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used for
each pin. Figure 1 illustrates this for a generic VDD pin and also
shows that VDDA requires that an additional 10Ω resistor along with
a 10µF bypass capacitor be connected to the VDDA pin.
3.3V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVDS Outputs
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
All unused LVDS outputs should be terminated with 100Ω resistor
between the differential pair.
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no
trace attached.
ICS8402015AKI REVISION A JUNE 25, 2009
10
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Crystal Input Interface
The ICS8402015I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
XTAL_OUT
C2
27p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and R2
can be 100Ω. This can also be accomplished by removing R1 and
making R2 50Ω.
VDD
VDD
R1
0.1µf
50Ω
Ro
Rs
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
ICS8402015AKI REVISION A JUNE 25, 2009
11
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω differential
transmission line environment, LVDS drivers require a matched load
termination of 100Ω across near the receiver input. For a multiple
LVDS outputs buffer, if only partial outputs are used, it is
recommended to terminate the unused outputs.
3.3V
50Ω
3.3V
LVDS Driver
+
–
R1
100Ω
50Ω
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
ICS8402015AKI REVISION A JUNE 25, 2009
12
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 5. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
Thermally/Electrically Enhance Leadframe Base Package, Amkor
Technology.
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
ICS8402015AKI REVISION A JUNE 25, 2009
13
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Schematic Example
Figure 6 shows an example of ICS8402015I application schematic. In
frequency accuracy. For different board layouts, the C1 and C2 may
be slightly adjusted for optimizing frequency accuracy. Two example
of LVDS for receiver without built-in termination and one example of
LVCMOS are shown in this schematic.
this example, the device is operated at VDD = VDDO_REF = VDDO_A
=
VDDO_B = VDDO_C = 3.3V. The 18pF parallel resonant 25MHz crystal
is used. The C1 = 27pF and C2 = 27pF are recommended for
Logic Input Pin Examples
QC2
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
RU1
1K
RU2
Not Install
nQC2
Zo = 50 Ohm
Zo = 50 Ohm
QC2
+
-
To Logic
Input
To Logic
R1
Input
pins
100
pins
nQC2
VDDO
RD1
RD2
1K
Not Install
VDD=3.3V
QC0
U1
VDDO=3.3V
VDD
R2
10
nQC0
VDD
VDDA
C3
0.01uF
C6
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
GND
GND
VDD
10uF
VDD
MR
Zo = 50 Ohm
VDDA
OE0
OE0
OE1
OE2
QC0
MR
OE1
GND
QB2
QB2
OE2
QB2
XTAL_I N
R3
50
XTAL_IN
XTAL_OUT
GND
QB1
18pF
QB0
+
-
C1
C4
VDDO_B
27pF
X1
0.1uF
25MHz
C5
0.1uF
R4
50
XTAL_OU T
Zo = 50 Ohm
nQC0
C2
27pF
Alternate
LVDS
Termination
VDDO
(U1:1) VDDO (U1:8) (U1:9)
R5
30
Zo = 50 Ohm
(U1:17)
(U1:24)
C7
C8
C9
C10
0.1uF
C11
0.1uF
0.1uF
0.1uF
0.1uF
LVCMOS
R6
30
Zo = 50 Ohm
REF_OUT
LVCMOS
Figure 6.ICS8402015I Schematic Example
ICS8402015AKI REVISION A JUNE 25, 2009
14
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8402015I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8402015I is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
Core and LVDS Output Power Dissipation
•
Power (core, LVDS) = VDD_MAX * (IDD + IDDO_X + IDDA) = 3.465V * (30mA + 26mA + 36mA) = 318.78mW
LVCMOS Output Power Dissipation
•
•
•
Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDDO/2
Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 20Ω)] = 24.7mA
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 20Ω * (24.7mA)2 = 12.25mW per output
Total Power Dissipation on the ROUT
Total Power (ROUT) = 12.25mW * 6 = 73.5mW
Total Power Dissipation
•
Total Power
= Power (core, LVDS) + Total Power (ROUT
= 318.78mW + 73.5mW
= 392.28mW
)
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 37°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.392W * 37°C/W = 99.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection
θJA Vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
29.0°C/W
ICS8402015AKI REVISION A JUNE 25, 2009
15
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Reliability Information
Table 8. θJA vs. Air Flow Table for a 32 Lead VFQFN
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
29.0°C/W
Transistor Count
The transistor count for ICS8402015I is: 2311
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
N & N
Even
Seating Plane
(N -1)x e
(Ref.)
A1
IndexArea
L
A3
E2
e
2
N
N
(Ty p.)
If N & N
are Even
Anvil
Singulation
1
2
(N -1)x e
OR
(Ref.)
E2
2
TopView
D
b
(Ref.)e
N &N
Odd
Thermal
Base
A
D2
2
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9.
Table 9. Package Dimensions
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
0
1.00
0.05
A1
A3
0.25 Ref.
0.25
b
ND & NE
D & E
D2 & E2
e
0.18
0.30
8
5.00 Basic
3.0
3.3
0.50 Basic
0.40
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
ICS8402015AKI REVISION A JUNE 25, 2009
16
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Ordering Information
Table 10. Ordering Information
Part/Order Number
8402015AKILF
8402015AKILFT
Marking
ICS02015AIL
ICS02015AIL
Package
“Lead-Free” 32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
Shipping Packaging
Tray
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS8402015AKI REVISION A JUNE 25, 2009
17
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
A
T10
17
Ordering Information Table - added “I” in part/order number.
6/25/09
ICS8402015AKI REVISION A JUNE 25, 2009
18
©2009 Integrated Device Technology, Inc.
ICS8402015I Datasheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
San Jose, California 95138
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2009. All rights reserved.
相关型号：
ICS84021AYLF
Clock Generator, 260MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32
IDT
ICS840245AGILF
Clock Generator, 75MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
ICS840245AGILFT
Clock Generator, 75MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
©2020 ICPDF网 联系我们和版权申明