MPC93R51FA [IDT]
PLL Based Clock Driver, 93R Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, LQFP-32;
| 型号： | MPC93R51FA |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 93R Series, 9 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总13页 (文件大小：353K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Voltage PLL Clock Driver
MPC93R51
NRND
DATASHEET
NRND – Not Recommend for New Designs
The MPC93R51 is a 3.3 V compatible, PLL based clock generator targeted for
high performance clock distribution systems. With output frequencies of up to
240 MHz and a maximum output skew of 150 ps, the MPC93R51 is an ideal
solution for the most demanding clock tree designs. The device offers 9 low skew
clock outputs, each is configurable to support the clocking needs of the various
high-performance microprocessors including the PowerQuicc II integrated
communication microprocessor. The devices employ a fully differential PLL
design to minimize cycle-to-cycle and long-term jitter.
MPC93R51
LOW VOLTAGE 3.3 V
PLL CLOCK GENERATOR
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
9 Outputs LVCMOS PLL Clock Generator
25–240 MHz Output Frequency Range
Fully Integrated PLL
Compatible to Various Microprocessors Such as PowerQuicc II
Supports Networking, Telecommunications and Computer Applications
Configurable Outputs: Divide-by-2, 4 and 8 of VCO Frequency
LVPECL and LVCMOS Compatible Inputs
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
External Feedback Enables Zero-Delay Configurations
Output Enable/Disable and Static Test Mode (PLL Enable/Disable)
Low Skew Characteristics: Maximum 150 ps Output-to-Output
Cycle-to-Cycle Jitter Max. 22 ps RMS
32-Lead LQFP Package
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
32-Lead Pb-Free Package Available
Ambient Temperature Range 0°C to +70°C
Pin and Function Compatible With the MPC951
Not Recommend for New Designs
Functional Description
The MPC93R51 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal
operation of the MPC93R51 requires a connection of one of the device outputs to the EXT_FB input to close the PLL feedback
path. The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be
selected to match the VCO frequency range. With available output dividers of divide-by-4 and divide-by-8, the internal VCO of
the MPC93R51 is running at either 4x or 8x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs
is either the one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using
the FSELA, FSELB, FSELC and FSELD pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2
and 1:4. The REF_SEL pin selects the differential LVPECL (PCLK and PCLK) or the LVCMOS compatible reference input
(TCLK). The MPC93R51 also provides a static test mode when the PLL enable pin (PLL_EN) is pulled to logic low state. In test
mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode is intended
for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency specification
does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE causes
the PLL to loose lock due to no feedback signal presence at EXT_FB. Asserting OE will enable the outputs and close the phase
locked loop, also enabling the PLL to recover to normal operation. The MPC93R51 is 3.3 V compatible and requires no external
loop filter components. All inputs except PCLK and PCLK accept LVCMOS signals while the outputs provide LVCMOS compatible
levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the
MPC93R51 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a
7x7 mm2 32-lead LQFP package.
Application Information
The fully integrated PLL of the MPC93R51 allows the low skew outputs to lock onto a clock input and distribute it with
essentially zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase
offset between the outputs and the reference signal.
MPC93R51 REVISION 4 JANUARY 31, 2013
1
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
(Pullup)
PCLK
PCLK
0
1
0
1
2
4
8
0
1
Ref
FB
(Pulldown)
D
D
D
Q
Q
Q
QA
QB
TCLK
PLL
(Pulldown)
(Pulldown)
REF_SEL
EXT_FB
0
1
200 – 480 MHz
(Pullup)
PLL_EN
QC0
QC1
0
1
(Pulldown)
(Pulldown)
(Pulldown)
FSELA
FSELB
QD0
FSELC
FSELD
(Pulldown)
QD1
QD2
QD3
QD4
0
1
D
Q
(Pulldown)
OE
The MPC93R51 requires an external RC filter for the analog power supply pin VCCA. Please see Applications Information for details.
Figure 1. MPC93R51 Logic Diagram
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
QD2
VCCO
QD3
GND
QD4
VCCO
GND
QB
VCCO
QA
MPC93R51
GND
TCLK
PLL_EN
REF_SEL
OE
PCLK
1
2
3
4
5
6
7
8
Figure 2. Pinout: 32-Lead Package Pinout (Top View)
MPC93R51 REVISION 4 JANUARY 31, 2013
2
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
Table 1. Pin Description
Number
Name
Type
Description
PCLK, PCLK
Input
LVPECL
Differential clock reference
Low voltage positive ECL input
TCLK
Input
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
VCC
Single ended reference clock signal or test clock
EXT_FB
REF_SEL
FSELA
FSELB
FSELC
FSELD
OE
Feedback signal input, connect to a QA, QB, QC, QD output
Selects input reference clock
Output A divider selection
Output B divider selection
Outputs C divider selection
Outputs D divider selection
Output enable/disable
Input
Input
Input
Input
Input
Input
QA
Output
Output
Output
Output
Supply
Bank A clock output
QB
Bank B clock output
QC0, QC1
QD0 – QD4
VCCA
Bank C clock outputs
Bank D clock outputs
Positive power supply for the PLL
VCC
Supply
Supply
VCC
Positive power supply for I/O and core
Negative power supply
GND
Ground
Table 2. Function Table
Control
REF_SEL
PLL_EN
Default
0
1
0
1
Selects PCLK as reference clock
Selects TCLK as reference clock
Test mode with PLL disabled. The input clock is PLL enabled. The VCO output is routed to the
directly routed to the output dividers
output dividers
OE
0
Outputs enabled
Outputs disabled, PLL loop is open
VCO is forced to its minimum frequency
FSELA
FSELB
FSELC
FSELD
0
0
0
0
QA = VCO 2
QB = VCO 4
QC = VCO 4
QD = VCO 4
QA = VCO 4
QB = VCO 8
QC = VCO 8
QD = VCO 8
Table 3. Absolute Maximum Ratings(1)
Symbol
VCC
VIN
Characteristics
Min
-0.3
-0.3
-0.3
Max
4.6
Unit
Supply Voltage
V
V
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
VCC+0.3
VCC+0.3
20
VOUT
IIN
IOUT
TS
V
mA
mA
°C
50
-55
150
MPC93R51 REVISION 4 JANUARY 31, 2013
3
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated
conditions is not implied.
Table 4. General Specifications
Symbol
VTT
Characteristics
Output Termination Voltage
ESD (Machine Model)
ESD (Human Body Model)
Latch-Up
Min
Typ
Max
Unit
V
Condition
VCC 2
MM
200
2000
200
V
HBM
LU
V
mA
pF
pF
CPD
CIN
Power Dissipation Capacitance
10
Per output
Inputs
4.0
Table 5. DC Characteristics (VCC = 3.3 V 5%, TA = 0° to 70°C)
Symbol
VIH
Characteristics
Input High Voltage
Min
Typ
Max
Unit
V
Condition
2.0
VCC + 0.3
0.8
LVCMOS
LVCMOS
LVPECL
LVPECL
VIL
Input Low Voltage
V
VPP
Peak-to-Peak Input Voltage PCLK, PCLK
250
1.0
2.4
mV
V
(1)
VCMR
Common Mode Range
Output High Voltage
PCLK, PCLK
VCC–0.6
IOH = –24 mA(2)
VOH
VOL
V
Output Low Voltage
0.55
0.30
V
V
IOL = 24 mA
IOL = 12 mA
ZOUT
IIN
Output Impedance
14 –17
Input Leakage Current
150
5.0
A
VIN = VCC or GND
VCCA Pin
ICCA
ICCQ
Maximum PLL Supply Current
3.0
7.0
mA
mA
Maximum Quiescent Supply Current
10
All VCC Pins
1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
2. The MPC93R51 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
MPC93R51 REVISION 4 JANUARY 31, 2013
4
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
Table 6. AC Characteristics (VCC = 3.3 V 5%, TA = 0° to 70°C)(1)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Input Frequency(2)
4 feedback
8 feedback
Static test mode
fref
50
25
0
120
60
300
MHz PLL_EN = 1
MHz PLL_EN = 1
MHz PLL_EN = 0
fVCO
fMAX
VCO Frequency
200
480
MHz
Maximum Output Frequency(2) 2 output
100
50
25
240
120
60
MHz
MHz
MHz
4 output
8 output
frefDC
VPP
Reference Input Duty Cycle
25
500
1.2
75
1000
%
Peak-to-Peak Input Voltage PCLK, PCLK
mV
V
LVPECL
(3)
VCMR
Common Mode Range
PCLK, PCLK
VCC–0.9
1.0
LVPECL
tr, tf(4)
t()
TCLK Input Rise/Fall Time
ns
0.8 to 2.0 V
Propagation Delay (static phase offset)
TCLK to EXT_FB
-50
+25
+150
+325
ps
ps
PLL locked
PLL locked
PCLK to EXT_FB
tsk(o)
DC
Output-to-Output Skew
Output Duty Cycle
150
ps
100 – 240 MHz
50 – 120 MHz
25 – 60 MHz
45
47.5
48.75
50
50
50
55
52.5
51.75
%
%
%
tr, tf
tPLZ, HZ
tPZL, ZH
BW
Output Rise/Fall Time
Output Disable Time
Output Enable Time
0.1
1.0
7.0
6.0
ns
ns
ns
0.55 to 2.4 V
PLL closed loop bandwidth
4 feedback
8 feedback
3.0 – 9.5
1.2 – 2.1
MHz –3 db point of
MHz PLL transfer characteristic
tJIT(CC)
Cycle-to-cycle jitter
Single Output Frequency Configuration
4 feedback
10
22
15
ps
ps
RMS value
RMS value
RMS value
tJIT(PER)
Period Jitter
Single Output Frequency Configuration
4 feedback
8.0
tJIT()
tLOCK
I/O Phase Jitter
4.0 – 17
ps
Maximum PLL Lock Time
1.0
ms
1. AC characteristics apply for parallel output termination of 50 to VTT.
2. The PLL will be unstable with a divide by 2 feedback ratio
3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t()
.
4. The MPC93R51 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(), can only be guaranteed if tr/tf
are within the specified range.
MPC93R51 REVISION 4 JANUARY 31, 2013
5
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
APPLICATIONS INFORMATION
The output division settings establish the output
Programming the MPC93R51
relationship. In addition, it must be ensured that the VCO will
be stable given the frequency of the outputs desired. The
feedback frequency should be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL supports output frequencies from 25 MHz to
240 MHz while the VCO frequency range is specified from
200 MHz to 480 MHz and should not be exceeded for stable
operation.
The MPC93R51 clock driver outputs can be configured
into several divider modes. In addition, the external feedback
of the device allows for flexibility in establishing various input
to output frequency relationships. The output divider of the
four output groups allows the user to configure the outputs
into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even
dividers ensure that the output duty cycle is always 50%.
Table 7 illustrates the various output configurations. The
table describes the outputs using the input clock frequency
CLK as a reference.
Table 7. Output Frequency Relationship(1) for an Example Configuration
Inputs
Outputs
FSELA
FSELB
FSELC
FSELD
QA
QB
CLK
QC
QD
CLK
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2 * CLK
2 * CLK
4 * CLK
4 * CLK
2 * CLK
2 * CLK
4 * CLK
4 * CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK 2
2* CLK
CLK
2 * CLK
2 * CLK
CLK 2
CLK 2
CLK
CLK
CLK 2
2 * CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK 2
2 * CLK
CLK
2 * CLK
2 * CLK
CLK
2 * CLK
2 * CLK
CLK 2
CLK 2
CLK
CLK
CLK
CLK 2
2 * CLK
CLK
2 * CLK
2 * CLK
CLK
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB.
Using the MPC93R51 in Zero-Delay Applications
consists of the static phase offset (SPO or t()), I/O jitter
(tJIT(), phase or long-term jitter), feedback path delay and
the output-to-output skew (tSK(O) relative to the feedback
output.
Nested clock trees are typical applications for the
MPC93R51. For these applications the MPC93R51 offers a
differential LVPECL clock input pair as a PLL reference. This
allows for the use of differential LVPECL primary clock
distribution devices such as the Freescale MC100EP111 or
MC10EP222, taking advantage of its superior low-skew
performance. Clock trees using LVPECL for clock distribution
and the MPC93R51 as LVCMOS PLL fanout buffer with zero
insertion delay will show significantly lower clock skew than
clock distributions developed from CMOS fanout buffers.
The external feedback option of the MPC93R51 PLL
allows for its use as a zero delay buffer. The PLL aligns the
feedback clock output edge with the clock input reference
edge and virtually eliminates the propagation delay through
the device.
The remaining insertion delay (skew error) of the
MPC93R51 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
MPC93R51 REVISION 4 JANUARY 31, 2013
6
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
Table 8. Confidence Factor CF
fref = 100 MHz
1
1
2
3
4
5
6
0.68268948
0.95449988
QA
QB
TCLK
2 x 100 MHz
2 x 100 MHz
REF_SEL
QC0
QC1
0.99730007
0.99993663
0.99999943
0.99999999
PLL_EN
FSELA
FSELB
FSELC
FSELD
1
1
0
0
0
QD0
QD1
QD2
QD3
4 x 100 MHz
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation, an
I/O jitter confidence factor of 99.7% ( 3) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –251 ps to 351 ps relative to TCLK (VCC = 3.3 V and
fVCO = 400 MHz):
QD4
Ext_FB
MPC93R51
100 MHz (Feedback)
Figure 3. MPC93R51 Zero-Delay Configuration
(Feedback of QD4)
tSK(PP) = [-50ps...150ps] + [-150ps...150ps] +
[(17ps · –3)...(17ps ·3)] + tPD, LINE(FB)
Calculation of Part-to-Part Skew
tSK(PP) = [-251ps...351ps] + tPD, LINE(FB)
The MPC93R51 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs (TCLK or PCLK)
of two or more MPC93R51 are connected together, the
maximum overall timing uncertainty from the common TCLK
input to any output is:
Above equation uses the maximum I/O jitter number
shown in the AC characteristic table for VCC = 3.3 V (17 ps
RMS). I/O jitter is frequency dependent with a maximum at
the lowest VCO frequency (200 MHz for the MPC93R51).
Applications using a higher VCO frequency exhibit less I/O
jitter than the AC characteristic limit. The I/O jitter
characteristics in Figure 5 can be used to derive a smaller
I/O jitter number at the specific VCO frequency, resulting in
tighter timing limits in zero-delay mode and for part-to-part
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() · CF
This maximum timing uncertainty consists of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter.
skew tSK(PP)
.
Max. I/O Jitter versus frequency
TCLKCommon
tPD,LINE(FB)
30
25
20
15
10
5
—t(
QFBDevice 1
tJIT()
Any QDevice 1
+tSK(O)
0
+t()
75
225
250
275 300
325
350
375
400
VCO frequency [MHz]
QFBDevice2
tJIT()
Figure 5. Max. I/O Jitter (RMS) Versus Frequency
for VCC = 3.3 V
Any QDevice 2
+tSK(O)
Power Supply Filtering
The MPC93R51 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Noise on the VCCA (PLL) power supply impacts the device
characteristics, for instance, I/O jitter. The MPC93R51
provides separate power supplies for the output buffers (VCC
and the phase-locked loop (VCCA) of the device. The purpose
of this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies, a
Max. skew
tSK(PP)
Figure 4. MPC93R51 Max. Device-to-Device Skew
Due to the statistical nature of I/O jitter, a RMS value (1 )
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 8.
)
Table 8. Confidence Factor CF
CF
Probability of clock edge within the distribution
MPC93R51 REVISION 4 JANUARY 31, 2013
7
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the VCCA
pin for the MPC93R51.
Figure 6 illustrates a typical power supply filter scheme.
The MPC93R51 frequency and phase stability is most
susceptible to noise with spectral content in the 100 kHz to 20
MHz range; therefore, the filter should be designed to target
this range. The key parameter that needs to be met in the
final filter design is the DC voltage drop across the series filter
resistor RF. From the data sheet, the ICCA current (the current
sourced through the VCCA pin) is typically 3 mA (5 mA
maximum), assuming that a minimum of 3.0 V must be
maintained on the VCCA pin. The resistor RF shown in
Figure 6 must have a resistance of 5-15 to meet the
voltage drop criteria.
MPC93R51 REVISION 4 JANUARY 31, 2013
8
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
RF
MPC93R51
OUTPUT
BUFFER
VCCA
MPC93R51
VCC
22 pF
0.1 F
0.1 F
ZO = 50
RS = 36
14
OutA
IN
IN
VCC
MPC93R51
OUTPUT
BUFFER
ZO = 50
RS = 36
RS = 36
OutB0
Figure 6. VCCA Power Supply Filter
14
As the noise frequency crosses the series resonant point
of an individual capacitor, its overall impedance begins to
look inductive, and thus, increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC93R51 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
ZO = 50
OutB1
Figure 7. Single versus Dual Transmission Lines
The waveform plots in Figure 8 show the simulation results
of an output driving a single line versus two lines. In both
cases, the drive capability of the MPC93R51 output buffer is
more than sufficient to drive 50 transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC93R51. The output
waveform in Figure 8 shows a step in the waveform. This
step is caused by the impedance mismatch seen looking into
the driver. The parallel combination of the 36 series
resistor, plus the output impedance, does not match the
parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
Driving Transmission Lines
The MPC93R51 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 resistance to VCC2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC93R51 clock driver. For the series
terminated case, however, there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 7 illustrates an output driving a single series
terminated line versus two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC93R51 clock
driver is effectively doubled due to its capability to drive
multiple lines.
VL = VS (Z0 (RS+R0 +Z0))
Z0 = 50 || 50
RS = 36 || 36
R0 = 14
VL = 3.0 (25 (18+17+25)
= 1.31 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
MPC93R51 REVISION 4 JANUARY 31, 2013
9
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
Since this step is well above the threshold region it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines, the
situation in Figure 9 should be used. In this case, the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
3.0
2.5
2.0
1.5
1.0
0.5
0
OutA
tD = 3.8956
OutB
tD = 3.9386
In
MPC93R51
OUTPUT
ZO = 50
RS = 22
RS = 22
BUFFER
14
Z
O = 50
2
4
6
8
10
12
14
14+ 22 || 22 = 50 || 50
25 = 25
TIME (ns)
Figure 8. Single versus Dual Waveforms
Figure 9. Optimized Dual Line Termination
MPC93R51 DUT
Pulse
Generator
Z = 50
ZO = 50
ZO = 50
RT = 50
RT = 50
VTT
VTT
Figure 10. CLK MPC93R51 AC Test Reference for VCC = 3.3 V
MPC93R51 DUT
ZO = 50
Differential Pulse
Generator
Z
O = 50
Z = 50
RT = 50
RT = 50
VTT
VTT
Figure 11. PCLK MPC9R351 AC Test Reference
MPC93R51 REVISION 4 JANUARY 31, 2013
10
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
PCLK
PCLK
VCC
TCLK
VCC 2
VCMR
VCMR
GND
VCC
VCC
VCC 2
VCC 2
Ext_FB
Ext_FB
GND
GND
t()
t()
Figure 12. Propagation Delay (tPD, Static Phase
Offset) Test Reference
Figure 13. Propagation Delay (tPD) Test Reference
VCC
VCC
VCC 2
VCC 2
GND
GND
tP
VCC
VCC 2
T0
GND
DC = tP/T0 x 100%
tSK(O)
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device.
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
Figure 14. Output Duty Cycle (DC)
Figure 15. Output-to-Output Skew tSK(O)
TJIT(CC) = |TN–TN+1
|
TJIT(PER) = |TN–1/f0|
TN
TN+1
T0
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs.
The deviation in cycle time of a signal with respect to the ideal
period over a random sample of cycles.
Figure 16. Cycle-to-Cycle Jitter
Figure 17. Period Jitter
TCLK
(PCLK)
VCC=3.3 V
2.4
Ext_FB
TJIT() = |T0–T1mean|
0.55
tF
tR
The deviation in t0 for a controlled edge with respect to a t0 mean
in a random sample of cycles.
Figure 18. I/O Jitter
Figure 19. Transition Time Test Reference
MPC93R51 REVISION 4 JANUARY 31, 2013
11
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
Revision History Sheet
Rev
4
Table
Page
Description of Change
Date
1
1
NRND – Not Recommend for New Designs
Removed replacement part from features list.
12/20/12
1/31/13
4
MPC93R51 REVISION 4 JANUARY 31, 2013
12
©2013 Integrated Device Technology, Inc.
MPC93R51 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
We’ve Got Your Timing Solution
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
San Jose, California 95138
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to signifi-
cantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2013. All rights reserved.
相关型号：
MPC93R51FAR2
PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC, LQFP-32
MOTOROLA
MPC93R52ACR2
93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD FREE, LQFP-32
NXP
MPC93R52FA
PLL Based Clock Driver, 11 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, PLASTIC, LQFP-32
MOTOROLA
MPC93R52FAR2
PLL Based Clock Driver, 93R Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, PLASTIC, LQFP-32
IDT
MPC93R52FAR2
PLL Based Clock Driver, 11 True Output(s), 0 Inverted Output(s), PQFP32, PLASTIC, LQFP-32
MOTOROLA
©2020 ICPDF网 联系我们和版权申明