ESD5V3L1B02LSE6327XTSA1 [INFINEON]
Trans Voltage Suppressor Diode, 5.3V V(RWM), Bidirectional, 1 Element, Silicon, 0.62 X 0.32 MM, 0.31 MM HEIGHT, GREEN, PLASTIC, TSSLP-2-1, 2 PIN;
| 型号： | ESD5V3L1B02LSE6327XTSA1 |
| 厂家： | 
Infineon |
| 描述： | Trans Voltage Suppressor Diode, 5.3V V(RWM), Bidirectional, 1 Element, Silicon, 0.62 X 0.32 MM, 0.31 MM HEIGHT, GREEN, PLASTIC, TSSLP-2-1, 2 PIN |
| 文件： | 总17页 (文件大小：1607K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TVS Diode
Transient Voltage Suppressor Diodes
ESD5V3L1B Series
Bi-directional Low Capacitance ESD / Transient Protection Diode
ESD5V3L1B-02LRH
ESD5V3L1B-02LS
Data Sheet
Revision 1.1, 2012-10-15
Final
Power Management & Multimarket
Edition 2012-10-15
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2012 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ESD5V3L1B Series
Revision History Revision 1, 2011-08-04
Page or Item
Subjects (major changes since previous revision)
Revision 1.1, 2012-10-15
5
Table 2-1 updated
Figure 3-3 and Figure 3-4 updated
8/9
Trademarks of Infineon Technologies AG
AURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™,
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MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™,
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SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™,
TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™
of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc.,
OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc.
RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc.
SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden
Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA.
UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™
of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of
Diodes Zetex Limited.
Last Trademarks Update 2010-10-26
Final Data Sheet
3
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Bi-directional Low Capacitance ESD / Transient Protection Diode
1
Bi-directional Low Capacitance ESD / Transient Protection Diode
1.1
Features
•
ESD / transient protection of signal lines in low voltage applications according to:
– IEC61000-4-2 (ESD): ±20 kV (air / contact)
– IEC61000-4-4 (EFT): 40 A (5/50 ns)
•
•
•
•
Bi-directional, symmetrical working voltage up to VRWM = ±5.3 V
Low capacitance: CL = 5 pF (typical)
Low clamping voltage, low dynamic resistance down to: RDYN = 0.23 Ω (typical)
Pb-free (RoHS compliant) and halogen free package, very small form factor: 0.62 x 0.32 x 0.31 mm3
1.2
Application Examples
•
•
•
Keypad, touchpad, buttons, convenience keys
LCD displays, Camera, audio lines, mobile communication, Consumer products (E-Book, MP3, DVD, DSC...)
Notebooks tablets and desktop computers and their peripherals
1.3
Product Description
Pin 1
Pin 2
Pin 1
Pin 2
Pin 1 marking
(lasered)
TSLP-2
Pin 1
Pin 2
TSSLP-2
a) Pin configuration
b) Schematic diagram
PG-TS(S)LP-2_Dual_Diode_Serie_PinConf_and_SchematicDiag.vsd
Figure 1-1 Pin Configuration and Schematic Diagram
Table 1-1 Ordering Information
Type
Package
Configuration
Marking code
ESD5V3L1B-02LRH PG-TSLP-2-17
1 line, bi-directional
1 line, bi-directional
4
ESD5V3L1B-02LS
Final Data Sheet
PG-TSSLP-2-1
C
4
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Characteristics
2
Characteristics
Table 2-1 Maximum Ratings at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Typ.
Unit
Min.
–
Max.
20
ESD contact discharge1)
Peak pulse current (tp = 8/20 μs)2) IPP
VESD
–
kV
A
–
3
2.5
Peak pulse power (tp = 8/20 μs)2)
PPP
TOP
Tstg
–
39
–
30
W
°C
°C
Operating temperature range
-40
-65
125
150
Storage temperature
–
1) VESD according to IEC61000-4-2
2) IPP according IEC61000-4-5
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
2.1
Electrical Characteristics at TA = 25 °C, unless otherwise specified
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Figure 2-1 Definitions of electrical characteristics
Final Data Sheet
5
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Characteristics
Table 2-2 DC Characteristics at TA = 25 °C, unless otherwise specified
Parameter Symbol Values
Typ.
Unit
Note /
Test Condition
Min.
-5.3
6
Max.
5.3
Reverse working voltage VRWM
–
–
–
V
Breakdown voltage
Reverse current
VBR
IR
10
V
IBR = 1 mA
–
100
nA
VR = 5.3 V
Table 2-3 RF Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Typ.
Unit
Note /
Test Condition
Min.
Max.
Line capacitance
Series inductance
CL
LS
4
–
–
–
7
–
–
pF
nH
VR = 0 V, f = 1 MHz
PG-TSLP-2-17
0.4
0.2
PG-TSSLP-2-1
Table 2-4 ESD Characteristics at TA = 25 °C, unless otherwise specified
Parameter
Symbol
Values
Typ.
Unit
Note /
Test Condition
Min.
Max.
Clamping voltage1)
VCL
–
10.2
13.2
12.1
17.2
8.5
–
V
I
TLP = 16 A,
from Pin 1 to Pin 2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I
TLP = 30 A,
from Pin 1 to Pin 2
I
TLP = 16 A,
from Pin 2 to Pin 1
I
TLP = 30 A,
from Pin 2 to Pin 1
Clamping voltage2)
I
PP = 1 A,
from Pin 1 to Pin 2
9.8
I
PP = 2.5 A,
from Pin 1 to Pin 2
PP = 1 A,
from Pin 2 to Pin 1
IPP = 2.5 A,
8.5
I
10.4
from Pin 2 to Pin 1
Dynamic resistance2)
RDYN
–
–
0.22
0.37
–
–
Ω
Ω
Pin 1 to Pin 2
Pin 2 to Pin 1
1) Please refer to Application Note AN210 [1]. TLP parameter: Z0 = 50 Ω , tp = 100ns, tr = 300ps, averaging window: t1 = 30 ns
to t2 = 60 ns, extraction of dynamic resistance using least squares fit of TLP characteristics between IPP1 = 10 A and
IPP2 = 40 A.
2) IPP according to IEC61000-4-5 (tp = 8/20 μs)
Final Data Sheet
6
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
3
Typical Characteristics at TA = 25 °C, unless otherwise specified
10-6
10-7
10-8
10-9
10-10
10-11
10-12
-10 -8
-6
-4
-2
0
2
4
6
8
10
VR [V]
Figure 3-1 Reverse current: IR = f(VR)
7
6
5
4
3
2
1
0
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
VR [V]
Figure 3-2 Line capacitance: CL = f(VR), f = 1MHz
Final Data Sheet
7
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
ESD5V3L1B-02xx
R
DYN
40
30
20
15
R
= 0.23 Ω
DYN
20
10
5
10
0
0
-10
-20
-30
-40
-5
-10
-15
-20
R
= 0.36 Ω
DYN
-25 -20 -15 -10
-5
0
5
10
15
20
25
V
[V]
TLP
Figure 3-3 Clamping voltage (TLP): ITLP = f(VTLP) according ANSI/ESD STM5.5.1 - Electrostatic Discharge
Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z0 = 50 Ω,
tp = 100 ns, tr = 0.6 ns, ITLP and VTLP averaging window: t1 = ns to t2 = 60 ns, extraction of
dynamic resistance using squares fit to TLP characteristics between ITLP1 = 10 A and
ITLP2 = 40 mA. Please refer to Application Note AN210[1]
Final Data Sheet
8
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
4
3
ESD5V3L1B-02xx
R
DYN
R
= 0.9 Ω
DYN
2
1
0
-1
-2
-3
-4
R
= 1.4 Ω
DYN
-15
-10
-5
0
5
10
15
V
[V]
CL
Figure 3-4 Pulse current (IEC61000-4-5) versus clamping voltage: IPP = f(VCL)
Final Data Sheet
9
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
70
60
50
40
30
20
10
0
VCL-max-peak = 45.0 [V]
CL-30ns-peak = 10.7 [V]
V
-10
-100
0
100 200 300 400 500 600 700 800 900
tp [ns]
Figure 3-5 IEC61000-4-2: VCL = f(t), 8 kV positive pulse from pin 1 to pin 2
10
0
-10
-20
-30
VCL-max-peak = -66.7 [V]
-40
VCL-30ns-peak = -9.7 [V]
-50
-60
-70
-100
0
100 200 300 400 500 600 700 800 900
tp [ns]
Figure 3-6 IEC61000-4-2: VCL = f(t), 8 kV negative pulse from pin 1 to pin 2
Final Data Sheet
10
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Typical Characteristics at TA = 25 °C, unless otherwise specified
110
100
90
80
70
60
50
40
30
20
10
0
VCL-max-peak = 74.5 [V]
VCL-30ns-peak = 12.0 [V]
-10
-20
-100
0
100 200 300 400 500 600 700 800 900
tp [ns]
Figure 3-7 IEC61000-4-2: VCL = f(t), 15 kV positive pulse from pin 1 to pin 2
20
10
0
-10
-20
-30
-40
-50
-60
VCL-max-peak = -96.9 [V]
-70
VCL-30ns-peak = -15.6 [V]
-80
-90
-100
-110
-100
0
100 200 300 400 500 600 700 800 900
tp [ns]
Figure 3-8 IEC61000-4-2: VCL = f(t), 15 kV negative pulse from pin 1 to pin 2
Final Data Sheet
11
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Application Information
4
Application Information
Protected signal line
1
ESD
I/O sensitive
device
The protection diode should be placed very close to the location
where the ESD or other transients can occur to keep loops and
inductances as small as possible .
Pin 2 (or pin 1) should be connected directly to a ground plane on
the board .
2
Application_ESD5V3S1B-02LS.vsd
Figure 4-1 Single line, bi-directional ESD / Transient protection
Final Data Sheet
12
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Ordering Information Scheme (Examples)
5
Ordering Information Scheme (Examples)
ESD 0P1 RF - XX YY
Package
XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins)
YY = Package family:
LS = TSSLP
LRH = TSLP
For Radio Frequency Applications
Line Capacitance CL in pF: (i.e.: 0P1 = 0.1pF)
ESD 5V3 U n U - XX YY
Package or Application
XX = Pin number (i.e.: 02 = 2 pins; 03 = 3 pins)
YY = Package family:
LS = TSSLP
LRH = TSLP
S = SOT363
U = SC74
XX = Application family:
LC = Low Clamp
HDMI
Uni- / Bi-directional or Rail to Rail protection
Number of protected lines(i.e.: 1 = 1 line; 4 = 4 lines)
Capacitance: Standard (>10pF), Low (<10pF), Ultra-low (<1pF)
Maximum working voltage VRWM in V: (i.e.: 5V3 = 5.3V)
Figure 5-1 Ordering information scheme
Final Data Sheet
13
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Package Information
6
Package Information
6.1
PG-TSLP-2-17 (mm) [2]
Top view
Bottom view
+0ꢀ01
-0ꢀ0ꢂ
0ꢀꢂ9
0ꢀ0ꢁ
0ꢀ6
0ꢀ0ꢁ MAXꢀ
2
1
1)
0ꢀ0ꢂꢁ
0ꢀꢁ
Cathode
marking
1) Dimension applies to plated terminal
TSLP 2 7 PO V02
Figure 6-1 PG-TSLP-2-17: Package overview
0.6
0.45
Copper
Solder mask
Stencil apertures
TSLP-2-7-FP V01
Figure 6-2 PG-TSLP-2-17: Footprint
0ꢀꢁ
4
0ꢀ76
Orientation
marking
TSLP-2-7-TP V0ꢂ
Figure 6-3 PG-TSLP-2-17: Packing
Type code
12
Cathode marking
Figure 6-4 PG-TSLP-2-17: Marking (example)
Final Data Sheet
14
Revision 1.1, 2012-10-15
ESD5V3L1B Series
Package Information
6.2
PG-TSSLP-2-1 (mm) [2]
Top view
Bottom view
+0ꢀ01
-0ꢀ02
0ꢀ31
0ꢀ035
0ꢀ32
2
1
1)
0ꢀ025
0ꢀ26
Cathode
marking
1) Dimension applies to plated terminal
TSSLP-2-1,-2-PO V05
Figure 6-5 PG-TSSLP-2-1: Package overview
0ꢀ32
0ꢀ27
Copper
Solder mask
Stencil apertures
TSSLP-2-1,-2-FP V02
Figure 6-6 PG-TSSLP-2-1: Footprint
0ꢀ35
4
Tape type
Ex Ey
Punched Tape
0ꢀ43 0ꢀ73
Embossed Tape 0ꢀ37 0ꢀ67
Deliveries can be both tape types (no selection possible)ꢀ
Specification allows identical processing (pick & place) by usersꢀ
Cathode
marking
Ex
TSSLP-2-1,-2-TP V03
Figure 6-7 PG-TSSLP-2-1: Packing
Figure 6-8 PG-TSSLP-2-1: Marking (example)
Final Data Sheet
15
Revision 1.1, 2012-10-15
ESD5V3L1B Series
References
References
[1] Infineon AG - Application Note AN210: Effective ESD Protection design at System Level Using VF-TLP
Characterization Methodology
[2] Infineon AG - Recommendations for PCB Assembly of Infineon TSLP and TSSLP Packages
Final Data Sheet
16
Revision 1.1, 2012-10-15
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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