IPD2132 [INFINEON]
LED Display, 8-Character, 4.9mm;
| 型号： | IPD2132 |
| 厂家： | 
Infineon |
| 描述： | LED Display, 8-Character, 4.9mm 功效 驱动 静态存储器 光电 |
| 文件： | 总13页 (文件大小：345K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
YELLOW IPD2131
HIGH EFFICIENCY RED IPD2132
HIGH EFFICIENCY GREEN IPD2133
0.200" 8-Character 5 x 7 Dot Matrix X-Y Stackable
Alphanumeric Programmable Display™
Dimensions in Inches (mm)
1.680 MAX. (42.7)
1.663 MIN.(42.2)
.210
(5.3)
.015
TYP.
(0.4)
.210
REF.
(5.3)
.105
(2.7)
.045
(1.1)
.300
(7.6)
.191
(4.8)
.39
(9.9)
.195
(4.9)
.111 (2.8)
.030 (0.8)
INTENSITY CODE
HUE CATEGORY
EIA DATE CODE
.180
(4.6)
.070 TYP.
(1.8)
.250 MAX.
(6.3)
OSRAM
YYWW
V
Z
IPD213X
SEATING
PLANE
SEATING
PLANE
FEATURES
.500
(12.7)
• Eight 0.2" Dot Matrix Characters in a Ceramic
Package
• True Hermetic Glass Flat Seal for all Colors
• Internal ROM with 128 ASCII Characters
• Internal RAM for up to 16 User Definable
Characters
.020 TYP.(0.5)
.240
(6.1)
.090 TYP.
(2.3)
.100 TYP.
(2.54)
NON-CUM.
.050 TYP.
(1.3)
Tolerance=.XXX±0.015 (0.30)
DESCRIPTION
• Programmable Control Word Allows User to
Select from 8 Brightness Levels, Display Blink,
Character Flash, Self Test, or Clear Functions
• Internal or External Clock Capability
• 8 Bit Bidirectional Data Bus Allows for
Read/Write Capability
• Contains all Display Drive and Multiplexing
Circuitry
• Reset Pin for Display Initialization, Multiple
Display Blinking and Flashing Synchronization
• TTL Compatible
The IPD2131 (yellow), IPD2132 (High Efficiency Red) and IPD2133
(High Efficiency Green) are eight-digit high reliability 5 x 7 dot matrix
Programmable Displays that are aimed at satisfying the most demand-
ing display requirements. They are designed for use in extremely
harsh environments where only the most reliable parts are accept-
able. The devices are constructed in ceramic packages with eight
0.2 inch high 5 x 7 dot matrix digits. The devices incorporate the latest
in CMOS technology which is the heart of the device intelligence. The
CMOS IC is controlled by a user supplied eight-bit data word on a bidi-
rectional BUS. The ASCII data and attribute data are word driven. This
approach allows the displays to interface using similar techniques as a
microprocessor peripheral.
• Operating Temperature Range: –55° to +100°C
Storage Temperature: –65° to +125°C
• Categorized for Luminous Intensity and Color
• X-Y Stackable
Applications include: control panels, night viewing applications, cockpit
monitors, portable and vehicle technology as well as industrial controllers.
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
1
March 28, 2000-00
Switching Specifications
(over operating temperature range and V =4.5 V to 5.5 V)
ESD Warning:
Standard precautions for CMOS
handling should be observed.
CC
Symbol Description
Display Access Time—Write
Min. Units
T
210
230
10
ns
ns
ns
ns
ns
ns
ns
ns
Maximum Ratings (T =25°C)
acc
A
T
Display Access Time—Read
Address Setup Time to CE
Chip Enable Active Time—Write
Chip Enable Active Time—Read
Address Hold Time to CE
DC Supply Voltage, V to GND
(max. voltage with no LEDs on)...................–0.3 to +7.0 VDC
Input Voltage Levels, All Inputs ................... –0.3 to (V +0.3) V
Operating Temperature ................................... –55°C to +100°C
Storage Temperature....................................... –65°C to +125°C
Relative Humidity (non-condensing)....................................85%
Operating Voltage, V to GND
(Max. voltage with 20 dots/digits on).............................. 5.5 V
Maximum Solder Temperature
acc
CC
T
acs
CC
T
140
160
20
ce
T
ce
T
CC
ach
T
Chip Enable Recovery Time
60
cer
(0.063" below Seating Plane, t<5.0 sec.) ...................... 260°C
ESD Protection at 1.5 kΩ, 100 pF...............V =4.0 kV (each pin)
T
Chip Enable Active Prior to
Rising Edge—Write
140
ces
Z
T
Chip Enable Active Prior to
Rising Edge—Read
160
0
ns
ns
ces
Figure 1. Enlarged Character Font
Dimensions in inches (mm)
T
Chip Enable Hold to Rising Edge
of Read/Write Signal
ceh
0.112
(2.85)
T
Write Active Time
100
50
ns
ns
w
C1 C2 C3 C4 C5
R1
T
Data Valid Prior to
Rising Edge of Write Signal
wd
R2
T
Data Write Time
20
ns
ns
dh
R3
R4
R5
R6
R7
0.030
(0.76)
typ.
0.189
(4.81)
T
Chip Enable Active Prior to Valid
Data
160
r
T
Read Active Prior to Valid Data
Read Data Float Delay
Reset Active Time
95
ns
ns
ns
rd
T
10
df
0.026 (0.65) typ.
T
300
rc
Oscillator, Refresh, Flash and Self Test Characteristics
Parameters
Min.
28
Typ.
57.34
—
Max.
81.14
640
Units
kHz
kHz
Hz
Conditions
Clock I/O Frequency
External Clock Frequency
FM, Digit Multiplex Frequency
Blinking Rate
V
V
V
=4.5 V to 5.5 V
=4.5 V to 5.5 V
=4.5 V to 5.5 V
CC
CC
CC
25
125
0.98
—
256
2.0
—
362.5
2.83
2.40
500
Hz
—
—
Clock I/O Bus Loading
Clock Out Rise Time
Clock Out Fall Time
pF
—
—
nsec
nsec
V
=4.5 V, V =2.4 V
OH
CC
CC
—
—
500
V
=4.5 V, V =0.4 V
OH
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2131/2/3
2
March 28, 2000-00
Figure 2. Write Cycle Timing Diagram
T
acc
A0-A3
FL
T
T
acs
ach
T
acs
T
T
ce
T
cer
CE
T
T
ceh
T
ces
T
w
WR
wd
dh
D0-D7
Input pulse levels –0.6 V to 2.4 V
Figure 3. Read Cycle Timing Diagram
T
acc
A0-A3
FL
T
acs
T
ach
T
acs
T
ce
T
cer
CE
RD
T
T
ceh
ces
T
r
T
rd
T
df
D0-D7
Figure 4. Maximum Power Dissipation vs. Ambient
Temperature Derating Based on T max=125°C
J
4.0
3.0
2.0
R
= 30°C/W
θJ–A
1.0
0
25 35 45 55 65 75 85 95 105
TA – °C
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2131/2/3
3
March 28, 2000-00
Optical Characteristics at 25°C (V =5.0 V at full brightness)
CC
Yellow IPD2131
Description
Symbol
Min.
125
—
Typ.
205
583
585
Units
µcd/dot
nm
Luminous Intensity
Peak Wavelength
Dominant Wavelength
I
V
λ
λ
peak
dom
—
nm
High Efficiency Red IPD2132
Description
Symbol
Min.
125
—
Typ.
350
635
626
Units
µcd/dot
nm
Luminous Intensity
Peak Wavelength
I
V
λ
λ
peak
dom
Dominant Wavelength
—
nm
High Efficiency Green IPD2133
Description
Symbol
Min.
150
—
Typ.
500
568
574
Units
µcd/dot
nm
Luminous Intensity
Peak Wavelength
I
V
λ
λ
peak
dom
Dominant Wavelength
—
nm
Electrical Characteristics at 25°C
Parameters
Limits
Min.
4.5
Conditions
Typ.
5.0
Max.
Units
V
V
5.5
—
CC
I
I
I
I
Blank
—
0.5
1.0
mA
mA
mA
µA
V
V
V
V
=5.0 V, V =5.0 V
IN
CC
CC
CC
CC
CC
(1) (2)
(1) (2)
12 dots/digit on
20 dots/digit on
(with pull-up)
—
200
300
–11
255
370
–18
=5.0 V, “V” in all 8 digits
=5.0 V, “#” in all 8 digits
CC
CC
ILP
—
–1.0
=5.0 V, V =0 V to V
N CC
Input Leakage
(WR, CE, FL, RST, RD, CLKSEL)
V =5.0 V, V =0–5.0 V
CC
I
(no pull-up)
–1.0
2.0
—
—
—
+1.0
µA
V
IL
IN
Input Leakage
(CLK, A0–A4, D0–D7)
V
V
V
=4.5 V to 5.5 V
IH
CC
CC
CC
Input Voltage High
+0.3
V
GND
–0.3
0.8
V
V
=4.5 V to 5.5 V
IL
Input Voltage Low
V
V
V
(D0–D7), Output Voltage Low
(CLK), Output Voltage Low
Output Voltage High
—
—
2.4
—
—
—
—
15
0.4
0.4
—
V
V
V
V
=4.5 V, I =1.6 mA
OL
OL
OL
OH
CC
CC
CC
V
=4.5 V, I =40 µA
OL
V
=4.5 V, I =–40 µA
OH
θ
Thermal Resistance,
—
°C/W
—
JC
Junction to Case
Notes:
1)
I
I
is an average value.
is measured with the display at full brightness. Peak I
CC
CC
2)
28
=
/
I
average (#displayed).
CC
CC
15
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
IPD2131/2/3
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
4
March 28, 2000-00
Recommended Operating Conditions (T =–55°C to +100°C)
A
Parameter
Symbol
Min.
4.5
—
Max. Units
Supply Voltage
V
V
V
V
V
5.5
0.8
—
V
V
V
V
V
CC
IL
Input Voltage Low
Input Voltage High
Output Voltage Low
Output Voltage High
2.0
—
IH
0.4
—
OL
OH
2.4
Pin Description
Pin No.
Function
Description
Explanation
1
CLS
Clock Select
Selects an internal or external clock source. CLS=1 the internal clock selected (mas-
ter clock), CLS=0 then external clock selected (slave operation).
2
3
4
5
CLK
WR
CE
Clock I/O
Write
Inputs or outputs the clock as determined by the CLS pin.
Writes data into the display when WR=0 and CE=0.
Enables the read/write access when low.
Chip Enable
Reset
RST
Initializes the display; clears the Character RAM (20 Hex), Flash RAM
(00 Hex), Control Word (00 Hex) and resets the internal counters. UDC Address
Register and UDC RAM are unaffected.
6
RD
Read
—
Outputs data from the display when RD=0 and CE=0.
—
7
No Pin
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
D0
D1
D2
D3
NC
Data Bus
8 bit bidirectional data bus. Character RAM and Control Word uses D7–D0, UDC
Address Register uses D3–D0, UDC RAM uses D4–D0, and Flash RAM uses D0.
—
—
V
—
Positive power supply.
Analog ground for the LED drivers.
Digital ground for the logic circuitry.
CC
GND
GND
D4
Supply
Logic
Data Bus
8 bit bidirectional data bus. Character RAM and Control Word uses D7-D0, UDC
Address Register uses D3-D0, UDC RAM uses D4-D0, and Flash RAM uses D0.
D5
D6
D7
No Pin
—
—
FL
Flash
Accesses the Flash RAM. Address inputs, A2–A0, select the digit address while
data bit D0 sets (D0=1) or resets (D0=0) the Flash bit. A4 and A3 are ignored.
28
29
30
31
32
A0
A1
A2
A3
A4
Address Inputs
A4 and A3 select a section of the display’s memory. A2–A0 select specific locations
in the different sections. If FL is low the Flash RAM is accessed regardless of the
status of A4 and A3.
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2131/2/3
5
March 28, 2000-00
Figure 5. Character Set
Notes:
D0
D1
D2
D3
L
L
L
L
0
H
L
L
L
1
L
H
L
L
2
H
H
L
L
3
L
L
H
L
4
H
L
H
L
L
H
H
L
H
H
H
L
L
L
L
H
8
H
L
L
H
9
L
H
L
H
A
H
H
L
H
B
L
L
H
H
C
H
L
H
H
D
L
H
H
H
E
H
H
H
H
F
ASCII
CODE
1. Upon power up, the device will
initialize in a random state.
2. X=don’t care.
D7 D6 D5 D4 HEX
5
6
7
L
L
L
L
L
L
L
L
L
L
H
L
0
1
2
3
4
5
6
L
L
L
H
H
L
L
H
L
H
H
H
L
H
L
H
L
H
X
H
X
H
X
7
8
UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC
10 11 12 13 14 15
H
0
1
2
3
4
5
6
7
8
9
Figure 6. Cascading Diagram
RD
WR
FL
RST
VCC
RST CLK I/O CLKSEL
Display
D0-D7 A0-A4
RD WR
FL
RD WR
FL
RST CLK I/O CLKSEL
Up to14 More Displays
in between
Display
CE
D0-D7 A0-A4
CE
Data I/O
Address
0
A6
A7
A8
A9
Address
Decoder
Address Decode Chip 1 to 14
15
Cascading Displays
The display’s oscillator is designed to drive up to 16 other dis-
play’s with input loading of 15 pF each.
The following are the general requirements for cascading 16
displays together:
• Determine the correct address for each display.
• Use CE from an address decoder to select the correct display.
• Select one of the Displays to provide the Clock for the other
displays. Connect CLKSEL to V for this display.
CC
• Tie CLKSEL to ground on other displays.
• Use RST to synchronize the blinking between the displays.
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2131/2/3
6
March 28, 2000-00
Figure 7. Block Diagram
OSC
÷32
Counter
÷7
Counter
Row
Drivers
Column
Drivers
8 Digit Display
÷128
Counter
Column
Latch
M
S
l
a
s
t
a
v
e
Cursor
Controls
and
Display
MUX
D Latch
Holding
Register
Character
RAM
Decode
ROM
64
÷3
Counter
5
25
25
ROM
Character
RAM
e
r
Word
Decode
5
Character
Decode
for Display
16
UDC
RAM
Control
Word
Register
Flash
RAM
Self
Test
16
Character
Decode
UDC
Address
Register
4
4
Data Bus
(Read/Write)
Functional Description
The display's user interface is organized into five memory
areas. They are accessed using the Flash Input, FL, and
address lines, A3 and A4. All the listed RAMs and Registers
may be read or written through the data bus. See Table 1. Each
input pin is described in Pin Definitions.
RST can be used to initialize display operation upon power up
or during normal operation. When activated, RST will clear the
Flash RAM and Control Word Register (00H) and reset the
internal counter. All eight display memory locations will be set
to 20H to show blanks in all digits.
FL pin enables access to the Flash RAM. The Flash RAM will
set (D0=1) or reset (D0=0) flashing of the character addressed
by A0–A2.
Five Basic Memory Areas
Character RAM
Stores either ASCII (Katakana)
character data or an UDC RAM
address
The 1 x 8 bit Control Word Register is loaded with attribute
data if A3=0.
The Control Word Logic decodes attribute data for proper
Flash RAM
1 x 8 RAM which stores Flash data
implementation.
User-Defined
Character RAM
(UDC RAM)
Stores dot pattern for custom
characters
Character ROM is designed for 128 ASCII characters. The
ROM is Mask Programmable for custom fonts.
The Clock Source could either be the internal oscillator
(CLKSEL=1) of the device or an external clock (CLKSEL=0)
could be an input from another IPD213X display for synchroniz-
ing blinking for multiple displays.
User-Defined Address
Register (UDC
Address Register)
Provides address to UDC RAM
when user is writing or reading
custom character
The Display Multiplexer controls the Row Drivers so no addi-
tional logic is required for a display system.
Control Word
Register
Enables adjustment of display
brightness, flash individual charac-
ters, blink, self test or clearing
the display
The Display has eight digits. Each digit has 35 LEDs.
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2131/2/3
7
March 28, 2000-00
Table 1. Memory Selection
FL
0
A4
X
A3
X
Section of Memory
Flash RAM
A2–A0
Data Bits Used
D0
Character Address
Don’t Care
1
0
0
UDC Address Register
UDC RAM
D3–D0
1
0
1
Row Address
Character Address
Don’t Care
D4–D0
1
1
1
Character RAM
D7–D0
1
1
0
Control Word Register
D7–D0
Theory of Operation
Microprocessor Interface
The IPD213X Display is designed to work with all major micro-
processors. Data entry is via an eight bit parallel bus. Three bits
of address route the data to the proper digit location in the
RAM. Standard control signals like WR and CE allow the data
to be written into the display.
The interface to a microprocessor is through the 8-bit data
bus (D0–D7), the 4-bit address bus (A0–A3) and control lines
FL, CE and WR.
To write data (ASCII/Control Word) into the display CE should
be held low, address and data signals stable and WR should
be brought low. The data is written on the low to high transi-
tion of WR.
D0–D7 data bits are used for both Character RAM and control
word data input. A3 acts as the mode selector.
If A3=1, character RAM is selected. Then input data bit D7 will
determine whether input data bits D0–D6 is ASCII coded data
(D7=0) or UDC data (D7=1). See section on UDC Address Reg-
ister and RAM.
The Control Word is decoded by the Control Word Decode
Logic. Each code has a different function. The code for display
brightness changes the duty cycle for the column drivers. The
peak LED current stays the same but the average LED current
diminishes depending on the intensity level.
For normal operation FL pin should be held high. When FL is
held low, Flash RAM is accessed to set character blinking.
The character Flash Enable causes 2.0 Hz coming out of the
counter to be ANDED with the column drive signal to make the
column driver cycle at 2.0 Hz. Thus the character flashes at
2.0 Hz.
The seven bit ASCII code is decoded by the Character ROM to
generate Column data. Twenty columns worth of data is sent
out each display cycle, and it takes fourteen display cycles to
write into eight digits.
The display Blink works the same way as the Flash Enable but
causes all twenty column drivers to cycle at 2.0 Hz thereby
making all eight digits blink at 2.0 Hz.
The rows are multiplexed in two sets of seven rows each.
The internal timing and control logic synchronizes the turning
on of rows and presentation of column data to assure proper
display operation.
The Self Test function of the IC consists of two internal rou-
tines which exercise major portions of the IC and illuminates
all the LEDs.
Power Up Sequence
Clear bit clears the character RAM and writes a blank into the
display memory. It however does not clear the control word.
Upon power up the display will come on at random. Thus the
display should be reset on power-up. Reset will clear the
Flash RAM, Control Word Register and reset the internal
counter. All the digits will show blanks and display brightness
level will be 100%.
ASCII Data or Control Word Data can be written into the dis-
play at this point. For multiple display operation, CLK I/O
must be properly selected. CLK I/O will output the internal
clock if CLKSEL=1, or will allow input from an external clock
if CLKSEL=0.
The display must not be accessed until three clock pulses (110
µseconds minimum using the internal clock) after the rising
edge of the reset line.
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2131/2/3
8
March 28, 2000-00
Character RAM
UDC Address Register
The Character RAM is selected when FL, A4 and A3 are set to
1,1,1 during a read or write cycle. The Character RAM is a 8 by
8 bit RAM with each of the eight locations corresponding to a
digit on the display. Digit 0 is on the left side of the display and
digit 7 is on the right side of the display. Address lines, A2–A0
select the digit address with A2 being the most significant bit
and A0 being the least significant bit. The two types of data
stored in the Character RAM are the ASCII coded data and the
UDC Address Data. The type of data stored in the Character
RAM is determined by data bit, D7. If D7 is low, then ASCII
coded data is stored in data bits D6–D0. If D7 is high, then UDC
Address Data is stored in data bit D3–D0.
The UDC Address Register is selected by setting FL=1, A4=0,
A3=0. It is a 4 bit register and uses data bits, D3–D0 to store
the 4 bit address code (D7–D4 are ignored). The address code
selects one of 16 UDC RAM locations for custom character
generation.
UDC RAM
The UDC RAM is selected by setting FL=1, A4=0, A3=1. The
RAM is comprised of a 7 x 5 bit RAM. As shown in Figure 10,
address lines, A2-A0 select one of the 7 rows of the custom
character. Data bits, D4-D0 determine the 5 bits of column data
in each row. Each data bit corresponds to a LED. If the data bit
is high, then the LED is on. If the data bit is low, the LED is off.
To create a character, each of the 7 rows of column data need
to be defined. See Figures 9 and 10 for logic.
The ASCII coded data is a 7 bit code used to select one of 128
ASCII characters permanently stored in the ASCII ROM.
The UDC Address data is a 4 bit code used to select one of the
UDC characters in the UDC RAM. There are up to 16 charac-
ters available. See Figure 8.
Flash RAM
The Flash RAM allows the display to flash one or more of the
characters being displayed. The Flash Ram is accessed by set-
ting FL low. A4 and A3 are ignored. The Flash RAM is a 8 x 1 bit
RAM with each bit corresponding to a digit address. Digit 0 is
on the left side of the display and digit 7 is on the right side of
the display. Address lines, A2–A0 select the digit address with
A2 being the most significant digit and A0 being the least sig-
nificant digit. Data bit, D0, sets and resets the flash bit for each
digit. When D0 is high, the flash bit is set; and when D0 is low,
it is reset. See Figure 11.
UDC Address Register and UDC RAM
The UDC Address Register and UDC RAM allows the user to
generate and store up to 16 custom characters. Each custom
character is defined in 5 x 7 dot matrix pattern. It takes 8 write
cycles to define a custom character, one cycle to load the UDC
Address Register and 7 cycles to define the character. The con-
tents of the UDC Address Register will store the 4 bit address
for one of the 16 UDC RAM locations. The UDC RAM is used
to store the custom character.
Figure 8. Character RAM Access Logic
RST
CE
WR
RD
FL
A4
A3
A2
A1
A0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
1
1
Character Address for
Digits 0–7
0
7 bit ASCII code for a Write Cycle
1
1
1
0
0
0
1
0
1
0
1
0
1
1
1
1
0
0
1
0
0
Character Address for
Digits 0–7
0
7 bit ASCII code read during a Read Cycle
Character Address for
Digits 0–7
1
1
D3–D0=UDC address for a Write Cycle
D3–D0=UDC address for Read Data
Character Address for
Digits 0–7
Figure 9. UDC Address Register and UDC Character RAM
RST
CE
WR
RD
FL
A4
A3
A2
A1
A0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
0
0
Not used for UDC
Address Register
D3–D0=UDC RAM Address Code for
Write Cycle
UDC
Address
Register
1
1
1
0
0
0
1
0
1
0
1
0
1
1
1
0
0
0
0
1
1
Not used for UDC
Address Register
D3–D0=UDC RAM Address Code for
Read Cycle
A2–A0=Character
Row Address
D4–D0=Character Column Data for
Write Cycle
UDC
RAM
A2–A0=Character
Row Address
D4–D0=Character Column Data read
during a Read Cycle
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2131/2/3
9
March 28, 2000-00
Control Word
Flash Function
The Control Word is used to set up the attributes required by
the user. It is addressed by setting FL=1, A4=1, A3=0. The
Control Word is an 8 bit register and is accessed using data
bits, D7–D0. See Figures 12 and 13 for the logic and attrib-
uted control. The Control Word has 5 functions. They are
brightness control, flashing character enable, blinking charac-
ter enable, self test, and clear (Flash and Character RAMS
only).
Control Word bit, D3, enables or disables the Flash Function.
When D3 is 1, the Flash Function is enabled and any digit with
its corresponding bit set in the Flash RAM will flash at approxi-
mately 2.0 hertz. When using an external clock, the flash rate
can be determined by dividing the clock rate by 28,672. When
D3 is 0, the Flash Function is disabled and the contents of the
Flash RAM is ignored. For synchronized flashing on multiple
displays, see the Reset Section.
Brightness Control
Blink Function
Control Word bits, D2–D0, control the brightness of the display
with a binary code of 000 being 100% brightness and 111
being display blank. See Figure 13 for brightness level versus
Control Word bit, D4, enables or disables the Blink Function.
When D4 is 1, the Blink Function is enabled and all characters
on the display will blink at approximately 2.0 hertz. The Blink
Function will override the Flash Function if both functions are
enabled. When D4 is 0, the Blink Function is disabled. When
using an external clock, the blink rate can be determined by
dividing the clock rate by 28,672. For synchronized blinking on
multiple displays, see the Reset Section.
binary code. The average I can be calculated by multiplying
CC
the 100% brightness level I value by the display’s brightness
CC
level. For example, a display set to 80% brightness with a
100% average I value of 200 mA will have an average I
CC
CC
value of 200 mA x 80%=160 mA.
Self Test
Figure 10. UDC Character Map
Control Word bits, D6 and D5, are used for the Self Test Func-
tion. When D6 is 1, the Self Test is initiated. Results of the Self
Test are stored in bit D5. Control Word bit, D5, is a read only
bit. When D5 is 1, Self Test has passed. When D5 is 0, Self
Test failed is indicated. The Self Test function of the IC consists
of two internal routines which exercise major portions of the IC
and illuminates all of the LEDs. The first routine cycles the
ASCII decoder ROM through all states and performs a check
sum on the out-put. If the check sum is correct, D5 is set to a 1
(Pass).
Row Data
Column Data
C1 C2 C3 C4 C5
D4 D3 D2 D1 D0
A2
0
A1
0
A0 Row #
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
0
5 x 7
Dot Matrix
Pattern
0
1
0
1
1
0
1
0
1
1
Figure 11. Flash RAM Access Logic
RST
CE
WR
RD FL
A4
A3
A2
A1
A0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
0
X
X
Flash RAM Address for Digits 0–7
D0=Flash Data, 0=Flash Off and 1=Flash On
(Write Cycle)
1
0
1
0
0
X
X
Flash RAM Address for Digits 0–7
D0=Flash Data, 0=Flash Off and 1=Flash On
(Read Cycle)
Figure 12. Control Word Access Logic
RST
CE
WR
RD FL
A4
A3
A2
A1
A0
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
1
1
1
0
Not used for Control Word
Control Word data for a Write Cycle,
see Figure 13
1
0
1
0
1
1
0
Not used for Control Word
Control Word data for a Read during a
Read Cycle
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2131/2/3
10
March 28, 2000-00
The second routine provides a visual test of the LEDs. This is
accomplished by writing checkered and inversed checkered
patterns to the display. Each pattern is displayed for approxi-
mately 2.0 seconds. During the self test function the display
must not be accessed. The time needed to execute the self
test function is calculated by multiplying the clock time by
262,144 (typical time≈ 4.6 sec.). At the end of the self test, the
Character RAM is loaded with blanks; the Control Word Regis-
ter is set to zeroes except D5; the Flash RAM is cleared and
the UDC Address Register is set to all 1.0s.
Reset Function
The display should be reset on power up of the display
(RST=LOW). When the display is reset, the Character RAM,
Flash RAM, and Control Word Register are cleared.
The display's internal counters are reset. Reset cycle takes
three clock cycles (110 µseconds minimum using the internal
clock). The display must not be accessed during this time.
To synchronize the flashing and blinking of multiple displays, it
is necessary for the display to use a common clock source and
reset all the displays at the same time to start the internal
counters at the same place.
Clear Function (see Figures 13 and 14)
Control Word bit, D7 clears the character RAM to 20 hex and
the flash RAM to all zeroes. The RAMs are cleared within three
clock cycles (110 µs minimum, using the internal clock) when
D7 is set to 1. During the clear time the display must not be
accessed. When the clear function is finished, bit 7 of the Con-
trol Word RAM will be reset to a “0”.
While RST is low, the display must not be accessed by RD
nor WR.
Figure 13. Control Word Data Definition
Key
D7 D6 D5 D4 D3 D2 D1 D0
C
Clear Function
C
ST ST BL FL Br Br Br
ST Self test
BL Blink function
FL Flash function
Br Brightness control
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100% Brightness
80% Brightness
53% Brightness
40% Brightness
27% Brightness
20% Brightness
13% Brightness
Blank Display
0
1
Flash Function Disabled
Flash Function Enabled
0
1
Blink Function Disabled
Blink Function Enabled (overrides Flash Function)
0
1
X
R
Normal Operation X=bit ignored
Run Self Test, R=Test Result, R=1/pass, 0=fail
0
1
Normal Operation
Clear Flash RAM & Character RAM (Character RAM=20 Hex)
Figure 14. Clear Function
CE
WR FL
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
0
0
0
1
1
0
0
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Clear disabled
Clear user RAM, flash RAM
and display
X=don’t care
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2131/2/3
11
March 28, 2000-00
Figure 15. Display Cycle Using Built-in ROM Example
Display message “Showtime.” Digit 0 is leftmost—closest to pin 1.
Logic levels: 0=Low, 1=High, X=Don’t care.
RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
Display
0
X
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
Reset. No Read/Write
Within 3 Clock Cycles
All Blank
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
0
1
1
1
1
0
1
1
0
0
0
0
1
1
0
1
1
0
1
1
1
53% Brightness Selected
Write “S” to Digit 0
Write “H” to Digit 1
Write “O” to Digit 2
Write “W” to Digit 3
Write “T” to Digit 4
Write “I” to Digit 5
Write “M” to Digit 6
Write “E” to Digit 7
All Blank
S
SH
SHO
SHOW
SHOWT
SHOWTI
SHOWTIM
SHOWTIME
Figure 16. Displaying User Defined Character Example
Load character “A” into UDC-5 and then display it in digit 2.
Logic levels: 0=Low, 1=High, X=Don‘t care
RST CE WR RD FL A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
Display
0
X
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
Reset. No Read/Write
Within 3 Clock Cycles
All Blank
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
0
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
0
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
1
1
1
X
0
1
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
1
0
1
0
0
1
0
0
0
0
1
0
1
1
1
1
1
1
1
Select UDC-5
All Blank
Write into Row 1 of UDC-5 All Blank
Write into Row 2 of UDC-5 All Blank
Write into Row 3 of UDC-5 All Blank
Write into Row 4 of UDC-5 All Blank
Write into Row 5 of UDC-5 All Blank
Write into Row 6 of UDC-5 All Blank
Write into Row 7 of UDC-5 All Blank
Write UDC-5 into Digit 2
(Digit 2) A
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2131/2/3
12
March 28, 2000-00
Electrical and Mechanical Considerations
Voltage Transient Suppression
Optical Considerations
The .200" high character of the IPD213X gives readability up
to eight feet. Proper filter selection enhances readability over
this distance.
For best results power the display and the components that
interface with the display to avoid logic inputs higher than V
.
CC
Additionally, the LEDs may cause transients in the power sup-
ply line while they change display states. The common practice
is to place a parallel combination of a .01 µF and a 22 µF capac-
Using filters emphasizes the contrast ratio between a lit LED
and the character background. This will increase the discrimina-
tion of different characters. The only limitation is cost. Take into
consideration the ambient lighting environment for the best
cost/benefit ratio for filters.
itor between V and GND for all display packages.
CC
ESD Protection
The input protection structure of the IPD2131X provides signifi-
cant protection against ESD damage. It is capable of withstand-
ing discharges greater than 4.0 kV. Take all the standard
precautions normal for CMOS components. These include
properly grounding personnel, tools, tables, and transport carri-
ers that come in contact with unshielded parts. If these condi-
tions are not, or cannot be met, keep the leads of the device
shorted together or the parts in anti-static packaging.
Incandescent (with almost no green) or fluorescent (with
almost no red) lights do not have the flat spectral response of
sunlight. Plastic band-pass filters are an inexpensive and effec-
tive way to strengthen contrast ratios. The high efficiency red
displays should be matched with a long wavelength pass filter
in the 570 nm to 590 nm range. The IPD2133 should be
matched with a yellow-green band-pass filter that peaks at 565
nm. For displays of multiple colors, neutral density grey filters
offer the best compromise.
Soldering Considerations
Additional contrast enhancement is gained by shading the dis-
plays. Plastic band-pass filters with built-in louvers offer the
next step up in contrast improvement. Plastic filters can be
improved further with anti-reflective coatings to reduce glare.
The trade-off is fuzzy characters. Mounting the filters close to
the display reduces this effect. Take care not to overheat the
plastic filter by allowing for proper air flow.
The IPD213X can be hand soldered with SN63 solder using a
grounded iron set to 260°C.
Wave soldering is also possible. Use water soluble organic acid
flux or resin based RMA flux.
A wave temperature of 245°C ±5°C with a dwell between 1.5
seconds to 3.0 seconds can be used. Exposure to the wave
should not exceed temperatures above 260°C for five seconds
at 0.063" below the seating plane. The packages should not be
immersed in the wave.
Optimal filter enhancements are gained by using circular polar-
ized, anti-reflective, band-pass filters. The circular polarizing fur-
ther enhances contrast by reducing the light that travels through
the filter and reflects back off the display to less than 1%.
Post Solder Cleaning Procedures
Several filter manufacturers supply quality filter materials.
Some of them are: Panelgraphic Corporation, W. Caldwell, NJ;
SGL Homalite, Wilmington, DE; 3M Company, Visual Products
Division, St. Paul, MN; Polaroid Corporation, Polarizer Division,
Cambridge, MA; Marks Polarized Corporation, Deer Park, NY,
Hoya Optics, Inc., Fremont, CA.
The least offensive cleaning solution is hot D.I. water (60°C) for
less than 15 minutes. Addition of mild saponifiers is accept-
able. Do not use commercial dishwasher detergents.
For faster cleaning, solvents may be used. Suggested solvents
include Freon TE, Freon TF, Genesolv DE-15, Genesolv DI-15,
and Genesolv DES.
One last note on mounting filters: recessing displays and bezel
assemblies is an inexpensive way to provide a shading effect in
overhead lighting situations. Several bezel manufacturers are:
R.M.F. Products, Batavia, IL; Nobex Components, Griffith Plas-
tic Corp., Burlingame, CA; Photo Chemical Products of Califor-
nia, Santa Monica, CA; I.E.E.-Atlas, Van Nuys, CA.
An alternative to soldering and cleaning the display modules is
to use sockets. Multiple display assemblies are best handled
by longer SIP sockets or DIP sockets when available for uni-
form package alignment. Socket manufacturers are Aries Elec-
tronics, Inc., Frenchtown, NJ; Garry Manufacturing, New
Brunswick, NJ; Robinson-Nugent, New Albany, IN; and Samtec
Electronic Hardward, New Albany, IN.
For further information refer to Appnote 22 at www.infin-
eon.com/opto.
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2131/2/3
13
March 28, 2000-00
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