IRF6601TR1PBF [INFINEON]
Power Field-Effect Transistor, 26A I(D), 20V, 0.0038ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, ISOMETRIC-3;
| 型号： | IRF6601TR1PBF |
| 厂家： | 
Infineon |
| 描述： | Power Field-Effect Transistor, 26A I(D), 20V, 0.0038ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, ISOMETRIC-3 开关 脉冲 晶体管 |
| 文件： | 总13页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 94366F
IRF6601/IRF6601TR1
HEXFET® Power MOSFET
VDSS
20V
RDS(on) max
Qg
30nC
l Application Specific MOSFETs
l Ideal for CPU Core DC-DC Converters
l Low Conduction Losses
l Low Switching Losses
l Low Profile (<0.7 mm)
3.8m @VGS = 10V
Ω
5.0m @VGS = 4.5V
Ω
l Dual Sided Cooling Compatible
l Compatible with exisiting Surface Mount
Techniques
DirectFET ISOMETRIC
MT
Applicable DirectFET Package/Layout Pad (see p.9, 10 for details)
SQ SX ST MQ MX
MT
Description
The IRF6601 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to
achieve the lowest on-state resistance in a package that has the footprint of an SO-8 and only 0.7 mm profile. The DirectFET
package is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase,
infra-red or convection soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods
and processes. The DirectFET package allows dual sided cooling to maximize thermal transfer in power systems, IM-
PROVING previous best thermal resistance by 80%.
The IRF6601 balances both low resistance and low charge along with ultra low package inductance to reduce both conduction
and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power the
latest generation of processors operating at higher frequencies. The IRF6601 has been optimized for parameters that are
critical in synchronous buck converters including Rds(on), gate charge and Cdv/dt-induced turn on immunity. The IRF6601
offers particularly low Rds(on) and high Cdv/dt immunity for synchronous FET applications.
Absolute Maximum Ratings
Parameter
Drain-to-Source Voltage
Max.
20
Units
V
VDS
V
Gate-to-Source Voltage
±20
85
GS
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
I
I
I
I
@ TC = 25°C
D
D
D
@ TA = 25°C
@ TA = 70°C
26
A
20
200
3.6
2.3
42
DM
Power Dissipation
P
P
P
@TA = 25°C
@TA = 70°C
@TC = 25°C
D
D
D
Power Dissipation
W
Power Dissipation
Linear Derating Factor
Operating Junction and
0.029
-40 to + 150
W/°C
°C
T
J
T
Storage Temperature Range
STG
Thermal Resistance
Parameter
Junction-to-Ambient
Junction-to-Ambient
Typ.
–––
12.5
20
Max.
35
Units
RθJA
RθJA
–––
–––
3.0
Junction-to-Ambient
Junction-to-Case
RθJA
°C/W
RθJC
–––
1.0
RθJ-PCB
Junction-to-PCB Mounted
–––
Notes through are on page 11
www.irf.com
1
03/09/05
IRF6601/IRF6601TR1
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250µA
BVDSS
∆Β
20
–––
–––
V
∆
V
DSS/ TJ
Breakdown Voltage Temp. Coefficient –––
19
––– mV/°C Reference to 25°C, ID = 1mA
mΩ
RDS(on)
Static Drain-to-Source On-Resistance
–––
–––
1.0
3.2
4.4
1.62
-4.6
–––
–––
–––
–––
–––
–––
30
3.8
5.0
2.2
VGS = 10V, ID = 26A
GS = 4.5V, ID = 21A
VDS = VGS, ID = 250µA
V
VGS(th)
Gate Threshold Voltage
V
∆
V
∆
GS(th)/ TJ
IDSS
IGSS
Gate Threshold Voltage Coefficient
–––
–––
–––
–––
–––
–––
50
––– mV/°C
100
VDS = 20V, VGS = 0V
Drain-to-Source Leakage Current
20
100
100
-100
–––
45
µA VDS = 16V, VGS = 0V
VDS = 16V, VGS = 0V, TJ = 70°C
nA VGS = 20V
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
VGS = -20V
gfs
Qg
S
VDS = 10V, ID = 21A
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Qgs1
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
5.4
2.9
12
–––
–––
–––
–––
–––
–––
3.2
V
DS = 10V
GS = 4.5V
Qgs2
Qgd
nC
V
ID = 16A
Qgodr
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
9.2
15
See Fig. 16
Qsw
Qoss
RG
Output Charge
48
nC
VDS = 16V, VGS = 0V
Ω
Gate Resistance
Turn-On Delay Time
Rise Time
1.9
61
td(on)
tr
td(off)
tf
–––
–––
–––
–––
VDD = 15V, VGS = 4.5V
ID = 21A
21
Turn-Off Delay Time
Fall Time
28
ns Clamped Inductive Load
22
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 3440 –––
––– 2430 –––
VGS = 0V
pF VDS = 15V
ƒ = 1.0MHz
–––
380
–––
Avalanche Characteristics
Parameter
Typ.
–––
–––
–––
Max.
65
Units
mJ
A
Single Pulse Avalanche Energy
EAS
IAR
Avalanche Current
21
Repetitive Avalanche Energy
EAR
0.36
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
MOSFET symbol
IS
D
Continuous Source Current
–––
–––
26
(Body Diode)
Pulsed Source Current
A
showing the
integral reverse
G
ISM
–––
–––
200
S
(Body Diode)
p-n junction diode.
VSD
trr
Diode Forward Voltage
–––
–––
–––
0.83
60
1.2
90
V
T = 25°C, I = 21A, V = 0V
J S GS
Reverse Recovery Time
Reverse Recovery Charge
ns T = 25°C, I = 21A
J F
Qrr
di/dt = 100A/µs
94
140
nC
2
www.irf.com
IRF6601/IRF6601TR1
1000
100
10
1000
VGS
VGS
10V
TOP
TOP
10V
5.0V
4.5V
4.0V
3.5V
3.3V
3.0V
5.0V
4.5V
4.0V
3.5V
3.3V
3.0V
BOTTOM 2.7V
BOTTOM 2.7V
100
2.7V
2.7V
20µs PULSE WIDTH
Tj = 25°C
20µs PULSE WIDTH
Tj = 150°C
10
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.0
1000
26A
=
I
D
1.5
1.0
0.5
0.0
T
= 25°C
J
T
= 150°C
J
100
V
= 15V
DS
20µs PULSE WIDTH
V
= 10V
GS
10
2.5
3.0
3.5
4.0
-60 -40 -20
0
20
40
60
80 100 120 140 160
°
T , Junction Temperature
( C)
J
V
, Gate-to-Source Voltage (V)
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRF6601/IRF6601TR1
6000
12.0
10.0
8.0
V
C
= 0V,
f = 1MHz
C
GS
iss
I = 16A
D
= C
+ C
+ C
SHORTED
ds
gs
gd ,
C
C
= C
gd
rss
oss
5000
4000
3000
2000
1000
0
V
= 16V
= 10V
= C
ds
gd
DS
V
DS
C
iss
6.0
C
oss
4.0
2.0
C
rss
0.0
1
10
100
0
10
20
30
40
V
, Drain-to-Source Voltage (V)
DS
Q
Total Gate Charge (nC)
G
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.0
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100.0
10.0
1.0
T
= 150°C
J
100µsec
T
= 25°C
J
1msec
Tc = 25°C
Tj = 150°C
Single Pulse
10msec
V
= 0V
GS
1
0.1
0
1
10
100
0.0
0.5
1.0
1.5
2.0
V
, Drain-toSource Voltage (V)
V
, Source-toDrain Voltage (V)
DS
SD
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating
Forward Voltage
Area
4
www.irf.com
IRF6601/IRF6601TR1
30
25
20
15
10
5
2.0
1.8
1.6
1.4
I
= 250µA
1.2
1.0
0.8
0.6
0.4
0.2
D
0
25
50
75
100
125
150
-75 -50 -25
0
25
50
75 100 125 150
T
, Temperature ( °C )
J
TA, Ambient Temperature (°C)
Fig 9. Maximum Drain Current Vs.
Fig 10. Threshold Voltage Vs. Temperature
Ambient Temperature
100
D = 0.50
10
0.20
0.10
0.05
1
0.02
0.01
P
DM
SINGLE PULSE
(THERMAL RESPONSE)
t
1
0.1
t
2
Notes:
1. Duty factor D =
t
/ t
1
2
2. Peak T
= P
x
Z
+ T
J
DM
thJA
A
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
100
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF6601/IRF6601TR1
160
120
80
40
0
15V
I
D
TOP
9.4A
17A
21A
DRIVER
+
L
V
BOTTOM
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
GS
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
Starting TJ, Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
I
AS
LD
VDS
Fig 12b. Unclamped Inductive Waveforms
+
-
VDD
D.U.T
Current Regulator
VGS
Same Type as D.U.T.
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
.2µF
12V
Fig 14a. Switching Time Test Circuit
VDS
.3µF
+
V
DS
D.U.T.
-
90%
V
GS
3mA
10%
VGS
I
I
D
G
Current Sampling Resistors
td(on)
td(off)
tr
tf
Fig 14b. Switching Time Waveforms
Fig 13. Gate Charge Test Circuit
6
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IRF6601/IRF6601TR1
Driver Gate Drive
P.W.
Period
D =
D.U.T
Period
P.W.
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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7
IRF6601/IRF6601TR1
Power MOSFET Selection for Non-Isolated DC/DC Converters
Synchronous FET
Control FET
The power loss equation for Q2 is approximated
by;
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
P = P
+ P + P*
loss
conduction
drive
output
P = Irms 2 × Rds(on)
loss ( )
Power losses in the control switch Q1 are given
by;
+ Q × V × f
(
)
g
g
⎛
⎜
Qoss
⎞
⎠
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
+
×V × f + Q × V × f
(
)
in
rr
in
⎝ 2
This can be expanded and approximated by;
*dissipated primarily in Q1.
P
= I 2 × Rds(on )
(
)
loss
rms
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
⎛
⎛
Qgd
ig
⎞
Qgs2
ig
⎞
⎟
⎜
⎟
⎜
+ I ×
× V × f + I ×
× V × f
in
in
⎝
⎠
⎝
⎠
+ Q × V × f
(
)
g
g
⎛ Qoss
⎞
⎠
+
×V × f
in
⎝
2
This simplified loss equation includes the terms Qgs2
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Figure A: Qoss Characteristic
8
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IRF6601/IRF6601TR1
DirectFET Outline Dimension, MT Outline
(Medium Size Can, T-Designation)
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
DIMENSIONS
IMPERIAL
METRIC
MAX
CODE
MIN
MIN
6.25
4.80
3.85
0.35
0.78
0.88
1.78
0.98
0.63
O.88
2.46
0.59
0.03
0.08
MAX
0.250
0.199
0.156
0.018
0.032
0.036
0.072
0.040
0.026
0.039
0.104
0.028
0.003
0.007
6.35
5.05
3.95
0.45
0.82
0.92
1.82
1.02
0.67
1.01
2.63
0.70
0.08
0.17
A
B
C
D
E
F
0.246
0.189
0.152
0.014
0.031
0.035
0.070
0.039
0.025
0.035
0.097
0.023
0.001
0.003
NOTE: CONTROLLING
DIMENSIONS ARE IN MM
G
H
J
K
L
M
N
P
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9
IRF6601/IRF6601TR1
DirectFET Board Footprint, MT Outline
(Medium Size Can, T-Designation)
Please see DirectFET application note AN-1035 for all details regarding the assembly of DirectFET.
This includes all recommendations for stencil and substrate designs.
10
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IRF6601/IRF6601TR1
DirectFET Tape and Reel Dimension
(Showing component orientation).
NOTE: Controlling dimensions in mm
Std reel quantity is 4800 parts. (ordered as IRF6601). For 1000 parts on 7" reel,
order IRF6601TR1
REEL DIMENSIONS
STANDARD OPTION (QTY 4800) TR1 OPTION (QTY 1000)
METRIC IMPERIAL
METRIC
MIN MAX
IMPERIAL
CODE
MIN
MAX
N.C
MIN
MAX
N.C
N.C
0.50
N.C
N.C
0.53
N.C
N.C
MIN
330.0
20.2
12.8
1.5
MAX
N.C
N.C
13.2
N.C
N.C
18.4
14.4
15.4
A
B
C
D
E
F
12.992
0.795
0.504
0.059
3.937
N.C
6.9
177.77
19.06
13.5
N.C
0.75
0.53
0.059
2.31
N.C
N.C
N.C
0.520
N.C
12.8
N.C
1.5
100.0
N.C
58.72
N.C
N.C
N.C
0.724
0.567
0.606
13.50
12.01
12.01
G
H
0.488
0.469
0.47
0.47
12.4
11.9
11.9
11.9
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11
IRF6601/IRF6601TR1
DirectFET Part Marking
Notes:
Surface mounted on 1 in. square Cu board.
ꢀ Used double sided cooling , mounting pad.
Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
TC measured with thermal couple mounted to top (Drain) of
part.
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.24mH,
RG = 25Ω, IAS = 20A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.03/05
12
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
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