IRF6604 [INFINEON]
Power MOSFET; 功率MOSFET型号: | IRF6604 |
厂家: | Infineon |
描述: | Power MOSFET |
文件: | 总11页 (文件大小:205K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PD - 94365B
IRF6604
HEXFET® Power MOSFET
l Application Specific MOSFETs
l Ideal for CPU Core DC-DC Converters
l Low Conduction Losses
VDSS
30V
RDS(on) max
11.5mΩ@VGS = 7.0V
13mΩ@VGS = 4.5V
Qg
17nC
l Low Switching Losses
l Low Profile (<0.7 mm)
l Dual Sided Cooling Compatible
l Compatible with existing Surface Mount
Techniques
DirectFET ISOMETRIC
Description
The IRF6604 combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging
to achieve the lowest on-state resistance charge product in a package that has the footprint of an SO-8 and only 0.7 mm
profile. The DirectFET package is compatible with existing layout geometries used in power applications, PCB assembly
equipment and vapor phase, infra-red or convection soldering techniques. The DirectFET package allows dual sided cooling
to maximize thermal transfer in power systems, IMPROVING previous best thermal resistance by 80%.
The IRF6604 balances both low resistance and low charge along with ultra low package inductance to reduce both conduc-
tion and switching losses. The reduced total losses make this product ideal for high efficiency DC-DC converters that power
the latest generation of processors operating at higher frequencies. The IRF6604 has been optimized for parameters that
are critical in synchronous buck converters including Rds(on) and gate charge to minimize losses in the control FET socket.
Absolute Maximum Ratings
Parameter
Max.
30
Units
V
VDS
Drain-to-Source Voltage
V
Gate-to-Source Voltage
±12
49
GS
Continuous Drain Current, VGS @ 7.0V
Continuous Drain Current, VGS @ 7.0V
Continuous Drain Current, VGS @ 7.0V
Pulsed Drain Current
I
I
I
I
@ TC = 25°C
D
D
D
@ TA = 25°C
@ TA = 70°C
12
A
9.2
92
DM
Power Dissipation
P
P
P
@TA = 25°C
@TA = 70°C
@TC = 25°C
2.3
1.5
42
D
D
D
Power Dissipation
W
Power Dissipation
Linear Derating Factor
Operating Junction and
0.018
-40 to + 150
W/°C
°C
T
J
T
Storage Temperature Range
STG
Thermal Resistance
Parameter
Junction-to-Ambient
Junction-to-Ambient
Typ.
–––
12.5
20
Max.
55
Units
RθJA
RθJA
–––
–––
3.0
Junction-to-Ambient
Junction-to-Case
RθJA
°C/W
RθJC
–––
1.0
RθJ-PCB
Junction-to-PCB Mounted
–––
Notes through are on page 11
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1
6/11/03
IRF6604
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
BVDSS
∆Β
Drain-to-Source Breakdown Voltage
30
–––
27
–––
V
VGS = 0V, ID = 250µA
∆
V
DSS/ TJ
Breakdown Voltage Temp. Coefficient –––
Static Drain-to-Source On-Resistance –––
–––
––– mV/°C Reference to 25°C, ID = 1mA
mΩ
RDS(on)
9.0
10
11.5
13
VGS = 7.0V, ID = 12A
VGS = 4.5V, ID = 9.6A
VDS = VGS, ID = 250µA
VGS(th)
Gate Threshold Voltage
1.0
–––
–––
–––
–––
–––
38
–––
-4.5
–––
–––
–––
–––
–––
17
3.0
V
∆
∆
VGS(th)/ TJ
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
––– mV/°C
IDSS
30
100
100
-100
–––
26
µA
nA
S
VDS = 24V, VGS = 0V
VDS = 24V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
V
GS = 12V
GS = -12V
V
gfs
Qg
VDS = 15V, ID = 9.6A
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Qgs1
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
4.1
1.0
6.3
5.6
7.3
9.5
11
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
VDS = 15V
Qgs2
Qgd
nC VGS = 4.5V
ID = 9.6A
Qgodr
Gate Charge Overdrive
See Fig. 16
Qsw
Switch Charge (Qgs2 + Qgd)
Qoss
td(on)
tr
Output Charge
nC
VDS = 16V, VGS = 0V
Turn-On Delay Time
Rise Time
VDD = 15V, VGS = 4.5V
ID = 9.6A
4.3
18
td(off)
tf
Turn-Off Delay Time
Fall Time
ns Clamped Inductive Load
25
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 2270 –––
V
GS = 0V
–––
–––
420
190
–––
–––
pF
VDS = 15V
ƒ = 1.0MHz
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Typ.
–––
–––
–––
Max.
Units
mJ
A
EAS
IAR
32
9.6
Avalanche Current
Repetitive Avalanche Energy
EAR
0.23
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
IS
D
Continuous Source Current
–––
–––
12
MOSFET symbol
(Body Diode)
Pulsed Source Current
A
showing the
integral reverse
G
ISM
–––
–––
92
S
(Body Diode)
p-n junction diode.
VSD
trr
Diode Forward Voltage
–––
–––
–––
0.94
31
1.2
47
39
V
T = 25°C, I = 9.6A, V = 0V
J S GS
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
ns T = 25°C, I = 9.6A
J F
Qrr
ton
di/dt = 100A/µs
26
nC
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRF6604
1000
100
10
1000
100
10
VGS
10V
VGS
10V
TOP
TOP
7.0V
4.5V
4.0V
3.5V
3.3V
3.0V
7.0V
4.5V
4.0V
3.5V
3.3V
3.0V
BOTTOM 2.7V
BOTTOM 2.7V
2.7V
2.7V
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.0
100.00
12A
=
I
D
T
= 150°C
J
1.5
1.0
0.5
0.0
T
= 25°C
J
10.00
V
= 15V
DS
20µs PULSE WIDTH
V
= 7.0V
1.00
GS
2.5
3.0
3.5
4.0
-60 -40 -20
0
20
40
60
80 100 120 140 160
°
T , Junction Temperature
( C)
V
, Gate-to-Source Voltage (V)
J
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRF6604
10000
6.0
5.0
4.0
3.0
2.0
1.0
0.0
V
= 0V,
f = 1 MHZ
GS
I
= 9.6A
D
C
= C + C
,
C
ds
SHORTED
iss
gs
gd
V
V
= 24V
= 15V
C
= C
DS
DS
rss
gd
C
= C + C
oss
ds
gd
Ciss
1000
Coss
Crss
100
1
10
100
0
5
10
15
20
25
V
, Drain-to-Source Voltage (V)
DS
Q
Total Gate Charge (nC)
G
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
100
10
1
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
°
T = 150
C
J
°
T = 25
C
J
100µsec
1msec
1
10msec
Tc = 25°C
Tj = 150°C
Single Pulse
V
= 0 V
GS
0.1
0.1
0.0
0.5
1.0
1.5
2.0
0
1
10
100
1000
V
,Source-to-Drain Voltage (V)
SD
V
, Drain-toSource Voltage (V)
DS
Fig 7. Typical Source-Drain Diode
Fig 8. Maximum Safe Operating Area
Forward Voltage
4
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IRF6604
12
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
9
I
= 250µA
D
6
3
0
25
50
75
100
125
150
-75 -50 -25
0
25
50
75 100 125 150
TA, Ambient Temperature
(°C)
T
, Temperature ( °C )
J
Fig 9. Maximum Drain Current Vs.
Fig 10. Threshold Voltage Vs. Temperature
Ambient Temperature
100
10
1
D = 0.50
0.20
0.10
0.05
P
DM
0.02
0.01
t
1
t
2
SINGLE PULSE
Notes:
(THERMAL RESPONSE)
1. Duty factor D =
2. Peak T = P
t
/ t
1
2
x
Z
+ T
10
J
DM
thJA
A
0.1
0.00001
0.0001
0.001
0.01
0.1
1
100
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
IRF6604
80
60
40
20
0
I
15V
D
TOP
4.3A
7.7A
9.6A
BOTTOM
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
GS
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
°
( C)
Starting Tj, Junction Temperature
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
LD
I
AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
-
VDD
D.U.T
Current Regulator
VGS
Same Type as D.U.T.
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
.2µF
12V
Fig 14a. Switching Time Test Circuit
VDS
.3µF
+
V
DS
D.U.T.
-
90%
V
GS
3mA
10%
VGS
I
I
D
G
Current Sampling Resistors
td(on)
td(off)
tr
tf
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
6
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IRF6604
Driver Gate Drive
P.W.
P.W.
D =
D.U.T
Period
Period
+
-
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
-
+
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
RG
+
-
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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7
IRF6604
Power MOSFET Selection for Non-Isolated DC/DC Converters
Synchronous FET
Control FET
The power loss equation for Q2 is approximated
by;
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
P = P
+ P + P*
drive output
loss
conduction
P = Irms 2 × Rds(on)
loss ( )
Power losses in the control switch Q1 are given
by;
+ Q × V × f
(
)
g
g
Qoss
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
+
×V × f + Q × V × f
in rr in
(
)
2
This can be expanded and approximated by;
*dissipated primarily in Q1.
P
= I 2 × Rds(on )
(
)
loss
rms
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
Qgd
ig
Qgs2
ig
+ I ×
× V × f + I ×
× V × f
in
in
+ Q × V × f
(
Qoss
)
g
g
+
×V × f
in
2
This simplified loss equation includes the terms Qgs2
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Figure A: Qoss Characteristic
8
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IRF6604
DirectFET Outline Dimension, MQ Outline
(Medium Size Can, Q-Designation).
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9
IRF6604
DirectFET Board Footprint, MQ Outline
(Medium Size Can, Q-Designation).
DirectFET Tape & Reel Dimension
(Showing component orientation).
10
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IRF6604
DirectFET Part Marking
6604
Notes:
Surface mounted on 1 in. square Cu board.
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.70mH
RG = 25Ω, IAS = 9.6A.
ꢀ Used double sided cooling , mounting pad.
Mounted on minimum footprint full size board with metalized
back and with small clip heatsink.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
TC measured with thermal couple mounted to top (Drain) of
part.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.6/03
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11
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