IRFI4019HG-117P [INFINEON]
Integrated Half-Bridge Package; 集成半桥套餐
| 型号： | IRFI4019HG-117P |
| 厂家： | 
Infineon |
| 描述： | Integrated Half-Bridge Package |
| 文件： | 总7页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 96274
IRFI4019HG-117P
DIGITAL AUDIO MOSFET
Features
Key Parameters
Integrated Half-Bridge Package
Reduces the Part Count by Half
Facilitates Better PCB Layout
Key Parameters Optimized for Class-D
Audio Amplifier Applications
Low RDS(ON) for Improved Efficiency
Low Qg and Qsw for Better THD and
Improved Efficiency
VDS
150
V
m
RDS(ON) typ. @ 10V
Qg typ.
80
13
nC
nC
Ω
Qsw typ.
4.1
2.5
150
RG(int) typ.
TJ max
°C
Low Qrr for Better THD and Lower EMI
Can Delivery up to 200W per Channel into
8Ω Load in Half-Bridge Configuration
Amplifier
D1
G1
S1/D2
G2
Lead-Free Package
S2
TO-220 Full-Pak 5 PIN
Halogen-Free
G1, G2
Gate
D1, D2
Drain
S1, S2
Source
Description
This Digital Audio MosFET Half-Bridge is specifically designed for Class D audio amplifier applications. It
consists of two power MosFET switches connected in half-bridge configuration. The latest process is used
toachievelowon-resistancepersiliconarea.Furthermore,Gatecharge,body-diodereverserecovery,and
internal Gate resistance are optimized to improve key Class D audio amplifier performance factors such
as efficiency, THD and EMI. These combine to make this Half-Bridge a highly efficient, robust and reliable
device for Class D audio amplifier applications.
Absolute Maximum Ratings
Parameter
Drain-to-Source Voltage
Max.
150
±20
8.7
Units
V
VDS
VGS
Gate-to-Source Voltage
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
A
6.2
34
EAS
Single Pulse Avalanche Energy
Power Dissipation
77
18
mJ
W
PD @TC = 25°C
PD @TC = 100°C
Power Dissipation
7.2
Linear Derating Factor
Operating Junction and
0.15
W/°C
°C
TJ
-55 to + 150
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lb in (1.1N m)
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Parameter
Typ.
Max.
6.9
Units
Junction-to-Case
Junction-to-Ambient
Rθ
Rθ
–––
–––
JC
65
JA
Notes through are on page 2
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1
10/08/09
IRFI4019HG-117P
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
BVDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
150
–––
–––
3.0
–––
0.19
80
–––
V
∆ΒVDSS/∆TJ
RDS(on)
m
Ω
95
VGS = 10V, ID = 5.2A
VDS = VGS, ID = 50µA
VGS(th)
–––
-11
–––
–––
–––
–––
–––
13
4.9
V
∆VGS(th)/∆TJ
IDSS
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
11
––– mV/°C
20
250
100
-100
–––
20
µA VDS = 150V, VGS = 0V
VDS = 150V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
nA VGS = 20V
VGS = -20V
gfs
S
VDS = 50V, ID = 5.2A
Qg
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Qgs1
Qgs2
Qgd
Qgodr
Qsw
RG(int)
td(on)
tr
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
3.3
0.8
3.9
5.0
4.1
2.5
7.0
6.6
13
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
VDS = 75V
GS = 10V
nC
V
ID = 5.2A
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
Internal Gate Resistance
Turn-On Delay Time
See Fig. 6 and 19
Ω
V
DD = 75V, VGS = 10V
ID = 5.2A
ns R = 2.4
Rise Time
td(off)
tf
Turn-Off Delay Time
Ω
G
Fall Time
3.1
810
100
15
Ciss
Coss
Crss
Coss
LD
Input Capacitance
VGS = 0V
DS = 25V
ƒ = 1.0MHz,
Output Capacitance
pF
V
Reverse Transfer Capacitance
Effective Output Capacitance
Internal Drain Inductance
See Fig.5
97
VGS = 0V, VDS = 0V to 120V
Between lead,
4.5
D
S
nH 6mm (0.25in.)
from package
G
LS
Internal Source Inductance
–––
7.5
–––
and center of die contact
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
IS @ TC = 25°C
Continuous Source Current
–––
–––
8.7
MOSFET symbol
(Body Diode)
A
showing the
ISM
Pulsed Source Current
–––
–––
34
integral reverse
(Body Diode)
p-n junction diode.
VSD
trr
Diode Forward Voltage
–––
–––
–––
–––
57
1.3
86
V
TJ = 25°C, IS = 5.2A, VGS = 0V
Reverse Recovery Time
Reverse Recovery Charge
ns TJ = 25°C, IF = 5.2A
di/dt = 100A/µs
nC
Qrr
140
210
Notes:
R is measured at TJ of approximately 90°C.
ꢀ Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive
avalanche information
θ
Repetitive rating; pulse width limited by max. junction temperature.
Starting TJ = 25°C, L = 5.8mH, RG = 25Ω, IAS = 5.2A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Specifications refer to single MosFET.
2
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IRFI4019HG-117P
100
10
100
10
1
VGS
15V
VGS
TOP
TOP
15V
12V
12V
10V
10V
9.0V
8.0V
7.0V
6.0V
5.5V
9.0V
8.0V
7.0V
6.0V
5.5V
BOTTOM
BOTTOM
1
5.5V
5.5V
0.1
0.01
60µs PULSE WIDTH
Tj = 25°C
≤
60µs PULSE WIDTH
Tj = 150°C
≤
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.5
2.0
1.5
1.0
0.5
0.0
100
I
= 5.2A
D
V
= 10V
GS
10
1
T
= 175°C
J
T
= 25°C
J
V
= 50V
DS
≤ 60µs PULSE WIDTH
0.1
4
5
6
7
8
-60 -40 -20
0
20 40 60 80 100 120 140 160
V , Gate-to-Source Voltage (V)
GS
T , Junction Temperature (°C)
J
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
100000
10000
1000
100
20
V
C
= 0V,
f = 1 MHZ
GS
I = 5.2A
D
= C + C , C SHORTED
iss
gs
gd ds
V
= 120V
DS
C
= C
rss
gd
16
12
8
VDS= 75V
VDS= 30V
C
= C + C
oss
ds
gd
Ciss
Coss
Crss
4
10
0
1
0
5
10
15
20
1
10
100
1000
Q
Total Gate Charge (nC)
G
V
, Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance vs.Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage
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3
IRFI4019HG-117P
100
100
10
1
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
1msec
100µsec
10
T
= 150°C
J
DC
10msec
1
T
= 25°C
J
Tc = 25°C
Tj = 150°C
Single Pulse
V
= 0V
GS
0.1
0.1
0.0
0.5
1.0
1.5
1
10
100
1000
V
, Drain-toSource Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
5.0
10
8
6
4
2
0
4.0
3.0
2.0
I
= 50µA
D
-75 -50 -25
0
25
50
75 100 125 150
25
50
T
75
100
125
150
T
, Temperature ( °C )
, Junction Temperature (°C)
J
J
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 10. Threshold Voltage vs. Temperature
10
D = 0.50
0.20
1
0.10
0.05
R1
R1
R2
R2
R3
R3
0.02
τι
Ri (°C/W)
(sec)
0.1
τ
J τJ
τ
τ
0.01
Cτ
1.508254 0.000814
2.154008 0.111589
3.237738 2.2891
τ
1 τ1
τ
2 τ2
3τ3
Ci= τi/Ri
Ci= τi/Ri
0.01
Notes:
SINGLE PULSE
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
t
, Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
4
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IRFI4019HG-117P
350
300
250
200
150
100
50
0.5
0.4
0.3
0.2
0.1
0.0
I
I
= 5.2A
D
D
TOP
0.91A
1.1A
5.2A
BOTTOM
T
T
= 125°C
= 25°C
J
J
0
4
5
6
7
8
9
10
25
50
75
100
125
150
V
, Gate-to-Source Voltage (V)
GS
Starting T , Junction Temperature (°C)
J
Fig 12. On-Resistance Vs. Gate Voltage
Fig 13. Maximum Avalanche Energy Vs. Drain Current
Driver Gate Drive
P.W.
D.U.T
Period
D =
Period
P.W.
+
V***
=10V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
-
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
*
VDD
**
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple ≤ 5%
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
*** VGS = 5V for Logic Level Devices
Fig 14. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
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5
IRFI4019HG-117P
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
GS
Ω
0.01
t
p
I
AS
Fig 15b. Unclamped Inductive Waveforms
Fig 15a. Unclamped Inductive Test Circuit
RD
VDS
VDS
90%
VGS
D.U.T.
RG
+VDD
-
10%
VGS
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
td(off)
tr
tf
Fig 16a. Switching Time Test Circuit
Fig 16b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
0
Vgs(th)
20K
Qgs1
Qgs2
Qgd
Qgodr
Fig 17a. Gate Charge Test Circuit
Fig 17b Gate Charge Waveform
6
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IRFI4019HG-117P
TO-220 Full-Pak 5-Pin Package Outline, Lead-Form Option 117
(Dimensions are shown in millimeters (inches))
TO-220 Full-Pak 5-Pin Part Marking Information
TO-220AB Full-Pak 5-Pin package is not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/2009
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7
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