IRFP17N50LPBF [INFINEON]
SMPS MOSFET HEXFET㈢Power MOSFET; 开关电源MOSFET HEXFET㈢Power MOSFET
| 型号： | IRFP17N50LPBF |
| 厂家： | 
Infineon |
| 描述： | SMPS MOSFET HEXFET㈢Power MOSFET |
| 文件： | 总8页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 95662
IRFP17N50LPbF
SMPS MOSFET
HEXFET® Power MOSFET
Applications
• Zero Voltage Switching SMPS
• Telecom and Server Power Supplies
• Uninterruptible Power Supplies
• Motor Control applications
• Lead-Free
Trr typ.
VDSS RDS(on) typ.
0.28
ID
500V
Ω
170ns 16A
Features and Benefits
• SuperFast body diode eliminates the need for external
diodes in ZVS applications.
• Lower Gate charge results in simpler drive requirements.
• Enhanced dv/dt capabilities offer improved ruggedness.
• Higher Gate voltage threshold offers improved noise
immunity.
TO-247AC
Absolute Maximum Ratings
Parameter
Max.
16
Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V
11
A
IDM
64
Pulsed Drain Current
PD @TC = 25°C
Power Dissipation
220
W
Linear Derating Factor
Gate-to-Source Voltage
1.8
W/°C
V
VGS
± 30
dv/dt
TJ
Peak Diode Recovery dv/dt
Operating Junction and
13
V/ns
-55 to + 150
TSTG
Storage Temperature Range
°C
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
300 (1.6mm from case )
10lb in (1.1N m)
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
I
Continuous Source Current
––– ––– 16
MOSFET symbol
S
(Body Diode)
A
showing the
I
Pulsed Source Current
––– ––– 64
integral reverse
SM
(Body Diode)
p-n junction diode.
V
t
T = 25°C, I = 16A, V = 0V
J S GS
Diode Forward Voltage
––– ––– 1.5
––– 170 250
––– 220 330
V
SD
T = 25°C, I = 16A
Reverse Recovery Time
Reverse Recovery Charge
ns
rr
J
F
TJ = 125°C, di/dt = 100A/µs
Q
T = 25°C, I = 16A, V = 0V
––– 470 710 nC
––– 810 1210
rr
J
S
GS
TJ = 125°C, di/dt = 100A/µs
IRRM
T = 25°C
J
Reverse Recovery Current
Forward Turn-On Time
––– 7.3
11
A
t
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
on
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1
07/30/04
IRFP17N50LPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250µA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
500
–––
–––
3.0
–––
–––
V
∆V(BR)DSS/∆TJ
RDS(on)
0.60
–––
V/°C Reference to 25°C, ID = 1mA
0.28 0.32
VGS = 10V, ID = 9.9A
DS = VGS, ID = 250µA
Ω
V
VGS(th)
–––
–––
–––
–––
5.0
50
V
IDSS
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
µA VDS = 500V, VGS = 0V
2.0
100
mA VDS = 400V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
nA
V
V
GS = 30V
GS = -30V
––– -100
1.4 –––
RG
Ω
f = 1MHz, open drain
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 9.9A
D = 16A
nC VDS = 400V
VGS = 10V, See Fig. 7 & 15
VDD = 250V
ns ID = 16A
gfs
Qg
11
–––
–––
–––
–––
21
–––
130
33
S
–––
–––
–––
–––
–––
–––
–––
I
Qgs
Qgd
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
59
td(on)
–––
–––
–––
–––
tr
51
td(off)
Turn-Off Delay Time
Fall Time
50
RG = 7.5Ω
VGS = 10V, See Fig. 14a & 14b
VGS = 0V
tf
28
Ciss
Input Capacitance
––– 2760 –––
Coss
Output Capacitance
–––
–––
325
37
–––
–––
VDS = 25V
Crss
Reverse Transfer Capacitance
Output Capacitance
ƒ = 1.0MHz, See Fig. 5
Coss
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 400V, ƒ = 1.0MHz
––– 3690 –––
pF
Coss
Output Capacitance
–––
–––
–––
84
–––
–––
–––
Coss eff.
Coss eff. (ER)
Effective Output Capacitance
Effective Output Capacitance
159
120
V
GS = 0V,VDS = 0V to 400V
(Energy Related)
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Typ.
–––
–––
–––
Max.
390
16
Units
mJ
A
Symbol
EAS
IAR
Avalanche Current
Repetitive Avalanche Energy
EAR
22
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
0.56
–––
62
Units
RθJC
Junction-to-Case
RθCS
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
0.50
–––
°C/W
RθJA
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 11)
Starting TJ = 25°C, L = 3.0mH, RG = 25Ω,
IAS = 16A. (See Figure 12).
Pulse width ≤ 300µs; duty cycle ≤ 2%.
ꢀ Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff.(ER) is a fixed capacitance that stores the same energy
as Coss while VDS is rising from 0 to 80% VDSS
.
ISD = 16A, di/dt ≤ 347A/µs, VDD ≤ V(BR)DSS
TJ ≤ 150°C.
,
.
2
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IRFP17N50LPbF
100
10
100
10
1
VGS
15V
12V
VGS
15V
12V
TOP
TOP
10V
10V
8.0V
7.0V
6.0V
5.5V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
BOTTOM 5.0V
5.0V
1
5.0V
0.1
0.01
20µs PULSE WIDTH
Tj = 150°C
20µs PULSE WIDTH
Tj = 25°C
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
16A
=
I
D
°
T = 150 C
J
2.5
2.0
1.5
1.0
0.5
0.0
10
°
T = 25 C
J
1
V
= 50V
DS
20µs PULSE WIDTH
V
=10V
GS
0.1
4.0
5.0
6.0
7.0
8.0 9.0 10.0
-60 -40 -20
0
20 40 60 80 100 120 140 160
°
V
, Gate-to-Source Voltage (V)
T , Junction Temperature ( C)
J
GS
Fig 4. Normalized On-Resistance
Fig 3. Typical Transfer Characteristics
Vs. Temperature
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3
IRFP17N50LPbF
20
15
10
5
100000
V
= 0V,
f = 1 MHZ
SHORTED
gd ds
GS
C
= C + C , C
iss
gs
C
= C
gd
rss
C
= C + C
oss
ds gd
10000
1000
100
Ciss
Coss
Crss
0
10
0
100
V
200
300
400
500
600
1
10
100
1000
V
, Drain-to-Source Voltage (V)
DS
Drain-to-Source Voltage (V)
DS,
Fig 5. Typical Capacitance Vs.
Fig 6. Typ. Output Capacitance
Drain-to-Source Voltage
Stored Energy vs. VDS
20
16
12
8
100
10
1
I =
D
16A
V
V
V
= 400V
= 250V
= 100V
DS
DS
DS
°
T = 150 C
J
°
T = 25 C
J
4
V
= 0 V
GS
0
0.1
0.2
0
30
60
90
120
150
0.6
0.9
1.3
1.6
Q , Total Gate Charge (nC)
V
,Source-to-Drain Voltage (V)
G
SD
Fig 8. Typical Source-Drain Diode
Fig 7. Typical Gate Charge Vs.
Forward Voltage
Gate-to-Source Voltage
4
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IRFP17N50LPbF
RD
20
16
12
8
VDS
VGS
D.U.T.
RG
+VDD
-
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
4
V
DS
90%
0
25
50
75
100
125
150
°
T , Case Temperature ( C)
C
10%
V
GS
t
t
r
t
t
f
Fig 9. Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
P
2
DM
0.01
t
1
t
2
Notes:
1. Duty factor D =t / t
1
2. Peak T =P
x Z
+ T
C
J
DM
thJC
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFP17N50LPbF
800
640
480
320
160
0
1000
I
D
OPERATION IN THIS AREA LIMITED
TOP
7A
10A
BOTTOM 16A
BY R
DS(on)
100
10us
10
1
100us
1ms
10ms
°
T = 25 C
C
J
°
T = 150 C
Single Pulse
0.1
25
50
75
100
125
150
10
100
1000
10000
°
Starting T , Junction Temperature ( C)
J
V
, Drain-to-Source Voltage (V)
DS
Fig 12. Maximum Safe Operating
Fig 13. Maximum Avalanche Energy
Area
vs. Drain Current
15V
V
(BR)DSS
t
p
DRIVER
L
V
DS
D.U.T
AS
R
G
+
-
V
DD
I
A
20V
0.01Ω
t
p
I
AS
Fig 14b. Unclamped Inductive Waveforms
Fig 14a. Unclamped Inductive Test Circuit
Current Regulator
Same Type as D.U.T.
Q
Q
G
50KΩ
.2µF
12V
VGS
.3µF
Q
+
GS
GD
V
DS
D.U.T.
-
V
GS
V
G
3mA
I
I
D
G
Charge
Current Sampling Resistors
Fig 15a. Gate Charge Test Circuit
Fig 15b. Basic Gate Charge Waveform
6
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IRFP17N50LPbF
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
Period
Period
D =
P.W.
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 16. For N-Channel HEXFET® Power MOSFETs
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7
IRFP17N50LPbF
TO-247AC Package Outline Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
EXAMPLE: THIS IS AN IRFPE30
WIT H AS S E MB L Y
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
LOT CODE 5657
IRFPE30
035H
57
ASSEMBLED ON WW 35, 2000
IN THE ASSEMBLY LINE "H"
56
DAT E CODE
YEAR 0 = 2000
WEEK 35
Note: "P" in assembly line
position indicates "Lead-Free"
AS S E MB L Y
LOT CODE
LINE H
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.07/04
8
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