IN74LV14N [INTEGRAL]

HEX SCHMITT-TRIGGER INVERTER; 六角施密特触发器逆变器


型号：	IN74LV14N
厂家：	INTEGRAL CORP.
描述：	HEX SCHMITT-TRIGGER INVERTER 六角施密特触发器逆变器栅极触发器
文件：	总6页 (文件大小：147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IN74LV14

HEX SCHMITT-TRIGGER INVERTER

The 74LV14 is a low-voltage Si-gate CMOS device and is pin

and function compatible with 74HC/HCT14.

The 74LV14 provides six inverting buffers with Schmitt-

trigger action.

• Wide Operating Voltage: 1.0 to 5.5 V

• Optimized for Low Voltage applications: 1.0 to 3.6 V

• Accepts TTL input levels between V_CC=2.7 V and V_CC=3.6 V

• Low input current

ORDERING INFORMATION

IN74LV14N

Plastic

SOIC

Chip

IN74LV14D

IZ74LV14

T_A= -40° ÷ 125° C for all

packages

LOGIC DIAGRAM

PIN ASSIGNMENT

FUNCTION TABLE

Input

Output

Y= A

PIN 7 = GND

=V_CC

IN74LV14

MAXIMUM RATINGS^*

Symbol

Parameter

Value

-0.5 ÷ +7.0

±20

Unit

V_CC

I_IK*¹

I_OK*²

Io*³

DC supply voltage (Referenced to GND)

DC input diode current

DC output diode current

±50

output

source

for

sink

types

current

with

±25

-bus driver outputs

DC GND current

- bus driver outputs

DC V_CCcurrent

I_GND

I_CC

±50

with

- bus driver outputs

P_D

Power dissipation per paskade, plastic DIP+

750

500

SOIC

package+

Tstg

T_L

Storage temperature

-65 ÷ +150

°C

Lead temperature, 1.5 mm from Case for 10

seconds

260

(Plastic DIP ), 0.3 mm (SOIC Package)

^*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

+Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C

SOIC Package: : - 8 mW/°C from 70° to 125°C

*¹: V_I< -0.5V or V_I> V_CC+0.5V

*²: Vo < -0.5V or Vo > V_CC+0.5V

*³: -0.5V < Vo < V_CC+0.5V

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

1.0

Max

5.5

Unit

V_CC

DC Supply Voltage (Referenced to GND)

V_IN, V_OUTDC Input Voltage, Output Voltage (Referenced to

GND)

V_CC

T_A

t_r, t_f

Operating Temperature, All Package Types

Input Rise and Fall Time

-40

+125

°C

500

200

100

1.0 V≤V_CC<2.0 V

2.0 V≤V_CC<2.7 V

2.7 V≤V_CC<3.6 V

3.6 V≤V_CC≤5.5 V

This device contains protection circuitry to guard against damage due to high static

voltages or electric fields. However, precautions must be taken to avoid applications of any voltage

higher than maximum rated voltages to this high-impedance circuit. For proper operation, V_INand

_OUTshould be constrained to the range GND≤(V_INor V_OUT)≤V_CC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or

V_CC). Unused outputs must be left open.

IN74LV14

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Test

V_CC

25°C

-40°C ÷

85°C

-40°C ÷

125°C

Symbol

V_IT+

Parameter

Conditio

Unit

min max min max min max

Positive-Going

Input

1.2 0.45 0.95

2.0 0.85 1.35

2.7 1.05 1.95

3.0 1.25 2.15

3.6 1.55 2.35

4.5 1.75 3.10

5.5 2.15 3.80

0.4

0.8

1.0

1.2

1.5

1.7

2.1

1.0

1.4

2.0

2.2

2.4

3.15

3.85

0.7

0.9

1.4

1.5

1.8

2.0

2.26

0.7

0.9

1.4

1.5

1.8

2.0

2.6

0.4

0.8

1.0

1.2

1.5

1.7

2.1

0.15

0.3

0.4

0.6

0.8

0.9

1.1

0.15

0.3

0.4

0.6

0.8

0.9

1.1

1.0

1.8

2.5

2.8

3.4

4.3

5.3

2.20

1.0

1.4

2.0

2.2

2.4

3.15

3.85

0.7

0.9

1.4

1.5

1.8

2.0

2.26

0.7

0.9

1.4

1.5

1.8

2.0

2.6

V_O≥ V_OH

Threshold

Voltage

V_IT-

Negative-

1.2

0.2

0.65 0.15

V_O≤ V_OL

Going

Input

2.0 0.35 0.85

2.7 0.45 1.35

3.0 0.65 1.45

3.6 0.85 1.75

4.5 0.95 1.95

5.5 1.15 1.15

0.3

0.4

0.6

0.8

0.9

1.1

Threshold

Voltage

V_H

Hysteresis

Voltage

1.2

0.2

0.65 0.15

V_O≥ V_OH

V_O≤ V_OL

2.0 0.25 0.75

2.7 0.35 1.05

3.0 0.45 1.15

3.6 0.45 1.15

4.5 0.45 1.35

5.5 0.65 1.45

0.3

0.4

0.6

0.8

0.9

1.1

1.0

1.8

2.5

2.8

3.4

4.3

5.3

2.40

V_OH

High-Level

V_I= V_IH– 1.2 1.05

2.0 1.85

Output Voltage or V_IL

I_O= -100 2.7 2.55

3.0 2.85

3.6 3.45

4.5 4.35

5.5 5.35

µA

V_OH

High-Level

V_I= V_IH– 3.0 2.48

Output Voltage or V_IL

I_O= -6.0

V_I= V_IH– 4.5 3.70

3.60

3.50

or V_IL

I_O= -12.0

V_OL

Low-Level

V_I= V_IH– 1.2

0.15

0.2

Output Voltage or V_IL

2.0

I_O= 100 2.7

µA

3.0

3.6

4.5

5.5

IN74LV14

DC ELECTRICAL CHARACTERISTICS (continuation)

Test

Guaranteed Limit

-40°C ÷

V_CC

25°C

-40°C ÷

125°C

Symbol

Parameter

Conditio

Unit

85°C

min max min max min max

V_OL

Low-Level

Output Voltage

V_I= V_IH– 3.0

0.33

0.40

0.50

or I_O

6.0 mA

V_I= V_IH– 4.5

or V_IL

0.40

0.55

0.65

I_O= 12.0

I_IL

Low-Level Input V_I=0 V

Leakage

5.5

-0.1

0.1

4.0

0.2

-1.0

1.0

-1.0

1.0

µA

Current

I_IH

High-Level Input V_I= V_СС

Leakage

Current

I_CC

Quiescent

V_I=0 В or 5.5

µA

Supply Current V_СС

(per Package)

Additional

I_O= 0 µA

I_CC1

V_I= V_СС

0.6V

2.7

3.6

0.5

0.85

Quiescent

Supply Current

on input

I_O= 0 µA

.AC ELECTRICAL CHARACTERISTICS (C_L=50 pF, t_LH=t_HL= 2.5 ns, R_L=1 kΩ)

Guaranteed Limit

Test

V_CC

25°C

-40°C ÷

85°C

-40°C ÷

125°C

Symbol

Parameter

Conditio

Unit

min max min max min max

t_PLH, t_PHLPropagation

V_I=0 V or 1.2

2.0

150

170

200

Delay, Input V₁

A to Output Y t_LH= t_HL2.7

(Figure 1 )

=2.5 ns 3.0

С_L= 50 4.5

R_L= 1

kΩ

C_I

Input

5.5

7.0

Capacitance

C_PD

V_I=0 V or 5.5

V_СС

IN74LV14

t_HL

t_LH

V₁

0.9

V_X

0.9

Input А

V_X

0.1

GND

0.1

t_PHL

t_PLH

V_OH

V_OL

Output Y

V_Y

V_X=0.5 V_CC

Figure 1. Switching Waveforms

V_CC

V_I

V_O

Termination resistance R_T

–

DEVICE

UNDER

TEST

should be equal to Z_OUTof pulse

generators

PULSE

GENERATOR

R_T

R_L

C_L

Figure 2. Test Circuit

IN74LV14

CHIP PAD DIAGRAM IZ74LV14

1.33 0.03

Chip marking

IN74LV14

(x=0.130; y=0.130

)

Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer)

Thickness of chip 0.46 ± 0,02 mm

PAD LOCATION

Pad No

Symbol

0.130

0.381

0.616

0.881

1.116

1.115

0.804

0.569

0.378

0.143

0.130

0.463

0.230

0.126

0.631

0.846

1.181

1.194

0.813

GND

V_CC

IN74LV14N [INTEGRAL]

相关型号：

IN74LV164

IN74LV164D

IN74LV164N

IN74LV174

IN74LV174D

IN74LV174N

IN74LV240

IN74LV240DW

IN74LV240N

IN74LV241

IN74LV241DW

IN74LV241N