LTC2974_技术文档

LTC2945

Wide Range

2

I C Power Monitor

FEATURES

DESCRIPTION

The LTC^®2945 is a rail-to-rail system monitor that mea-

sures current, voltage, and power. It features an operating

range of 2.7V to 80V and includes a shunt regulator for

supplies above 80V to allow flexibility in the selection of

input supply. The current measurement range of 0V to

80Visindependentoftheinputsupply. Anonboard0.75%

accurate 12-bit ADC measures load current, input voltage

and an auxiliary external voltage. A 24-bit power value is

generatedbydigitallymultiplyingthemeasured12-bitload

current and input voltage data. Minimum and maximum

values are stored and an overrange alert with program-

mablethresholdsminimizestheneedforsoftwarepolling.

n

Rail-to-Rail Input Range: 0V to 80V

n

Wide Input Supply Range: 2.7V to 80V

n

Shunt Regulator for Supplies >80V

n

Δ∑ ADC with less than 0.7ꢀ5 ꢁotal Unadjusted Error

n

12-Bit Resolution for Current and Voltages

n

Internal Multiplier Calculates 24-Bit Power Value

n

Stores Minimum and Maximum Values

n

Additional ADC Input Monitors an External Voltage

n

Internal Digital Multiplier Calculates Power

Continuous Scan and Snapshot Modes

n

Shutdown Mode with I < 80μA

Split SDA for Opto-Isolation

Available in 12-Lead 3mm × 3mm QFN and MSOP

Q

n

2

n

Data is reported via a standard I C interface. Shutdown

mode reduces power consumption to 20μA.

Packages

2

The LTC2945 I C interface includes separate data input

APPLICATIONS

2

and output pins for use with standard or opto-isolated I C

connections. The LTC2945-1 has an inverted data output

for use with inverting opto-isolator configurations.

n

Telecom Infrastructure

n

Industrial

n

Automotive

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

n

Consumer

TYPICAL APPLICATION

Wide Range Power Monitor with Onboard ADC and I²C

ADC Differential

Nonlinearity (ADIN)

ADC Integral Nonlinearity

(ADIN)

0.02Ω

V

TO

LOAD

IN

4V TO 80V

0.3

0.2

0.3

0.2

+

–

SENSE SENSE

V

0.1

ALERT

SCL

DD

LTC2945

INTV

CC

2

I C

0.0

0.1μF

INTERFACE

ADR1

ADR0

SDAI

2

NINE I C

–0.1

–0.2

–0.3

–0.1

–0.2

–0.3

ADDRESSES

SDAO

ADIN

MEASURED

VOLTAGE

GND

2945 TA01

0

1024

2048

3072

4096

0

1024

2048

3072

4096

CODE

2945 TA01a

2945 TA01b

2945f

1

LTC2945

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

SCL, SDAI Voltages (Note 4)..................... –0.3V to 5.9V

SCL, SDAI Clamp Current ........................................5mA

Operating Temperature Range

V

Voltage.............................................. –0.3V to 100V

DD

+

SENSE Voltage ...........................................–1V to 100V

–

+

SENSE Voltage .....–1V or SENSE – 1V to SENSE + 1V

LTC2945C................................................ 0°C to 70°C

LTC2945I.............................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10sec)

INTV Voltage (Note 3) ........................... –0.3V to 5.9V

CC

ADR1, ADR0, ADIN, ALERT, SDAO, SDAO

Voltage......................................................... –0.3V to 7V

INTV Clamp Current ...........................................35mA

CC

MS Package Only..............................................300°C

PIN CONFIGURATION

LꢁC294ꢀ

TOP VIEW

12 11 10

+

–

1

2

3

4

5

6

V

INTV

ADR1

ADR0

ADIN

GND

12 SENSE

11 SENSE

10 ALERT

DD

CC

INTV

1

2

3

9

8

7

ALERT

SDAO

SDAI

CC

13

5

ADR1

ADR0

9

8

7

SDAO

SDAI

SCL

4

6

MS PACKAGE

12-LEAD PLASTIC MSOP

T

= 125°C, θ = 135°C/W

JMAX

JA

UD PACKAGE

12-LEAD (3mm s 3mm) PLASTIC QFN

= 125°C, θ = 58.7°C/W

T

JMAX

JA

EXPOSED PAD (Pin 13) PCB GND CONNECTION OPTIONAL

LꢁC294ꢀ-1

TOP VIEW

12 11 10

+

–

1

2

3

4

5

6

V

INTV

ADR1

ADR0

ADIN

GND

12 SENSE

11 SENSE

10 ALERT

DD

CC

INTV

1

2

3

9

8

7

ALERT

SDAO

SDAI

CC

13

5

ADR1

ADR0

9

8

7

SDAO

SDAI

SCL

4

6

MS PACKAGE

12-LEAD PLASTIC MSOP

= 125°C, θ = 135°C/W

T

JMAX

JA

UD PACKAGE

12-LEAD (3mm s 3mm) PLASTIC QFN

= 125°C, θ = 58.7°C/W

T

JMAX

JA

EXPOSED PAD (Pin 13) PCB GND CONNECTION OPTIONAL

2945f

2

LTC2945

ORDER INFORMATION

LEAD FREE FINISH

LTC2945CUD#PBF

LTC2945IUD#PBF

LTC2945CUD-1#PBF

LTC2945IUD-1#PBF

LTC2945CMS#PBF

LTC2945IMS#PBF

LTC2945CMS-1#PBF

LTC2945IMS-1#PBF

ꢁAPE AND REEL

PARꢁ MARKING

LFWK

PACKAGE DESCRIPꢁION

ꢁEMPERAꢁURE RANGE

0°C to 70°C

LTC2945CUD#TRPBF

LTC2945IUD#TRPBF

LTC2945CUD-1#TRPBF

LTC2945IUD-1#TRPBF

LTC2945CMS#TRPBF

LTC2945IMS#TRPBF

LTC2945CMS-1#TRPBF

LTC2945IMS-1#TRPBF

12-Lead (3mm × 3mm) Plastic QFN

12-Lead Plastic MSOP

LFWK

–40°C to 85°C

0°C to 70°C

LFYX

–40°C to 85°C

0°C to 70°C

2945

12-Lead Plastic MSOP

–40°C to 85°C

0°C to 70°C

29451

12-Lead Plastic MSOP

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS ^ꢁhel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at ꢁ_A= 2ꢀ°C. V_DDis from 4V to 80V unless otherwise noted. (Note 2)

SYMBOL

PARAMEꢁER

CONDIꢁIONS

MIN

ꢁYP

MAX

UNIꢁS

SUPPLIES

l

V

Supply Voltage Range

DD

4

80

V

DD

INTV Supply Voltage Range

2.7

5.9

INTVCC

CC

l

I

V

Supply Current

V

= 48V, INTV Open

0.8

40

1.2

70

mA

μA

DD

CC

Shutdown

l

INTV Supply Current

INTV = V = 5V

Shutdown, INTV = V = 5V

0.6

20

0.9

80

mA

μA

CC

DD

CC

DD

l

INTV Linear Regulator Output Current

V = 7V

DD

–10

5.5

mA

V

CCSRC

CC

V

INTV Linear Regulator Voltage

7V < V < 80V, I

= 1mA

4.5

5.9

5

CC

DD

LOAD

ΔV

INTV Linear Regulator Load Regulation

7V < V < 80V, I

= 1mA to 10mA

100

6.3

200

6.7

mV

V

CC

DD

V

INTV Shunt Regulator Voltage

V

DD

V

DD

= 48V, I = 1mA

CC

CCZ

CC

ΔV

INTV Shunt Regulator Load Regulation

= 48V, I = 1mA to 35mA

250

2.69

3.5

mV

V

CCZ

CC

V

INTV Supply Undervoltage Lockout

INTV Rising, V = INTV

CC

2.2

2.9

2

2.6

3.2

2.5

1.8

CC(UVL)

DD(UVL)

DDI2C(RST)

CCI2C(RST)

CC

DD

V

Supply Undervoltage Lockout

V

DD

V

DD

Rising, INTV Open

V

DD

CC

2

I C Logic Reset

Falling, INTV Open

V

CC

2

INTV I C Logic Reset

INTV Falling, V = INTV

CC

1.5

V

CC

DD

SENSE INPUꢁS

+

–

l

V

CM

SENSE , SENSE Common Mode Voltage

0

80

V

+

–

l

I

+

48V SENSE Input Current

SENSE , SENSE , V = 48V

100

150

2

μA

SENSE (HI)

DD

Shutdown

–

+

–

l

–

48V SENSE Input Current

SENSE , SENSE , V = 48V

20

1

μA

SENSE (HI)

DD

Shutdown

+

–

l

+

0V SENSE Source Current

SENSE , SENSE = 0V V = 48V

–10

–2

μA

SENSE (LO)

DD

Shutdown

–

+

–

l

–

0V SENSE Source Current

SENSE , SENSE = 0V, V = 48V

–5

1

μA

SENSE (LO)

DD

Shutdown

2945f

3

LTC2945

ELECTRICAL CHARACTERISTICS ^ꢁhel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at ꢁ_A= 2ꢀ°C. V_DDis from 4V to 80V unless otherwise noted. (Note 2)

SYMBOL

ADC

PARAMEꢁER

CONDIꢁIONS

MIN

ꢁYP

MAX

UNIꢁS

l

RES

Resolution (No missing codes)

Full-Scale Voltage

(Note 5)

12

Bits

V

FS

ΔSENSE (Note 7)

102.4

2.048

mV

V

IN

ADIN

LSB

TUE

LSB Step Size

ΔSENSE

IN

ADIN

25

0.5

μV

mV

V

l

Total Unadjusted Error (Note 6)

Offset Error

ΔSENSE

0.75

%

V

IN

ADIN

l

V

OS

ΔSENSE

3.1

1.5

1.1

LSB

V

IN

ADIN

l

INL

Integral Nonlinearity

Transition Noise

ΔSENSE

IN

ADIN

3

2

LSB

V

ΔSENSE

1.2

0.3

10

μV

mV

μV

RMS

σ

T

V

IN

ADIN

l

f

t

Conversion Rate (Continuous Mode)

Conversion Time (Snapshot Mode)

6

7.5

9

Hz

CONV

l

ΔSENSE

IN

60

30

66

33

72

36

ms

CONV

V , ADIN

l

R

ADIN Pin Input Resistance

ADIN Pin Input Current

V

= 48V, ADIN = 3V

3

10

MΩ

μA

ADIN

DD

I

V

1

ADIN

2

I C INꢁERFACE (V = 48V)

DD

l

V

ADR0, ADR1 Input High Threshold

ADR0, ADR1 Input Low Threshold

ADR0, ADR1 Input Current

2.1

0.3

2.4

0.6

2.7

0.9

13

7

V

ADR(H)

ADR(L)

I

ADR0, ADR1 = 0V, 3V

μA

V

ADR(IN)

ADR(IN,Z)

Allowable Leakage When Open

SDAO, SDAO, ALERT Output Low Voltage

SDAI, SDAO, SDAO, SCL Input Current

SDAI, SCL Input Threshold

V

I , I , I = 8mA

SDAO SDAO ALERT

0.15

0

0.4

1

OD(OL)

I

SDAI, SDAO, SDAO, SCL = 5V

μA

V

SDA,SCL(IN)

V

1.5

5.9

1.9

6.4

0

2.2

6.9

1

SDA,SCL(TH)

SDA,SCL(CL)

ALERT(IN)

SDAI, SCL Clamp Voltage

I

, I

= 3mA

V

SDAI SCL

I

ALERT Input Current

ALERT = 5V

μA

2945f

4

LTC2945

ELECTRICAL CHARACTERISTICS ^ꢁhel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at ꢁ_A= 2ꢀ°C. V_DDis from 4V to 80V unless otherwise noted. (Note 2)

SYMBOL

PARAMEꢁER

CONDIꢁIONS

MIN

ꢁYP

MAX

UNIꢁS

2

I C INꢁERFACE ꢁIMING (Note ꢀ)

f

t

Maximum SCL Clock Frequency

Minimum SCL Low Period

Minimum SCL High Period

400

kHz

μs

SCL(MAX)

LOW

0.65

50

1.3

600

1.3

ns

HIGH

Minimum Bus Free Time Between Stop/Start

Condition

0.12

μs

BUF(MIN)

t

Minimum Hold Time After (Repeated) Start

Condition

140

30

600

ns

HD,STA(MIN)

SU,STA(MIN)

Minimum Repeated Start Condition Set-Up

Time

t

Minimum Stop Condition Set-Up Time

Minimum Data Hold Time Input

Minimum Data Hold Time Output

Minimum Data Set-Up Time

30

–100

600

30

600

0

ns

ms

pF

SU,STO(MIN)

HD,DATI(MIN)

HD,DATO(MIN)

SU,DAT(MIN)

SP(MAX)

300

900

100

250

Maximum Suppressed Spike Pulse Width

Stuck Bus Reset Time

50

25

110

33

SCL or SDAI Held Low

RST

C

SCL, SDAI Input Capacitance

5

10

X

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: Internal clamps limit the SCL and SDAI pins to a minimum of 5.9V.

Driving these pins to voltages beyond the clamp may damage the part. The

pins can be safely tied to higher voltages through resistors that limit the

current below 5mA.

Note 2: All currents into pins are positive. All voltages are referenced to

Note ꢀ: Guaranteed by design and not subject to test.

ground, unless otherwise noted.

Note 3: An internal shunt regulator limits the INTV pin to a minimum of

Note 6:

ACTUAL CODE−IDEAL CODE

(

)

×100%

TUE =

4096

CC

5.9V. Driving this pin to voltages beyond 5.9V may damage the part. This

pin can be safely tied to higher voltages through a resistor that limits the

current below 35mA.

where IDEAL CODE is derived from a straight line passing through Code 0

at 0V and Theoretical Code of 4096 at V

.

FS

Note 7: ΔSENSE is defined as V

+ – V

SENSE

–

SENSE

2945f

5

LTC2945

V_DD= 48V, ꢁ_A= 2ꢀ°C, unless noted.

TYPICAL PERFORMANCE CHARACTERISTICS

V_DDSupply Current

V_DDSupply Current in Shutdown

INꢁV_CCSupply Current

800

750

700

650

600

70

60

50

40

30

20

10

600

575

550

525

500

0

20

40

60

80

0

20

40

60

80

2

3

4

5

6

V

SUPPLY VOLTAGE (V)

V

SUPPLY VOLTAGE (V)

V

SUPPLY VOLTAGE (V)

CC

DD

2945 G01

2945 G02

2945 G03

INꢁV_CCSupply Current in

Shutdown

INꢁV_CCLoad Regulation

INꢁV_CCLine Regulation

5.2

5.1

5.0

4.9

4.8

5.5

5.0

4.5

4.0

3.5

3.0

22.5

20.0

17.5

15.0

12.5

10.0

0

2

4

6

8

10

0

20

V

40

60

80

2

3

4

5

6

LOAD CURRENT (mA)

SUPPLY VOLYAGE (V)

V

SUPPLY VOLTAGE (V)

DD

CC

2945 G05

2945 G06

2945 G04

ADC Differential Nonlinearity

(ADIN)

ADC ꢁotal Unadjusted Error

(ADIN)

ADC Integral Nonlinearity (ADIN)

0.3

0.2

0.3

0.2

0.02

0.01

0

0.1

0.0

–0.1

–0.2

–0.3

–0.1

–0.2

–0.3

–0.01

–0.02

0

1024

2048

3072

4096

0

1024

2048

3072

4096

0

1024

2048

3072

4096

CODE

2945 G07

2945 G08

2945 G09

2945f

6

LTC2945

V_DD= 48V, ꢁ_A= 2ꢀ°C, unless noted.

TYPICAL PERFORMANCE CHARACTERISTICS

ADC Integral Nonlinearity

(ΔSENSE)

ADC Differential Nonlinearity

(ΔSENSE)

ADC ꢁotal Unadjusted Error

(ΔSENSE)

0.4

0.2

0.3

0.2

0.50

0.25

0.1

0.0

0.00

–0.1

–0.2

–0.3

–0.2

–0.4

–0.25

–0.50

0

1024

2048

3072

4096

0

1024

2048

3072

4096

0

1024

2048

3072

4096

CODE

2945 G10

2945 G11

2945 G12

SDAO, SDAO, ALERT Loaded

Output Low Voltage

INꢁV_CCShunt Regulator Load

Regulation

SCL, SDAI Loaded Clamp Voltage

0.4

0.3

0.2

0.1

0.0

6.6

6.5

6.4

6.3

6.2

6.1

6.0

6.6

6.4

6.2

6.0

0

2

4

6

8

10

0.01

0.10

1.00

10.00

0

10

20

30

40

I

,

(mA)

I

(mA)

V

CC

SHUNT CURRENT (mA)

SDA ALERT

LOAD

2945 G13

2945 G14

2945 G15

ADRO, ADR1 Voltage with Current

Sink or Source

SENSE⁺Input Current

SENSE^–Input Current

150

110

70

10

8

3.0

2.5

2.0

1.5

1.0

0.5

0.0

6

4

2

30

0

–10

–2

0

20

40

60

80

0

20

40

60

80

–10

–5

0

5

10

V

+ (V)

V

+ (V)

I

(μA)

SENSE

ADR

2945 G16

2945 G17

2945 G18

2945f

7

LTC2945

PIN FUNCTIONS

ADIN: ADC Input. The onboard ADC measures voltages

between 0V and 2.048V. Tie to ground if unused.

2

SCL: I C Bus Clock Input. Data at the SDAI pin is shifted

in or out on rising edges of SCL. This pin is driven by an

open-collectoroutputfromamastercontroller.Anexternal

pull-up resistor or current source is required and can be

placed between SCL and V or INTV . The voltage at

SCL is internally clamped to 6.4V (5.9V minimum)

2

ADR1,ADR0:I CDeviceAddressInputs.Connectingthese

pins to INTV , GND or leaving the pins open configures

CC

DD

CC

oneofninepossibleaddresses.SeeTable1inApplications

Information section for details.

2

SDAI: I C Bus Data Input. Used for shifting in address,

ALERT: Fault Alert Output. Open drain logic output that

is pulled to ground after an ADC conversion resulted in

a fault to alert the host controller. A fault alert is enabled

by setting the corresponding bit in the ALERT register

as shown in Table 4. This device is compatible with the

SMBus alert protocol. See Applications Information. Tie

to ground if unused.

command or data bits. This pin is driven by an open-

collector output from a master controller. An external

pull-up resistor or current source is required and can be

placed between SDAI and V or INTV . The voltage at

SDAI is internally clamped to 6.4V (5.9V minimum)

DD

CC

2

SDAO: I C Bus Data Output. Open-drain output used for

sendingdatabacktothemastercontrolleroracknowledging

a write operation. An external pull-up resistor or current

source is required.

EXPOSED PAD (Pin 13, DD Package Only): Exposed pad

may be left open or connected to device ground. For best

thermal performance, connect to a large PCB area.

2

SDAO: Inverted I C Bus Data Output. Open-drain output

GND: Device Ground.

used for sending data back to the master controller or

acknowledging a write operation. Data is inverted for

convenienceofopto-isolation.Anexternalpull-upresistor

or current source is required.

INꢁV : Internal Low Voltage Supply Input/Output. This

CC

pin is used to power internal circuitry. It can be config-

ured as a direct input for a low voltage supply, as linear

regulator from higher voltage supply connected to V ,

DD

+

SENSE :SupplyVoltageandCurrentSenseInput.Usedas

or as a shunt regulator. Connect this pin directly to a 2.7V

a supply and current sense input for the internal current

sense amplifier. The voltage at this pin is monitored by the

onboard ADC with a full-scale input range of 102.4V. See

Figure 16 for recommended Kelvin connection.

to 5.9V supply if available. When INTV is powered from

CC

an external supply, short the V pin to INTV . If V

DD

CC

DD

is connected to a 4V to 80V supply, INTV becomes the

CC

5V output of an internal series regulator that can supply

–

up to 10mA to external circuitry. For even higher supply

SENSE : Current Sense Input. Connect an external sense

+

–

voltages or if a floating topology is desired, INTV can

resistor between SENSE and SENSE . The differential

CC

+

–

be used as a 6.3V shunt regulator. Connect the supply to

voltage between SENSE and SENSE is monitored by the

onboard ADC with a full-scale sense voltage of 102.4mV.

INTV through a shunt resistor that limits the current to

CC

less than 35mA. An undervoltage lockout circuit disables

the ADC when the voltage at this pin drops below 2.5V.

Connect a bypass capacitor between 0.1μF and 1μF from

this pin to ground.

V :HighVoltageSupplyInput.Thispinpowersaninternal

DD

series regulator with input voltages ranging from 4V to

80V and produces 5V at INTV when the input voltage

CC

is above 7V. Connect a bypass capacitor between 0.1μF

and 1μF from this pin to ground if external load is pres-

ent on the INTV pin. The onboard 12-bit ADC can be

CC

configured to monitor the voltage at V with a full-scale

DD

input range of 102.4V.

2945f

8

LTC2945

BLOCK DIAGRAM

+

–

ADR0

SENSE

ADR1

V

DD

ALERT

DECODER

V

STBY

20X

2

I C

–

SDAO/SDAO

(LTC2945 / LTC2945-1)

5.7V

V

= 2.048V

REF

V

GEN

STBY

INTV

CC

735k

15k

LOGIC

SDAI

V

STBY

12

6.4V

12-BIT ADC

MUX

ADIN

SCL

REGISTERS

15k

6.3V

6.4V

GND

2945 BD

TIMING DIAGRAM

SDA

t

SP

t

SU,STA

SU,DAT

BUF

HD,DATO

HD,DATI

t

HD,STA

t

SU,STO

t

SP

2945 TD

SCL

t

HD,STA

REPEATED START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

START

CONDITION

2945f

9

LTC2945

OPERATION

The LTC2945 accurately monitors current, voltage, and

power of any supply rail from 0V to 80V. An internal linear

regulator allows the LTC2945 to operate directly from a

4V to 80V rail, or from an external supply voltage between

2.7V and 5.9V. Quiescent current is less than 0.9mA in

In snapshot mode, the LTC2945 performs a single mea-

surement of one selected voltage or current. Snapshot

mode is enabled by setting the snapshot mode enable bit

2

in the CONTROL register via the I C interface. A status bit

in the CONTROL register monitors the ADC’s conversion;

when complete, the conversion result is stored in the cor-

responding data registers.

2

normal operation. Enabling shutdown mode via the I C

interface reduces the quiescent current to below 80ꢀA.

TheLTC2945includesashuntregulatorforoperationfrom

supply voltages above 80V.

Onboard logic tracks the minimum and maximum values

for each ADC measurement, calculates power data by

digitally multiplying the stored current and voltage data,

andtriggersauser-configurablealertbypullingtheALERT

pin low when the ADC measured value falls outside the

programmed window thresholds. All logic outputs are

stored in onboard registers. The LTC2945 includes an

Theonboard12-bitanalog-to-digitalconverter(ADC)runs

either continuously or on-demand using snapshot mode.

In the default continuous scan mode, the ADC repeatedly

+

measures the differential voltage between SENSE and

–

+

SENSE (full-scale 102.4mV) the voltage at the SENSE

2

or V pin (full-scale 102.4V), and the voltage at the ADIN

I C interface to access the onboard data registers and to

DD

pin (full-scale 2.048V). The conversion results are stored

program the alert threshold and control registers. Two

three-state pins, ADR1 and ADR0, are decoded to allow

nine device addresses (see Table 1). The SDA pin is split

into SDAI (input) and SDAO (output, LTC2945) or SDAO

(output, LTC2945-1) to facilitate opto-isolation.

in onboard registers.

APPLICATIONS INFORMATION

R

SNS

The LTC2945 offers a compact and complete solution for

high- and low-side power monitoring. With an input com-

mon mode range of 0V to 80V and a wide input supply

operating voltage range from 2.7V to 80V, this device is

idealforalargevarietyofpowermanagementapplications

includingautomotive,industrialandtelecominfrastructure.

The basic application circuit shown in Figure 1 provides

monitoring of high side current with a 0.02Ω resistor

(5.12A full-scale), input voltage (102.4V full-scale) and an

external voltage (2.048V full-scale), all using an internal

12-bit resolution ADC.

0.02Ω

V

IN

3.3V

V

OUT

4V TO 80V

+

–

SENSE

DD

SENSE

R1

2k

R2

2k

R3

2k

V

DD

SCL

SDA

V

SCL

LTC2945

μP

INTV

SDAI

SDAO

CC

C2

0.1μF

ADR1

ALERT

INT

ADR0

V

ADIN

GND

2945 F01

Figure 1. Monitoring High Side Current and Voltages

Using the LꢁC294ꢀ

Data Converter

TheLTC2945featuresanonboard,12-bitΔ∑ADCthatinher-

ently averages input noise over the measurement window.

+

The supply voltage at V or SENSE is directly measured

DD

with 25mV resolution (102.4V full-scale). The voltage at

the uncommitted ADIN pin is measured with 0.5mV resolu-

tion (2.048V full-scale) to allow monitoring of an arbitrary

external voltage. A 12-bit digital word corresponding to

each measured voltage is stored in two adjacent registers

2945f

TheADCcontinuouslymonitorsthreevoltagesinsequence:

+

ΔSENSE first, V or V

second, and V

third. The

DD

SENSE

ADIN

+

–

differential voltage between SENSE and SENSE is moni-

tored with 25ꢀV resolution (102.4mV full-scale) to allow

accuratemeasurementacrossverylowvalueshuntresistors.

10

LTC2945

APPLICATIONS INFORMATION

out of the six total ADC data registers (ΔSENSE MSB/LSB,

secondary supply connected to the V pin as shown in

DD

V MSB/LSB, and ADIN MSB/LSB), with the eight MSBs

Figure 2b. The SENSE pins can be biased independent of

IN

in the first register and the four LSBs in the second (see

Table 2). The lowest 4 bits in the LSB registers are set to 0.

These data registers are updated immediately following the

corresponding ADC conversion, giving an effective refresh

rate of 7.5Hz in continuous scan mode.

the part’s supply voltage. Alternatively, if a low voltage

supply is present it can be connected to the INTV pin

CC

as shown in Figure 2c to minimize on-chip power dissipa-

tion. When INTV is powered from a secondary supply,

CC

connect V to INTV .

DD

CC

The data converter also features a snapshot mode which

makes a measurement of a single selected voltage (either

For supply voltages above 80V, the shunt regulator at

INTV can be used in both high and low side configura-

CC

ΔSENSE, V or V

+, or V ). To make a snapshot

tions to provide power to the LTC2945 through an exter-

DD

SENSE

ADIN

measurement, set CONTROL register bit A7 and write

the two-bit code of the desired ADC channel to A6 and

A5 (Table 3) using a Write Byte command. When the

Write Byte command is completed, the ADC converts the

selected voltage and the Busy Bit (A3 in the CONTROL

register) will be set to indicate that the conversion is in

progress. After completing the conversion, the ADC will

halt and the Busy Bit will reset to indicate that the data is

ready. To make another snapshot measurement, rewrite

the CONTROL register.

nal shunt resistor, R

. Figure 3a shows a high side

SHUNT

power monitor with an input monitoring range beyond

80V in a high side shunt regulator configuration. The

device ground is separated from ground through R

SHUNT

and clamped at 6.3V below the input supply. Note that

2

due to the different ground levels, the I C signals from

the part need to be level shifted for communication with

other ground referenced components. Figure 3b shows a

high side rail-to-rail power monitor which derives power

from a greater than 80V secondary supply. The voltage

at INTV is clamped at 6.3V above ground in a low side

CC

Flexible Power Supply to LꢁC294ꢀ

shuntregulatorconfigurationtopowerthepart.Inlowside

power monitors, the device ground and the current sense

inputs are connected to the negative terminal of the input

supplyasshowninFigure3c. Thelowsideshuntregulator

configuration allows operation with input supplies above

The LTC2945 can be externally configured to flexibly derive

power from a wide range of supplies. The LTC2945 includes

anonboardlinearregulatortopowerthelow-voltageinternal

circuitryconnectedtotheINTV pinfromhighV voltages.

CC

DD

80V by clamping the voltage at INTV . R

should

CC SHUNT

The regulator operates with V voltages from 4V to 80V,

DD

be sized according to the following equation:

and produces a 5V output capable of supplying 10mA at the

V_S(MAX)–5.9V

35mA

V

_S(MIN)–6.7V

INTV pin when V is greater than 7V. The regulator is

CC

DD

≤R_SHUNT

≤

disabled when die temperature rises above 150°C, and the

1mA +I_LOAD(MAX)

(1)

outputisprotectedagainstaccidentalshorts.Bypasscapaci-

tors between 0.1ꢀF and 1ꢀF at both the V and INTV pins

where V

and V

are the operating maximum

DD

CC

S(MAX)

S(MIN)

are recommended for optimal transient performance. Note

and minimum of the supply. I

is the maximum

LOAD(MAX)

that operation with high V voltages can cause significant

externalcurrentloadthatisconnectedtotheshuntregula-

tor.Theshuntresistormustalsoberatedtosafelydissipate

the worst-case power. As an example, consider the –48V

Telecom System where the supply operates from –36V to

–72V and the shunt regulator is used to supply an external

DD

powerdissipation,andcareisrequiredtoensuretheoperating

junctiontemperaturestaysbelow125°C.Forimprovedpower

dissipation,usetheQFNpackageandsoldertheexposedpad

to a large copper region for improved thermal resistance.

load up to 4mA. R

needs to be between 1.9k and

SHUNT

Figure 2a shows the LTC2945 being used to monitor an

input supply that ranges from 4V to 80V. No secondary

5.9k according to the above equation, and for reduced

power dissipation, a larger resistance is advantageous.

supply is needed since V can be connected directly to

DD

The worst-case power dissipated in an R

of 5.4k is

SHUNT

theinputsupply.IftheLTC2945isusedtomonitoraninput

calculated to be 0.8W. So, three 0.5W rated 1.8k resistors

supply of 0V to 80V, it can derive power from a wide range

in series would suffice for this example.

2945f

11

LTC2945

APPLICATIONS INFORMATION

R

SNS

V

>80V

IN

V

OUT

R

SNS

V

IN

V

OUT

+

–

4V TO 80V

SENSE

+

–

SENSE

INTV

CC

V

DD

LTC2945

V

DD

LTC2945

GND

C2

INTV

CC

GND

R

C2

2945 F03a

2945 F02a

SHUNT

Figure 3a. LꢁC294ꢀ Derives Power

ꢁhrough High-Side Shunt Regulator

Figure 2a. LꢁC294ꢀ Derives Power from

the Supply Being Monitored

R

SNS

R

SNS

V

IN

V

OUT

0V TO 80V

+

–

+

–

SENSE

R

SHUNT

>80V

INTV

CC

V

4V TO 80V

DD

V

DD

LTC2945

GND

LTC2945

GND

C2

INTV

CC

C2

2945 F02b

2945 F03b

Figure 2b. LꢁC294ꢀ Derives Power from

a Wide Range Secondary Supply

Figure 3b. LꢁC294ꢀ Derives Power ꢁhrough Low-Side

Shunt Regulator in High-Side Current Sense ꢁopology

GND

R

SHUNT

R

SNS

V

IN

V

OUT

0V TO 80V

INTV

CC

+

–

SENSE

V

DD

2.7V TO 5.9V

INTV

CC

C1

LTC2945

–

V

DD

GND

LTC2945

GND

C2

+

SENSE

2945 F03a

V

NEG

2945 F02c

V

OUT

>–80V

R

SNS

Figure 2c. LꢁC294ꢀ Derives Power from

a Low Voltage Secondary Supply

Figure 3c. LꢁC294ꢀ Derives Power ꢁhrough Low-Side

Shunt Regulator in Low-Side Current Sense ꢁopology

2945f

12

LTC2945

APPLICATIONS INFORMATION

GND

opto-couplers or pull-ups, ensure bit A1 in the CONTROL

register is masked off during software development. In

such applications, the user is advised that accidentally

V

DD

INTV

GND

2

CC

disabling the regulator would prevent I C communication

C2

from the master and cause the LTC2945 to disengage

from the system. The LTC2945 would then have to be

reset by cycling its power to come out of shutdown. It is

recommended that external regulators be used in such

applications if powering down the LTC2945 is desirable.

Quiescent current drops below 80μA in shutdown mode

with the internal regulator disabled.

LTC2945

–

+

SENSE

2945 F03b

V

NEG

V

OUT

–4V TO –80V

R

SNS

Figure 3d. LꢁC294ꢀ Derives Power from the Supply

Being Monitored in Low-Side Current Sense ꢁopology

Power Calculation and Configuration

TheLTC2945calculatespowerbymultiplyingthemeasured

current with the measured voltage. In continuous mode,

If the supply input is nominally below 80V and transient

is limited to below 100V, the shunt resistor is not required

+

–

the differential voltage between SENSE and SENSE is

measured to obtain load current data. The supply volt-

and V can be connected to GND of the supply as shown

DD

in Figure 3d.

age data for multiplication can be selected between V ,

DD

+

SENSE , or ADIN. SENSE is selected by default as it is

normally connected to the supply voltage. In negative

supply voltage systems such as shown in Figure 3d, the

deviceground(GNDpinofLTC2945)andSENSE arecon-

nected to the supply and V measures the supply voltage

Supply Undervoltage Lockout

2

During power-up, the internal I C logic and the ADC are

–

enabled when either V or INTV rises above its under-

DD

CC

voltagelockoutthreshold. Duringpower-down, theADCis

DD

at GND with respect to the device ground. For negative

supply voltages of more than 80V, use external resistors

to divide down the voltage to suit the ADIN measurement

range. In the CONTROL register,

disabled when V and INTV fall below their respective

DD

CC

2

undervoltage lockout thresholds. The internal I C logic is

2

reset when V and INTV fall below their respective I C

DD

CC

reset thresholds.

+

• write bits A2=1, A0=1 to select SENSE (Default)

Shutdown Mode

• write bits A2=0, A0=1 to select V

DD

The LTC2945 includes a low quiescent current shutdown

mode, controlled by bit A1 in the CONTROL register

(Table 3). Setting A1 puts the part in shutdown mode,

poweringdowntheADCandinternalreference.Theinternal

• write bits A2=1, A0=0 to select ADIN

More details on the CONTROL register can be found in

Table 3.

2

I C bus remains active, and although the ADR1 and ADR0

Once the ADC conversions are complete, a 24-bit power

value is generated by digitally multiplying the 12-bit load

current data with the 12-bit supply voltage data. 1LSB of

power is 1LSB of voltage multiplied by 1LSB of ΔSENSE

(current). The result is held in the three adjacent POWER

registers (Table 2). The POWER registers initialize with

undefined data and subsequently refresh at a frequency

of 7.5Hz in continuous scan mode. In snapshot mode, the

POWER registers are not refreshed.

pins are disabled, the device will retain the most recently

2

programmed I C bus address. All on-board registers re-

2

tain their contents and can be accessed through the I C

interface. To re-enable ADC conversions, reset bit A1 in

the CONTROL register. The analog circuitry will power up

and all registers will retain their contents.

Theonboardlinearregulatorisdisabledinshutdownmode

to conserve power. If low I mode is not required and the

Q

2

regulatorisusedtopowerI Cbus-relatedcircuitrysuchas

2945f

13

LTC2945

APPLICATIONS INFORMATION

Storing Minimum and Maximum Values

The LTC2945 is a read-write slave device and supports

the SMBus Read Byte, Write Byte, Read Word and Write

Word protocols. The LTC2945 also supports extended

Read and Write commands that allow reading or writing

more than two bytes of data. When using the Read/Write

Word or extended Read and Write commands, the bus

master issues an initial register address and the internal

register address pointer automatically increments by 1

after each byte of data is read or written. After the register

address reaches 31h, it will roll over to 00h and continue

incrementing.AStopconditionresetstheregisteraddress

pointer to 00h. The data formats for the above commands

are shown in Figures 6 to 11.

The LTC2945 compares each measurement including the

calculated power with the stored values in the respective

MIN and MAX registers for each parameter (Table 2). If

the new conversion is beyond the stored minimum or

maximum values, the MIN or MAX registers are updated

with the new values. The MIN and MAX of the registers are

refreshed at the end of their respective ADC conversions

in both continuous scan mode and snapshot mode. They

are also refreshed if the ADC registers are written via the

2

I C bus with values beyond the stored values. To initiate

a new peak hold cycle, write all 1’s to the MIN registers

2

and all 0’s to the MAX registers via the I C bus. These

registers will be updated when the next respective ADC

conversion is done.

2

I C Device Addressing

2

Nine distinct I C bus addresses are configurable using the

The LTC2945 also includes MIN and MAX THRESHOLD

registers (Table 2) for the measured parameters including

the calculated power. At power-up, the maximum thresh-

olds are set to all 1’s and minimum thresholds are set to

all 0’s, effectively disabling them. The thresholds can be

three-state pins ADR0 and ADR1, as shown in Table 1.

ADR0 and ADR1 should be tied to INTV , to GND, or left

CC

floating (NC) to configure the lower four address bits.

During low power shutdown, the address select state

is latched into memory powered from standby supply.

Address bits a6, a5 and a4 are permanently set to (110)

and the least significant bit is the R/W bit. In addition, all

LTC2945 devices will respond to a common Mass Write

address (1100 110)b; this allows the bus master to write

to several LTC2945s simultaneously, regardless of their

individualaddresssettings.TheLTC2945willalsorespond

to the standard ARA address (0001100)b if the Alert pin

is asserted; see the Alert Response Protocol section for

more details. The LTC2945 will not respond to the ARA

address if no alerts are pending.

2

reprogrammed to any desired value via the I C bus.

Fault Alert and Resetting Faults

As soon as a measured quantity falls below the minimum

thresholdorexceedsthemaximumthreshold,theLTC2945

sets the corresponding flag in the STATUS register and

latchesitintotheFAULTregister(seeFigure4). TheALERT

pinispulledlowiftheappropriatebitintheALERTregister

is set. More details on the alert behavior can be found in

the Alert Response Protocol section.

An active fault indication can be reset by writing zeros

to the corresponding FAULT register bits or by reading

the FAULT CoR register (Table 2), which clears all FAULT

Start and Stop Conditions

2

When the I C bus is idle, both SCL and SDA are in the high

register bits. All FAULT register bits are also cleared if the

state.Abusmastersignalsthebeginningofatransmission

with a Start condition by transitioning SDA from high to

low while SCL stays high. When the master has finished

communicating with the slave, it issues a Stop condition

by transitioning SDA from low to high while SCL stays

high. The bus is then free for another transmission.

2

V

and INTV fall below their respective I C logic reset

DD

CC

threshold. Note that faults that are still present, as indi-

cated in the STATUS registers, will immediately reappear.

2

I C Interface

2

The LTC2945 includes an I C/SMBus-compatible inter-

face to provide access to the onboard registers. Figure 5

2

shows a general data transfer format using the I C bus.

2945f

14

LTC2945

APPLICATIONS INFORMATION

STATUS

LATCH

FAULT

MEASURED

DATA

DIGITAL

COMPARATOR

ENA_ALERT_RESPONSE

LOGIC

ALERT

THRESHOLD

DATA

RESET

2945 F04

Figure 4. LꢁC294ꢀ Fault Alert Generation Blocks

SDA

SCL

a6 - a0

1 - 7

b7 - b0

8

9

1 - 7

8

9

1 - 7

8

9

S

P

START

CONDITION

STOP

CONDITION

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

2945 F05

Figure ꢀ. General Data ꢁransfer over I²C

S

ADDRESS W A

COMMAND

A

DAꢁA

A

P

S

ADDRESS W A

1 1 0 a3:a0

COMMAND

A

DAꢁA

A

DAꢁA

A

P

0

X X b5:b0

0

b7:b0

0

b7:b0

0

1 1 0 a3:a0

0

X X b5:b0

0

b7:b0

0

2945 F06

2945 F07

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

A: ACKNOWLEDGE (LOW)

A: NOT ACKNOWLEDGE (HIGH) S: START CONDITION

R: READ BIT (HIGH) P: STOP CONDITION

W: WRITE BIT (LOW)

Figure 6. LꢁC294ꢀ Serial Bus SDA Write Byte Protocol

Figure 7. LꢁC294ꢀ Serial Bus SDA Write Word Protocol

S

ADDRESS W A

1 1 0 a3:a0

COMMAND

A

DAꢁA

A

DAꢁA

A

...

DAꢁA

A

P

S

ADDRESS W A

1 1 0 a3:a0

COMMAND

A

S

ADDRESS

R

A

DAꢁA

A

P

0

X X b5:b0

0

b7:b0

0

b7:b0

0

...

b7:b0

0

X X b5:b0

0

1 1 0 a3:a0

1

0

b7:b0

1

2945 F08

2945 F09

Figure 8. LꢁC294ꢀ Serial Bus SDA Write Page Protocol

Figure 9. LꢁC294ꢀ Serial Bus SDA Read Byte Protocol

S

ADDRESS W A

1 1 0 a3:a0

COMMAND

A

S

ADDRESS

R

A

DAꢁA

A

DAꢁA

A

P

0

X X b5:b0

0

1 1 0 a3:a0

1

0

b7:b0

0

b7:b0

1

2945 F10

Figure 10. LꢁC294ꢀ Serial Bus SDA Read Word Protocol

S

ADDRESS W A

1 1 0 a3:a0

COMMAND

A

S

ADDRESS

R

A

DAꢁA

A

DAꢁA

...

DAꢁA

A

P

0

X X b5:b0

0

1 1 0 a3:a0

1

0

b7:b0

0

b7:b0

...

b7:b0

1

2945 F11

Figure 11. LꢁC294ꢀ Serial Bus SDA Read Page Protocol

2945f

15

LTC2945

APPLICATIONS INFORMATION

Stuck-Bus Reset

terminates and the register address pointer resets to 00h

when the master sends a Stop condition.

2

The LTC2945 I C interface features a stuck bus reset timer

to prevent it from holding the bus lines low indefinitely if

the SCL signal is interrupted during a transfer. The timer

starts when either SCL or SDAI is low, and resets when

both SCL and SDAI are pulled high. If either SCL or SDAI

are low for over 33ms, the stuck-bus timer will expire and

Read Protocol

The master begins a read operation with a Start condition

followed by the 7-bit slave address and the R/W bit set

to zero. After the addressed LTC2945 acknowledges the

address byte, the master then sends a command byte

that indicates which internal register the master wishes to

read. TheLTC2945acknowledgesthisandthenlatchesthe

lowersixbitsofthecommandbyteintoitsinternalregister

address pointer. The master then sends a repeated Start

conditionfollowedbythesame7-bitaddresswiththeR/W

bit now set to 1. The LTC2945 acknowledges and sends

the contents of the requested register. The transmission

terminates when the master sends a Stop condition. If the

master acknowledges the transmitted data byte, as in a

ReadWordcommand, theLTC2945will sendthecontents

of the next register. If the master keeps acknowledging,

the LTC2945 will keep incrementing the register address

pointer and sending out data bytes. The read operation

terminates and the register address pointer resets to 00h

when the master sends a Stop condition.

2

the internal I C interface and the SDAO pin pulldown logic

will be reset to release the bus. Normal communication

will resume at the next Start command.

Acknowledge

The acknowledge signal is used for handshaking between

the transmitter and the receiver to indicate that the last

byte of data was received. The transmitter always releases

the SDA line during the acknowledge clock pulse. The

LTC2945 will pull the SDA line low on the 9th clock cycle

to acknowledge receipt of the data. If the slave fails to

acknowledge by leaving SDA high, then the master can

abort the transmission by generating a Stop condition.

When the master is receiving data from the slave, the

master must acknowledge the slave by pulling down the

SDA line during the 9th clock pulse to indicate receipt of

a data byte. After the last byte has been received by the

master, it will leave the SDA line high (not acknowledge)

and issue a Stop condition to terminate the transmission.

Alert Response Protocol

When any of the fault bits in the FAULT register are set, a

bus alert is generated if the appropriate bit in the ALERT

register has been set. This allows the bus master to select

which faults will generate alerts. At power-up, the ALERT

register is cleared (no alerts enabled) and the ALERT pin is

high. If an alert is enabled, the corresponding fault causes

the ALERT pin to pull low. The bus master responds to the

alertinaccordancewiththeSMBusalertresponseprotocol

by broadcasting the Alert Response Address (0001100)b,

and the LTC2945 replies with its own address and releases

itsALERTpinasshowninFigure12. TheALERTlineisalso

released if the FAULT or FAULT CoR registers are read (see

Table 2) since the faulting event can be identified by the

content in these registers. The ALERT signal is not pulled

low again until the Fault register indicates a different fault

has occurred or the original fault is cleared and it occurs

again. Note that this means repeated or continuing faults

will not generate additional alerts until the associated

Write Protocol

The master begins a write operation with a Start condition

followed by the seven-bit slave address and the R/W bit

set to zero. After the addressed LTC2945 acknowledges

the address byte, the master then sends a command byte

that indicates which internal register the master wishes to

write.TheLTC2945acknowledgesthisandthenlatchesthe

lowersixbitsofthecommandbyteintoitsinternalregister

addresspointer.Themasterthendeliversthedatabyteand

the LTC2945 acknowledges once more and writes the data

into the internal register pointed to by the register address

pointer. If the master continues sending additional data

bytes with a Write Word or extended Write command, the

additionaldatabyteswillbeacknowledgedbytheLTC2945,

theregisteraddresspointerwillautomaticallyincrementby

one, and data will be written as above. The write operation

FAULT register bits have been cleared.

2945f

16

LTC2945

APPLICATIONS INFORMATION

If two or more LTC2945s on the same bus are generating

alerts when the ARA is broadcasted, the bus master will

repeat the alert response protocol until the ALERT line

is released. The device with the highest priority (lowest

address) will reply first and the device with the lowest

priority (highest address) will reply last.

R

can then be calculated using Equation 1. Note that

SHUNT

both LTC2945 and LTC2945-1 can be used in the shunt

regulator applications mentioned.

Figure 16 shows an alternate connection for use with low-

speed opto-couplers and the LTC2945-1. This circuit uses

a limited-current pullup on the internally clamped SDAI

pin and clamps the SDAO pin with the input diode of the

ALERT

RESPONSE

ADDRESS

DEVICE

S

R

1

P

A

0

A

outgoing opto-isolator, removing the need to use INTV

ADDRESS

CC

for biasing in the absence of an auxiliary low voltage sup-

0 0 0 1 1 0 0

a7:a0

1

2945 F12

ply. For proper clamping:

Figure 12. LꢁC294ꢀ Serial Bus SDA Alert Response Protocol

V_S(MAX)–5.9V

5mA

V_S(MIN)–6.9V

≤R4≤

(3)

0.5mA

2

Opto-Isolating the I C Bus

As an example, a supply that operates from 36V to 72V

would require the value of R4 to be between 13k and 58k.

The LTC2945-1 must be used in this application to ensure

that the SDAO signal polarity is correct.

2

Opto-isolating a standard I C device is complicated

by the bidirectional SDA pin. The LTC2945/LTC2945-1

2

minimize this problem by splitting the standard I C SDA

line into SDAI (input) and SDAO (output, LTC2945) or

SDAO (inverted output, LTC2945-1). The SCL is an input

only pin and does not require special circuitry to isolate.

The LTC2945-1 can also be used with high-speed opto-

couplers with push-pull outputs and inverted logic as

shown in Figure 17. The incoming opto-isolator draws

2

For conventional non-isolated I C applications, use the

power from the INTV , and the data output is connected

CC

LTC2945 and tie the SDAI and SDAO pins together to form

directly to the SDAI pin with no pullup required. Ensure

2

a standard I C SDA pin.

the current drawn does not exceed the 10mA maximum

Low speed isolated interfaces that use standard open-

drain opto-isolators typically use the LTC2945 with the

SDAI and SDAO pins separated as shown in Figure 13.

Connect SDAI to the output of the incoming opto-isolator

capability of the INTV pin. The SDAO pin is connected

CC

to the cathode of the outgoing optocoupler with a current

limiting resistor connected back to INTV . An additional

CC

discrete N-channel MOSFET is required at the output of

with a pullup resistor to INTV or a local 5V supply; con-

the outgoing optocoupler to provide the open-drain pull-

CC

2

nect SDAO to the cathode of the outgoing opto-isolator

with a current-limiting resistor in series with the anode.

The input and output must be connected together on the

isolated side of the bus to allow the LTC2945 to participate

down that the I C bus requires. Finally, the input of the

incoming opto-isolator is connected back to the output

as in the low-speed case.

2

Layout Considerations

in I C arbitration. Note that maximum I C bus speed will

generally be limited by the speed of the opto-couplers

used in this application.

A Kelvin connection between the sense resistor R

and

SNS

the LTC2945 is recommended to achieve accurate current

sensing (Figure 18). The recommended minimum trace

width for 1oz copper foil is 0.02” per amp to ensure the

trace stays at a reasonable temperature. Using 0.03” per

amp or wider is preferred. Note that 1oz copper exhibits

a sheet resistance of about 530ꢀΩ per square.

Both low and high side shunt regulators can supply up to

34mA of current to drive opto-isolator and pullup resis-

tors as shown in Figure 14 and 15. For identical SDAI/SCL

pullup resistors the maximum load is:

6.7V

2 •R1+R3

I_LOAD(MAX)

=

(2)

2945f

17

LTC2945

APPLICATIONS INFORMATION

V

IN

48V

INTV

CC

V

DD

1/2 ACPL-064L*

C

1μF

C2

1μF

3.3V

1

R5

2k

V

CC

LTC2945-1

M1

BS170

GND

R6

2k

R7

2k

SDAO

V

DD

V

CC

μP

ISO_SDA

SDAI

SDA

GND

2945 F13

1/2 ACPL-064L*

* CMOS OUTPUT

Figure 13. Opto-Isolation of a 10kHz I²C Interface Between LꢁC294ꢀ and Microcontroller (SCL Omitted for Clarity)

GND

R

3.3V

SHUNT

SDAI

R3 R1

R2

0.51k

R4

10k

1k

10k

INTV

CC

V

DD

V

DD

LTC2945

V

μP

EE

C1

1/2 MOCD207M

1μF

SDA

GND

SDAO

SENSE

–

+

SENSE

2945 F14

1/2 MOCD207M

V

OUT

EE

R

SNS

0.02Ω

Figure 14. Low Speed 10kHz Opto-Isolators Powered from Low-Side Shunt Regulator

R

SNS

3.3V

0.02Ω

V

OUT

R3

1k

R1

10k

+

–

R2

1k

R4

10k

SENSE

INTV

SENSE

SDAI

CC

V

DD

V

DD

LTC2945-1

μP

C1

1μF

1/2 MOCD207M

SDA

SDAO

GND

2945 F15

R

SHUNT

Figure 1ꢀ. Low Speed 10kHz Opto-Isolators Powered from High-Side Shunt Regulator

2945f

18

LTC2945

APPLICATIONS INFORMATION

3.3V

48V

R4

20k

R5

7.5k

R6

0.51k

R7

10k

SDAI

V

DD

LTC2945-1

μP

1/2 MOCD207M

SDAO

SDA

GND

2945 F16

1/2 MOCD207M

Figure 16. Opto-Isolation of a 1.ꢀkHz I²C Interface Between LꢁC294ꢀ-1 and Microcontroller (SCL Omitted for Clarity)

3.3V

5V

R4

R5

R6

R7

10k

0.82k

0.51k

10k

SDAI

V

DD

LTC2945

GND

μP

1/2 MOCD207M

SDA

GND

SDAO

2945 F17

1/2 MOCD207M

Figure 17. Opto-Isolation of I²C Interface with Low Power, High Speed Opto-couplers (SCL Omitted for Clarity)

R

SNS

TO

LOAD

V

IN

1

2

3

4

5

12

11

10

9

8

6

7

2945 F18

Figure 18. Recommended Layout for Kelvin Connection

2945f

19

LTC2945

APPLICATIONS INFORMATION

ꢁable 1. LꢁC294ꢀ Device Addressing

HEX

LꢁC294ꢀ

ADDRESS

PINS

DEVICE

DESCRIPꢁION

ADDRESS

BINARY DEVICE ADDRESS

h

a6

1

0

1

aꢀ

1

0

1

a4

0

a3

0

1

0

1

a2

1

0

1

a1

1

0

1

0

1

0

1

a0

0

1

0

1

0

1

0

1

0

1

R/W

0

ADR1

ADR0

X

Mass Write

CC

X

Alert Response

19

1

X

0

1

2

3

4

5

6

7

8

CE

X

H

L

D0

X

NC

H

D2

X

H

D4

X

NC

L

NC

L

D6

X

D8

X

H

DA

DC

DE

X

H

NC

L

X

L

X

L

ꢁable 2. LꢁC294ꢀ Register Addresses and Contents

REGISꢁER

ADDRESS

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

REGISꢁER NAME

READ/WRIꢁE

R/W

DESCRIPꢁION

DEFAULꢁ

05h

00h

XXh

00h

FFh

CONTROL (A)

Controls ADC Operation Mode and Test Mode

Selects Which Faults Generate Alerts

System Status Information

ALERT (B)

R/W

STATUS (C)

R

FAULT (D)

R/W

Fault Log

FAULT CoR (E)

CoR

Same Data as Register D, D Content Cleared on Read

Power MSB2 Data

POWER MSB2

R/W**

R/W

POWER MSB1

Power MSB1 Data

POWER LSB

Power LSB Data

MAX POWER MSB2

MAX POWER MSB1

MAX POWER LSB

Maximum Power MSB2 Data

Maximum Power MSB1 Data

Maximum Power LSB Data

MIN POWER MSB2

MIN POWER MSB1

MIN POWER LSB

Minimum Power MSB2 Data

Minimum Power MSB1 Data

FFh

Minimum Power LSB Data

FFh

MAX POWER THRESHOLD MSB2

MAX POWER THRESHOLD MSB1

MAX POWER THRESHOLD LSB

MIN POWER THRESHOLD MSB2

MIN POWER THRESHOLD MSB1

MIN POWER THRESHOLD LSB

ΔSENSE MSB

Maximum Power Threshold MSB2 to Generate Alert

Maximum Power Threshold MSB1 to Generate Alert

Maximum Power Threshold LSB to Generate Alert

Minimum Power Threshold MSB2 to Generate Alert

Minimum Power Threshold MSB1 to Generate Alert

Minimum Power Threshold LSB to Generate Alert

ΔSENSE MSB Data

FFh

R/W

FFh

10h

11h

12h

13h

14h

15h

16h

R/W

FFh

R/W

00h

XXh

X0h

00h

R/W

R/W**

ΔSENSE LSB

ΔSENSE LSB Data

MAX ΔSENSE MSB

Maximum ΔSENSE MSB Data

2945f

20

LTC2945

APPLICATIONS INFORMATION

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

2Bh

2Ch

2Dh

2Eh

2Fh

30h

31h

MAX ΔSENSE LSB

R/W**

R/W

Maximum ΔSENSE LSB Data

00h

FFh

FOh

FFh

FOh

00h

XXh

X0h

00h

FFh

FOh

FFh

FOh

00h

XXh

X0h

00h

FFh

FOh

FFh

FOh

00h

MIN ΔSENSE MSB

Minimum ΔSENSE MSB Data

MIN ΔSENSE LSB

Minimum ΔSENSE LSB Data

MAX ΔSENSE THRESHOLD MSB

MAX ΔSENSE THRESHOLD LSB

MIN ΔSENSE THRESHOLD MSB

MIN ΔSENSE THRESHOLD LSB

Maximum ΔSENSE Threshold MSB to Generate Alert

Maximum ΔSENSE Threshold LSB to Generate Alert

Minimum ΔSENSE Threshold MSB to Generate Alert

Minimum ΔSENSE Threshold LSB to Generate Alert

R/W

V

MSB

LSB

R/W**

R/W

ADC V MSB Data

IN

V

ADC V LSB Data

IN

MAX V MSB

Maximum V MSB Data

IN

MAX V LSB

Maximum V LSB Data

IN

MIN V MSB

Minimum V MSB Data

IN

MIN V LSB

Minimum V LSB Data

IN

MAX V THRESHOLD MSB

Maximum V Threshold MSB to Generate Alert

IN

MAX V THRESHOLD LSB

R/W

Maximum V Threshold LSB to Generate Alert

IN

MIN V THRESHOLD MSB

R/W

Minimum V Threshold MSB to Generate Alert

IN

MIN V THRESHOLD LSB

R/W

Minimum V Threshold LSB to Generate Alert

IN

ADIN MSB

ADIN LSB

R/W**

R/W

ADIN MSB Data

ADIN LSB Data

MAX ADIN MSB

Maximum ADIN MSB Data

MAX ADIN LSB

Maximum ADIN LSB Data

MIN ADIN MSB

Minimum ADIN MSB Data

MIN ADIN LSB

Minimum ADIN LSB Data

MAX ADIN THRESHOLD MSB

MAX ADIN THRESHOLD LSB

MIN ADIN THRESHOLD MSB

MIN ADIN THRESHOLD LSB

Maximum ADIN Threshold MSB to Generate Alert

Maximum ADIN Threshold LSB to Generate Alert

Minimum ADIN Threshold MSB to Generate Alert

Minimum ADIN Threshold LSB to Generate Alert

R/W

*Register address MSBs b7-b6 are ignored. ** Writable if bit A4 is set

2945f

21

LTC2945

APPLICATIONS INFORMATION

ꢁable 3. CONꢁROL Register A (00h) - Read/Write

BIꢁ

NAME

OPERAꢁION

A7

ADC Snapshot Mode Enable

Enables ADC Snapshot Mode; 1 = Snapshot Mode Enabled. Only channel selected by A6 and A5 is

measured by the ADC. After the conversion, the BUSY bit is reset and the ADC is halted.

0 = Snapshot Mode Disabled (Continuous Scan Mode. Default)

A6

A5

ADC Channel Label for Snapshot Mode ADC Channel Label for Snapshot Mode

A6

0

Aꢀ

0

ADC Channel

ΔSENSE (Default)

0

1

V

IN

1

0

ADIN

A4

Test Mode Enable

Test Mode Halts ADC Operation and Enables Writes to Internal ADC/LOGIC Registers;

1 = Enable Test Mode, 0 = Disable Test Mode (Default)

A3

A2

ADC Busy in Snapshot Mode

ADC Current Status; 1 = ADC Converting, 0 = ADC Conversion Completed (Default), Not Writable

+

V

Monitor

Enables V or SENSE Voltage Monitoring; 1 = Monitor SENSE Voltage (Default),

DD

IN

0 = Monitor V Voltage

DD

A1

A0

Shutdown Enable

Multiplier Select

Enables Low-I / Shutdown Mode; 1 = Enable Shutdown, 0 = Normal Operation (Default)

Q

+

Selects ADIN or SENSE /V (depends on A2) data for digital multiplication with SENSE data;

DD

+

1 = Select SENSE /V (Default), 0 = Select ADIN

DD

ꢁable 4. ALERꢁ Register B (01h) - Read/Write

BIꢁ

NAME

OPERAꢁION

B7

Maximum POWER Alert

Enables Alert When POWER Calculation Data is > Maximum Power Threshold;

1 = Enable Alert,

0 = Disable Alert (Default)

B6

B5

B4

B3

B2

B1

B0

Minimum POWER Alert

Maximum ΔSENSE Alert

Minimum ΔSENSE Alert

Enables Alert When POWER Calculation Data is < Minimum Power Threshold;

1 = Enable Alert,

0 = Disable Alert (Default)

Enables Alert When ADC ΔSENSE Measurement Data is > Maximum ΔSENSE Threshold;

1 = Enable Alert,

0 = Disable Alert (Default)

Enables Alert When ADC ΔSENSE Measurement Data is < Minimum ΔSENSE Threshold;

1 = Enable Alert,

0 = Disable Alert (Default)

Maximum V Alert

Enables Alert When ADC V Measurement Data is > Maximum V Threshold;

IN

IN IN

1 = Enable Alert,

0 = Disable Alert (Default)

Minimum V Alert

Enables Alert When ADC V Measurement Data is < Minimum V Threshold;

IN

IN IN

1 = Enable Alert,

0 = Disable Alert (Default)

Enables Alert When ADC ADIN Measurement Data is > Maximum ADIN Threshold;

1 = Enable Alert,

0 = Disable Alert (Default)

Enables Alert When ADC ADIN Measurement Data is < Minimum ADIN Threshold;

1 = Enable Alert,

Maximum ADIN Alert

Minimum ADIN Alert

0 = Disable Alert (Default)

2945f

22

LTC2945

APPLICATIONS INFORMATION

ꢁable ꢀ. SꢁAꢁUS Register C (02h) - Read

BIꢁ

NAME

OPERAꢁION

C7

POWER Overvalue Present

Indicates POWER Overvalue When POWER is > Maximum Power Threshold;

1 = POWER Overvalue,

0 = POWER Not Overvalue

C6

C5

C4

C3

C2

C1

C0

POWER Undervalue Present Indicates POWER Undervalue When POWER is < Minimum Power Threshold;

1 = POWER Undervalue,

0 = POWER Not Undervalue

ΔSENSE Overvalue Present

Indicates ΔSENSE Overvalue When ΔSENSE is > Maximum ΔSENSE Threshold;

1 = ΔSENSE Overvalue,

0 = ΔSENSE Not Overvalue

ΔSENSE Undervalue Present Indicates ΔSENSE Undervalue When ΔSENSE is < Minimum ΔSENSE Threshold;

1 = ΔSENSE Undervalue,

0 = ΔSENSE Not Undervalue

V

Overvalue Present

Undervalue Present

Indicates V Overvalue When V is > Maximum V Threshold;

IN IN IN

IN

1 = V Overvalue,

IN

0 = V Not Overvalue

IN

Indicates V Undervalue When V is < Minimum V Threshold;

IN

1 = V Undervalue,

IN

0 = V Not Undervalue

IN

ADIN Overvalue Present

ADIN Undervalue Present

Indicates ADIN Overvalue When ADIN is > Maximum ADIN Threshold;

1 = ADIN Overvalue,

0 = ADIN Not Overvalue

Indicates ADIN Undervalue When ADIN is < Minimum ADIN Threshold;

1 = ADIN Undervalue,

0 = ADIN Not Undervalue

ꢁable 6. FAULꢁ Register D (03h) - Read/Write

BIꢁ

NAME

OPERAꢁION

D7

POWER Overvalue Fault

Occurred

Indicates POWER Overvalue Fault When POWER was > Maximum Power Threshold;

1 = POWER Overvalue Fault Occurred,

0 = No POWER Overvalue Faults

D6

D5

D4

D3

D2

D1

D0

POWER Undervalue Fault

Occurred

Indicates POWER Undervalue Fault When POWER was < Minimum Power Threshold;

1 = POWER Undervalue Fault Occurred,

0 = No POWER Undervalue Faults

Indicates ΔSENSE Overvalue Fault When ΔSENSE was > Maximum ΔSENSE Threshold;

1 = ΔSENSE Overvalue Fault Occurred,

0 = No ΔSENSE Overvalue Faults

Indicates ΔSENSE Undervalue Fault When ΔSENSE was < Minimum ΔSENSE Threshold;

1 = ΔSENSE Undervalue Fault Occurred,

0 = No ΔSENSE Undervalue Faults

ΔSENSE Overvalue Fault

Occurred

ΔSENSE Undervalue Fault

Occurred

V

Overvalue Fault

Indicates V Overvalue Fault When V was > Maximum V Threshold;

IN

IN IN IN

Occurred

1 = V Overvalue Fault Occurred,

IN

0 = No V Overvalue Faults

IN

V

IN

Undervalue Fault

Indicates V Undervalue Fault When V was < Minimum V Threshold;

IN IN IN

Occurred

1 = V Undervalue Fault Occurred,

IN

0 = No V Undervalue Faults

IN

ADIN Overvalue Fault

Occurred

Indicates ADIN Overvalue Fault When ADIN was > Maximum ADIN Threshold;

1 = ADIN Overvalue Fault Occurred,

0 = No ADIN Overvalue Faults

Indicates ADIN Undervalue Fault When ADIN was < Minimum ADIN Threshold;

1 = ADIN Undervalue Fault Occurred,

ADIN Undervalue Fault

Occurred

0 = No ADIN Undervalue Faults

2945f

23

LTC2945

APPLICATIONS INFORMATION

ꢁable 7. ADC, ADC MIN/MAX, MIN/MAX ADC ꢁHRESHOLD Register Data Format: MSB Bytes-Read/Write*

BIꢁ (7)

BIꢁ (6)

BIꢁ (ꢀ)

BIꢁ (4)

BIꢁ (3)

BIꢁ (2)

BIꢁ (1)

BIꢁ (0)

Data (11)

Data (10)

Data (9)

Data (8)

Data (7)

Data (6)

Data (5)

Data (4)

*Set Bit A4 before writing to ADC and MIN/MAX ADC Registers

ꢁable 8. ADC, ADC MIN/MAX, MIN/MAX ꢁHRESHOLD Register Data Format: LSB Bytes-Read/Write*

BIꢁ (7)

BIꢁ (6)

BIꢁ (ꢀ)

BIꢁ (4)

BIꢁ (3)

BIꢁ (2)

BIꢁ (1)

BIꢁ (0)

Data (3)

Data (2)

Data (1)

Data (0)

Reserved**

* Set Bit A4 before writing to ADC and MIN/MAX ADC Registers

** Read as ‘0’

ꢁable 9. POWER, MIN/MAX POWER, MIN/MAX POWER ꢁHRESHOLD Register Data Format: MSB2 Bytes- Read/Write*

BIꢁ (7)

BIꢁ (6)

BIꢁ (ꢀ)

BIꢁ (4)

BIꢁ (3)

BIꢁ (2)

BIꢁ (1)

BIꢁ (0)

Data (23)

Data (22)

Data (21)

Data (20)

Data (19)

Data (18)

Data (17)

Data (16)

* Set Bit A4 before writing to POWER and MIN/MAX POWER Registers

ꢁable 10. POWER, MIN/MAX POWER, MIN/MAX POWER ꢁHRESHOLD Register Data Format: MSB1 Bytes- Read/Write*

BIꢁ (7)

BIꢁ (6)

BIꢁ (ꢀ)

BIꢁ (4)

BIꢁ (3)

BIꢁ (2)

BIꢁ (1)

BIꢁ (0)

Data (15)

Data (14)

Data (13)

Data (12)

Data (11)

Data (10)

Data (9)

Data (8)

* Set Bit A4 before writing to POWER and MIN/MAX POWER Registers

ꢁable 11. POWER, MIN/MAX POWER, MIN/MAX POWER ꢁHRESHOLD Register Data Format: LSB Bytes- Read/Write*

BIꢁ (7)

BIꢁ (6)

BIꢁ (ꢀ)

BIꢁ (4)

BIꢁ (3)

BIꢁ (2)

BIꢁ (1)

BIꢁ (0)

Data (7)

Data (6)

Data (5)

Data (4)

Data (3)

Data (2)

Data (1)

Data (0)

* Set Bit A4 before writing to POWER and MIN/MAX POWER Registers

2945f

24

LTC2945

TYPICAL APPLICATIONS

A Wide Range Supply Monitor

Wide Range Supply Monitor with Wide Range V_DDInput

R

SNS

0.02Ω

SNS

0.02Ω

V

IN

4V TO 80V

IN

3.3V

V

OUT

V

OUT

0V TO 80V

+

–

+

–

SENSE

R1

2k

R2

2k

R3

2k

R1

2k

R2

2k

R3

2k

V

DD

V

DD

SCL

SDA

SCL

SDA

2.7V TO 5.9V

V

DD

SCL

DD

LTC2945

μP

LTC2945

μP

SDAI

INTV

CC

C2

0.1μF

C2

0.1μF

ADR1

SDAO

ADR1

SDAO

ALERT

INT

ALERT

INT

ADR0

V

ADIN

V

ADIN

GND

2945 TA02

2945 TA03

Dual Supply Monitor with Common Opto-coupler for Galvanic Isolation

3.3V

R8

R9

R10 R11 R12

0.51k 0.51k 10k 10k 10k

R

SNS1

0.02Ω

V

24V

IN1

V

OUT1

HCPL063L

R4

10k 10k

R5

V

+

–

CC

SENSE

SCL

V

DD

C1

1μF

V

DD

LTC2945

GND

SCL

SDAI

INTV

CC

C2

0.1μF

ADR1

ADR0

SDAO

ALERT

ADIN

GND

μP

V

ADIN1

R6

1k

R7

1k

3.3V

R

V

CC

SNS2

0.02Ω

V

48V

IN2

SDA

V

OUT2

GND

+

–

SENSE

INT

V

DD

SCL

C3

1μF

GND

LTC2945

HCPL063L

INTV

SDAI

SDAO

ALERT

CC

C4

0.1μF

ADR1

ADR0

V

ADIN2

ADIN

GND

2945 TA04

2945f

25

LTC2945

TYPICAL APPLICATIONS

Power Monitoring in –48V System Using Low Side Sensing (1.ꢀkHz I²C Interface)

–48V

RTN

R1

R2

20k 20k

3.3V

V

INTV

ADR1

CC

DD

C2

C1

R7

R8

R9

R10 R11

R4 R3

1k 1k

0.1μF

1μF

0.51k 0.51k 10k 10k 10k

V

DD

SCL

LTC2945

SCL

SDAI

μP

V

EE

MOCD207M

GND

SDA

ADIN

SDAO

ADR0

INT

GND

ALERT

–

+

SENSE

MOCD207M

CONTROL REGISTER A2 = 0

V

EE

V

OUT

–48V INPUT

R

SNS

0.02Ω

2945 TA05

Power Monitoring in –48V Harsh Environment Using INꢁV_CCShunt Regulator to ꢁolerate 200V ꢁransients

–48V

RTN

R

SHUNT

R12

100

3 × 1.8k IN SERIES

Q1

PZTA42

D1

1N4148WS

3.3V

C2

V

DD

1μF

R7

0.51k

R8

0.51k

R9

1k

R10 R11

1k 10k

R4 R3

1k 0.51k

R1

1k

R2

1k

INTV

CC

V

EE

ADR1

V

DD

V

CC

R5

735k

SCL

LTC2945

SCL

SDA

C1

1μF

ADIN

SDAI

μP

GND

R6

15k

HCPL-063L

V

EE

3.3V

V

CC

GND

ADR0

SDAO

INT

GND

ALERT

2945 TA06

GND

–

+

SENSE

HCPL-063L

CONTROL REGISTER A0 = 0

V

EE

V

OUT

–48V INPUT

R

SNS

0.02Ω

2945f

26

LTC2945

TYPICAL APPLICATIONS

Power Monitoring in –48V System Using External Linear Regulator to Supply Opto-couplers and SCL/SDA Resistive Pull-Ups

LT3010-5

OUT

–48V

RTN

IN

C3

0.1μF

C2

1μF

SHDN SENSE

GND

5V

DD

V

EE

R7

0.5k

R8

R9

R10 R11

1k 10k

V

DD

0.51k 1k

R4 R3

1k 0.51k 1k

R1

R2

10k

ADR1

V

CC

INTV

CC

SCL

LTC2945

C1

1μF

SCL

SDA

SDAI

GND

μP

PS9817-2

5V

V

EE

GND

V

CC

ADIN

SDAO

ADR0

INT

GND

ALERT

2945 TA07

GND

–

+

SENSE

PS9817-2

CONTROL REGISTER A2 = 0

V

EE

V

OUT

–48V INPUT

R

SNS

0.02Ω

Wide Range Dual Supply Monitor with Single LꢁC294ꢀ

D1

BAT54

R

SNS1

0.02Ω

SUPPLY B

4.5V TO 80V

R

TO

LOAD

SNS

R

1k

R

1k

IN1

IN2

0.02Ω

SUPPLY A

4.5V TO 80V

+

–

D2

BAT54

SENSE

DD

SENSE

V

–INF –INS

+IN

C3

0.1μF

R

SHUNT*

+

LTC2945

V

C1

0.1μF

LTC6102

SCL

INTV

CC

2

I C

C2

0.1μF

ADR1

SDAI

REG

INTERFACE

OUT

ADIN

SDAO

–

ADR0

ALERT

R

20k

ADIN

V

GND

2945 TA08

CONꢁROL REG

A2

VOLꢁAGE

DAꢁA

CURRENꢁ POWER

DAꢁA DAꢁA

+

SUPPLY A

SUPPLY B

1

0

SENSE

ΔSENSE INTERNALLY GENERATED

V

DD

**

ADIN

USE EXTERNAL μP TO MULTIPLY VOLTAGE (V

AND CURRENT (ADIN) DATA

)

DD

* SELECT RSHUNT ACCORDING TO THE EQUATION IN THE “FLEXIBLE POWER SUPPLY TO LTC2945” SECTION.

** VOLTAGE DATA HAS AN OFFSET VALUE DUE TO D1’S DROP, IF DESIRABLE THIS CAN BE COMPENSATED THROUGH SOFTWARE.

2945f

27

LTC2945

TYPICAL APPLICATIONS

Ruggedized 4V to 80V High Side Power Monitor with Surge Protection Up to 200V

R

SNS

0.02Ω

V

OUT

IN

R12

100Ω

+

–

SENSE

DD

SENSE

INTV

Q1

PZTA42

V

CC

3.3V

C2

1μF

R7

0.51k

R8

0.51k

R9

1k

R10 R11

1k 10k

R4 R3

1k 0.51k

R1

1k

R2

1k

V

EE

LTC2945

V

DD

V

T1

SMAJ78A

CC

SCL

SDA

C1

0.1μF

SDAI

μP

GND

HCPL-063L

FGND

3.3V

V

CC

ADR1

ADR0

ADIN

SDAO

INT

GND

ALERT

2945 TA09

GND

M1

HCPL-063L

FGND

BSP149

R5

1Ω

2945f

28

LTC2945

TYPICAL APPLICATIONS

Wide Range –4V to –ꢀ00V Negative Power Monitor (10kHz I²C Interface)

RTN

M1

R5

BSP135

750k

R13

10k

3.3V

R4 R3

1k 1k

R1

2k

R2

2k

C1

0.1μF

R7

R8

R9

R10 R11

10k

V

DD

V

R6

750k

EE

0.51k 0.51k 10k 10k

V

DD

SCL

Z1

4.7V

LTC2945

SCL

SDAI

V

EE

ADIN

μP

MOCD207M

GND

SDA

R12

5k

ADR1

ADR0

SDAO

INT

GND

2945 TA10

INTV

ALERT

CC

C2

0.1μF

–

+

SENSE

MOCD207M

CONTROL REGISTER A2 = 0

V

EE

V

OUT

R

SNS

0.02Ω

2945f

29

LTC2945

PACKAGE DESCRIPTION

MS Package

12-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1668 Rev Ø)

0.889 p 0.127

(.035 p .005)

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

4.039 p 0.102

(.159 p .004)

(NOTE 3)

0.65

(.0256)

BSC

0.42 p 0.038

(.0165 p .0015)

TYP

0.406 p 0.076

(.016 p .003)

REF

12 11 10 9 8 7

RECOMMENDED SOLDER PAD LAYOUT

DETAIL “A”

0o – 6o TYP

3.00 p 0.102

(.118 p .004)

(NOTE 4)

4.90 p 0.152

(.193 p .006)

0.254

(.010)

GAUGE PLANE

0.53 p 0.152

(.021 p .006)

1

2 3 4 5 6

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.22 – 0.38

(.009 – .015)

TYP

0.1016 p 0.0508

(.004 p .002)

MSOP (MS12) 1107 REV Ø

0.650

(.0256)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

2945f

30

LTC2945

PACKAGE DESCRIPTION

UD Package

12-Lead Plastic QFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1855 Rev Ø)

0.70 p0.05

3.50 p 0.05

2.10 p 0.05

1.65 p 0.05

(4 SIDES)

PACKAGE OUTLINE

0.25 p0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.20 TYP

OR 0.25 s 45o CHAMFER

R = 0.115

TYP

0.75 p 0.05

3.00 p 0.10

(4 SIDES)

11 12

PIN 1

TOP MARK

(NOTE 6)

0.40 p 0.10

1

2

1.65 p 0.10

(4-SIDES)

(UD12) QFN 0709 REV Ø

0.200 REF

0.25 p 0.05

0.00 – 0.05

0.50 BSC

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

2945f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

31

LTC2945

TYPICAL APPLICATION

3.3V Input Supply Monitor with 12V V_DDInput

Rail-to-Rail Bidirectional Current and Power Monitor

R

SNS

+

–

LT6105

0.02Ω

V

3.3V

IN

V

OUT

V

3.3V

OUT

–

+

–

R1 R2 R3

2k 2k 2k

IN

IN1

IN

SENSE

V

DD

R

IN2

1k

R

1k

V

SCL

SDA

12V

SNS

DD

LTC2945

0.02Ω

V

TO

LOAD

IN

μP

INTV

SDAI

SDAO

ALERT

CC

0V TO 44V

ADR1

ADR0

+

–

SENSE

C2

0.1μF

INT

V

ADIN

GND

V

SCL

DD

LTC2945

GND

2945 TA12

2

2.7V TO 5.9V

INTV

SDAI

I C

CC

INTERFACE

SDAO

ADR1

ALERT

ADR0

ADIN

R

20k

ADIN

2945 TA11

CONꢁROL REG

A2

VOLꢁAGE

CURRENꢁ

POWER

DAꢁA

SENSE

DAꢁA

ΔSENSE

ADIN

+

FORWARD

REVERSE

1

INTERNALLY GENERATED

USE EXTERNAL μP TO

+

MULTIPLY VOLTAGE (SENSE )

AND CURRENT (ADIN) DATA

RELATED PARTS

PARꢁ NUMBER DESCRIPꢁION

COMMENꢁS

2

LTC4151

LT6105

High Voltage I C Current and Voltage Monitor

Rail-to-Rail Input Current Sense Amplifier

Easy-to-Use, Ultra-Tiny 16-Bit ADC

7V to 80V Operation, 12-Bit Resolution with 1.25% TUE

Very Wide Input Common Mode Range, 2.85V to 36V Operation

LTC2450

GND to V Single-Ended Input Range, 0.02 LSB RMS Noise, 2 LSB INL

CC

(No Missing Codes), 2 LSB Offset Error, 4 LSB Full-Scale Error

8-Bit ADC, Adjustable Current Limit and Inrush, 2.9V to 15V Operation

10-Bit ADC, Adjustable Current Limit and Inrush, 2.9V to 29V Operation

2

LTC4215

LTC4222

LTC4260

LTC4261

LTC2940

LTC2970

LTC2974

Single Channel, Hot Swap Controller with I C Monitoring

2

Dual Channel, Hot Swap Controller with I C Monitoring

2

Positive High Voltage Hot Swap Controller with I C Monitoring 8-Bit ADC, Adjustable Current Limit and Inrush, 8.5V to 80V Operation

2

Negative High Voltage Hot Swap Controller with I C Monitoring 10-Bit ADC, Floating Topology, Adjustable Inrush

Power and Current Monitor

Four-Quadrant Multiplication, 5% Power Accuracy, 4V to 80V Operation

14-Bit ADC with 0.5% TUE, Dual 8-Bit DACs

2

Dual I C Power Supply Monitor and Margining Controller

Quad Digital Power Supply Manager with EEPROM

16-Bit ADC with 0.25% TUE, Supervise/Sequence/Monitor/Margin/

2

Trim, Configuration/Fault Logging EEPROM, I C, Supervise/Monitor

Current and Temperature

LTC2978

Octal Digital Power Supply Manager with EEPROM

16-Bit ADC with 0.25% TUE, Supervise/Sequence/Monitor/Margin/

2

Trim, Configuration/Fault Logging EEPROM, I C

2945f

LT 1012 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2974
厂家：	Linear
描述：	Wide Range I2C Power Monitor Rail-to-Rail Input Range: 0V to 80V 宽范围I2C电源监视器，轨到轨输入范围： 0V至80V 监视器
文件：	总32页 (文件大小：1394K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2974 [Linear]

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