UPD8872 [NEC]
(5400 + 5400) PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR; ( 5400 + 5400 )像素× 3彩色CCD线性图像传感器型号: | UPD8872 |
厂家: | NEC |
描述: | (5400 + 5400) PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR |
文件: | 总24页 (文件大小:187K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD8872
(5400 + 5400) PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
DESCRIPTION
The µPD8872 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The µPD8872 has 3 rows of (5400 + 5400) staggered pixels, and each row has a dual-sided readout-type charge
transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for
1200 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
• Valid photocell
: (5400 + 5400) staggered pixels × 3
• Photocell pitch : 5.25 µm
• Line spacing
: 63 µm (12 lines) Red line - Green line, Green line - Blue line
10.5 µm (2 lines) Odd line - Even line (for each color)
: Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
: 48 dot/mm A4 (210 × 297 mm) size (shorter side)
• Color filter
• Resolution
1200 dpi US letter (8.5” × 11”) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate
: 10 MHz Max.
: +12 V
• Power supply
• On-chip circuits : Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
µPD8872CY
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S15330EJ3V0DS00 (3rd edition)
Date Published July 2003 NS CP (K)
Printed in Japan
The mark
shows major revised points.
µPD8872
BLOCK DIAGRAM
φ
φ
φ
2L
2
1
VOD
GND GND
17
1
11
19
15
14
CCD analog shift register
Transfer gate
φ
TG1
(Blue)
13
12
10
V
(Blue)
OUT
1
20
21
22
Photocell
(Blue)
······
······
······
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
φ
TG2
(Green)
V
OUT2
Photocell
(Green)
(Green)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
φ
TG3
(Red)
V
(Red)
OUT3
Photocell
(Red)
Transfer gate
CCD analog shift register
3
2
4
8
9
φ
φ
1
φ
φ
2
φ
RB
1L
CLB
2
Data Sheet S15330EJ3V0DS
µPD8872
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
• µPD8872CY
Ground
Reset gate clock
GND
1
2
22
21
20
19
V
V
V
φ
OUT
OUT
OUT
2L
3
2
1
Output signal 3 (Red)
φ
Output signal 2 (Green)
Output signal 1 (Blue)
Last stage shift register clock 2
No connection
RB
Reset feed-through level clamp clock
Last stage shift register clock 1
No connection
φ
3
CLB
φ
4
1L
NC
NC
NC
5
18 NC
17
16 NC
No connection
6
VOD
Output drain voltage
No connection
No connection
7
Shift register clock 2
φ
φ
2
1
8
15
14
13
12
φ
φ
φ
φ
2
1
Shift register clock 2
Shift register clock 1
Shift register clock 1
9
Transfer gate clock 3
(for Red)
Transfer gate clock 1
(for Blue)
φ
10
TG1
TG2
TG3
Transfer gate clock 2
(for Green)
GND 11
Ground
Caution Connect the No connection pins (NC) to GND.
3
Data Sheet S15330EJ3V0DS
µPD8872
PHOTOCELL STRUCTURE DIAGRAM
2.5
µ
m
2.75
µ
m
µ
Channel stopper
Aluminum
shield
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
5.25 µm
5.25 µm
5.25 µm
Blue photocell array
Blue photocell array
2 lines
(10.5
µ
m)
12 lines
(63 m)
µ
10 lines
(52.5
µ
m)
5.25 µm
5.25 µm
5.25 µm
Green photocell array
Green photocell array
2 lines
(10.5
µ
m)
12 lines
(63 m)
µ
10 lines
(52.5
µ
m)
5.25
5.25
5.25
µ
µ
µ
m
m
m
Red photocell array
Red photocell array
2 lines
(10.5
µ
m)
4
Data Sheet S15330EJ3V0DS
µPD8872
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Output drain voltage
Symbol
Ratings
−0.3 to +15
−0.3 to +8
−0.3 to +8
−0.3 to +8
Unit
V
VOD
Shift register clock voltage
Reset gate clock voltage
Vφ 1, Vφ 2, Vφ 1L, Vφ 2L
V
Vφ RB
V
Reset feed-through level clamp clock
voltage
Vφ CLB
V
Transfer gate clock voltage
Operating ambient temperatureNote
Storage temperature
Vφ TG1 to Vφ TG3
−0.3 to +8
0 to +60
V
TA
°C
°C
Tstg
−40 to +70
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter
Output drain voltage
Symbol
Min.
11.4
4.75
−0.3
4.5
Typ.
12.0
5.0
0
Max.
12.6
5.5
Unit
V
VOD
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Vφ 1_H, Vφ 2_H, Vφ 1LH, Vφ 2LH
V
Vφ 1_L, Vφ 2_L, Vφ 1LL, Vφ 2LL
+0.25
5.5
V
Vφ RBH
Vφ RBL
Vφ CLBH
5.0
0
V
−0.3
4.5
+0.5
5.5
V
Reset feed-through level clamp clock
high level
5.0
V
Reset feed-through level clamp clock
low level
Vφ CLBL
−0.3
0
+0.5
V
Note
Note
Transfer gate clock high level
Transfer gate clock low level
Data rate
Vφ TG1H to Vφ TG3H
Vφ TG1L to Vφ TG3L
fφ RB
4.75
−0.3
−
Vφ1_ H
Vφ 1_H
V
V
0
+0.15
2.0
10.0
MHz
Note When Transfer gate clock high level (Vφ TG1H to Vφ TG3H) is higher than Shift register clock high level (Vφ 1_H),
Image lag can increase.
5
Data Sheet S15330EJ3V0DS
µPD8872
ELECTRICAL CHARACTERISTICS
TA = +25°C, VOD = 12 V, data rate (fφ RB) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p,
light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter
Saturation voltage
Saturation exposure
Symbol
Vsat
Test Conditions
Min.
Typ.
3.0
Max.
−
Unit
V
2.7
Red
SER
SEG
SEB
PRNU
ADS
DSNU
PW
−
0.505
0.573
0.888
6
−
lx•s
lx•s
lx•s
%
Green
Blue
−
−
−
−
Photo response non-uniformity
Average dark signal
VOUT = 1.0 V
−
20
2.0
5.0
540
1.00
7.73
6.82
4.39
7.0
7.5
−
Light shielding
Light shielding
−
0.2
mV
mV
mW
kΩ
Dark signal non-uniformity
Power consumption
−
1.5
−
360
0.35
5.94
5.24
3.38
3.0
Output impedance
ZO
−
4.15
3.66
2.36
−
Response
Red
RR
V/lx•s
V/lx•s
V/lx•s
%
Green
Blue
RG
RB
Image lag
Offset level Note 1
Output fall delay time Note 2
Total transfer efficiency
Register imbalance
Response peak
IL
VOUT = 1.0 V
VOS
td
4.5
−
6.0
V
VOUT = 1.0 V, t1’, t2’ = 5 ns
VOUT = 1.0 V, data rate = 10 MHz
VOUT = 1.0 V
25
ns
TTE
RI
92
−
98
−
%
1.0
4.0
−
%
Red
−
630
540
460
2000
3000
+300
1.0
nm
Green
Blue
−
−
nm
−
−
nm
Dynamic range
DR1
Vsat/DSNU
−
−
times
times
mV
mV
DR2
Vsat/σCDS
−
−
Reset feed-through noise Notes 1, 3
Random noise (CDS)
RFTN
σCDS
Light shielding
Light shielding
−2000
−
+1000
−
Notes 1. Refer to TIMING CHART 2, 3.
2. When the fall time of φ 1L and φ 2L (t1’, t2’) is the Typ. value (refer to TIMING CHART 2, 3).
3. The reset feed-through noise changes by peripheral circuit of register, the driver circuit for φ RB and so on.
6
Data Sheet S15330EJ3V0DS
µPD8872
INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V)
Parameter
Symbol
Pin name Pin No.
Min.
−
Typ.
500
500
1000
500
500
1000
10
Max.
−
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Shift register clock pin capacitance 1
Cφ 1
φ 1
9
14
−
−
φ 1 total capacitance
φ 2
−
−
Shift register clock pin capacitance 2
Cφ 2
8
−
−
15
−
−
φ 2 total capacitance
−
−
Last stage shift register clock pin capacitance
Reset gate clock pin capacitance
Cφ L
φ 1L
4
19
2
−
−
φ 2L
−
10
−
Cφ RB
φ RB
−
10
−
Reset feed-through level clamp clock pin capacitance Cφ CLB
Transfer gate clock pin capacitance Cφ TG
φ CLB
φ TG1
φ TG2
φ TG3
3
−
10
−
13
12
10
−
200
200
200
−
−
−
−
−
Remarks 1. Pins 9 and 14 (φ 1), 8 and 15 (φ 2) are each connected inside of the device.
2. Cφ 1 and Cφ 2 show the equivalent capacity of the real drive including the capacity of between φ 1 and
φ 2.
7
Data Sheet S15330EJ3V0DS
TIMING CHART 1-1 (Bit clamp mode, for each color)
φ
TG1 to
φ
1,
2,
TG3
φ
φ
φ
φ
1L
2L
φ
RB
Note
Note
φ
CLB
VOUT1 to VOUT3
Optical black
(49 pixels)
Valid photocell
(10800 pixels)
Invalid photocell
(4 pixels)
Invalid photocell
(4 pixels)
Note Set the φ RB and φ CLB to high level during this period.
µ
TIMING CHART 1-2 (Line clamp mode, for each color)
φ
TG1 to
φ
1,
2,
TG3
φ
φ
φ
φ
1L
2L
φ
RB
Note
Note
φ
CLB
(φ TG1 to φ TG3)
V
OUT1 to VOUT3
Optical black
(49 pixels)
Valid photocell
(10800 pixels)
Invalid photocell
(4 pixels)
Invalid photocell
(4 pixels)
Note Set the φ RB to high level during this period.
Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB.
µ
µPD8872
TIMING CHART 2 (Bit clamp mode, for each color)
t1
t2
90%
φ
φ
1
2
10%
90%
10%
t1'
t2'
90%
10%
φ
φ
1L
2L
90%
10%
t5
t6
t5
t6
t3
t4
t3
t4
90%
10%
φ
RB
t9
t10
t9
t10
t7
t8
t11
t7
t8
t11
90%
10%
φ
CLB
td
t
d
RFTN
RFTN
V
OUT
V
OS
10%
Symbol
t1, t2
Min.
Typ.
25
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
−
−
−
−
−
−
−
−
−
t1’, t2’
t3
5
20
30
0
−5 Note
20
0
100
150
25
t4
t5, t6
t7
25
t8
100
25
t9, t10
t11
5
25
Note Min. of t7 shows that the φ RB and φ CLB overlap each other.
90%
φ
RB
t7
90%
φ
CLB
10
Data Sheet S15330EJ3V0DS
µPD8872
TIMING CHART 3 (Line clamp mode, for each color)
t1
t2
90%
φ
φ
1
2
10%
90%
10%
t1'
t2'
90%
10%
φ
φ
1L
2L
90%
10%
t5
t6
t5
t6
t3
t4
t3
t4
90%
10%
φ
RB
"H"
φ
CLB
td
t
d
RFTN
RFTN
V
OUT
V
OS
10%
Symbol
Min.
0
Typ.
25
Max.
Unit
t1, t2
−
−
−
−
−
ns
ns
ns
ns
ns
t1’, t2’
t3
0
5
20
30
0
100
150
25
t4
t5, t6
11
Data Sheet S15330EJ3V0DS
µPD8872
φ TG1 to φ TG3, φ 1, φ 2 TIMING CHART
t13
90%
10%
t15
t14
t12
φ
TG1 to φ TG3
t16
90%
φ
φ
1
2
t17
90%
t7
Note 1
t18
φ
RB
90%
φ
CLB
(Bit clamp mode)
t20
t21
t22
Note 2
t23
90%
10%
φ
CLB
(Line clamp mode)
t9
t19
t10
Symbol
Min.
−5 Note 3
0
Typ.
25
Max.
Unit
t7
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
t9, t10
t12
25
−
5000
0
10000
50
50000
t13, t14
t15, t16
t17, t18
t19
−
900
200
t12
0
1000
400
t12
−
−
50000
t20, t21
t22, t23
50
−
−
0
350
Notes 1. Set the φ RB and φ CLB to high level during this period.
2. Set the φ RB to high level during this period.
3. Min. of t7 shows that the φ RB and φ CLB overlap each other.
90%
φ
RB
t7
90%
φ
CLB
Remark Inverse pulse of the φ TG1 to φ TG3 can be used as φ CLB.
12
Data Sheet S15330EJ3V0DS
µPD8872
φ 1, φ 2 cross points
φ
1
2
1.0 V to 4.0 V
1.0 V to 4.0 V
φ
φ 1, φ 2L cross points
φ
1
2.0 V or more
0.5 V or more
φ
2L
φ 2, φ 1L cross points
φ
2
2.0 V or more
0.5 V or more
φ
1L
Remark Adjust cross points (φ 1, φ 2), (φ 1, φ 2L) and (φ 2, φ 1L) with input resistance of each pin.
13
Data Sheet S15330EJ3V0DS
µPD8872
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
x
∆
PRNU (%) =
× 100
x
∆
x : maximum of x
j
− x
10800
x
j
Σ
j = 1
10800
: Output voltage of valid pixel number j
x =
xj
VOUT
x
Register Dark
DC level
∆
x
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following
formula.
10800
d
j
Σ
j = 1
10800
ADS (mV) =
d
j
: Dark signal of valid pixel number j
14
Data Sheet S15330EJ3V0DS
µPD8872
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the
valid pixels at light shielding. This is calculated by the following formula.
DSNU (mV) : maximum of d
j
− ADS j = 1 to 10800
d
j
: Dark signal of valid pixel number j
VOUT
ADS
Register Dark
DC level
DSNU
6. Output impedance : ZO
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lx•s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
φ
TG
Light
ON
OFF
V
OUT
V
1
V
OUT
V
1
IL (%) =
× 100
OUT
V
15
Data Sheet S15330EJ3V0DS
µPD8872
9. Register imbalance: RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the
average output voltage of all the valid pixels.
n
2
2
n
∑
(V2j –1 – V2j
n
)
j = 1
RI (%) =
× 100
1
n
∑
V
j
j = 1
n
V
: Number of valid pixels
: Output voltage of each pixel
j
10. Random noise (CDS) : σCDS
Random noise σCDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100
lines) data sampling at dark (light shielding). σCDS is calculated by the following procedure.
1. One valid photocell in one reading is fixed as measurement point.
2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get
“VDi”.
3. The output level is measured during the video output time averaged over 100 ns to get “VOi”.
4. The correlated double sampling output is defined by the following formula.
VCDSi = VDi – VOi
5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines).
6. Calculate the standard deviation σ CDS using the following formula equation.
100
100
(VCDS
100
i
– V)2
1
Σ
σ
CDS (mV) =
, V =
VCDS
i
100 Σ
i = 1
i = 1
Reset feed-through
Video output
16
Data Sheet S15330EJ3V0DS
µPD8872
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T = +25°C)
A
8
2
4
2
1
1
0.5
0.25
0.2
0.1
0.1
0
10
20
30
40
50
1
5
10
Operating Ambient Temperature T
A
(°C)
Storage Time (ms)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter) (T = +25°C)
A
100
80
R
B
G
60
40
20
G
B
0
400
500
600
700
800
Wavelength (nm)
17
Data Sheet S15330EJ3V0DS
µPD8872
APPLICATION CIRCUIT EXAMPLE
+5 V
+12 V
+
+
µ
PD8872
1
2
22
21
20
19
18
17
16
15
14
13
12
10 µF/16 V 0.1 µF
GND
V
OUT
OUT
OUT
3
2
1
B3
B2
0.1
µ
F 47
µ
F/25 V
+5 V
47
Ω
φ
RB
CLB
1L
φ
φ
φ
RB
V
V
47 Ω
3
φ
CLB
1L
B1
150 Ω
150 Ω
4
φ
φ
2L
5
+
NC
NC
NC
NC
6
VOD
0.1
µ
F 10
µ
F/16 V
7
NC
φ
2L
4.7 Ω
4.7 Ω
10 Ω
4.7 Ω
8
φ
2
φ
φ
φ
2
φ
φ
2
1
4.7 Ω
10 Ω
10 Ω
9
1
φ
φ
1
10
11
TG3
φ
φ
TG1
TG2
TG
GND
Caution Connect the No connection pins (NC) to GND.
Remarks 1. The inverters shown in the above application circuit example are the 74HC04 (data rate < 2 MHz) or
the 74AC04 (2 ≤ data rate < 10 MHz).
2. Inverters B1 to B3 in the above application circuit example are shown in the figure below.
B1 to B3 EQUIVALENT CIRCUIT
12 V
+
µ
47 F/25 V
100 Ω
CCD
2SC945
2 kΩ
V
OUT
100 Ω
18
Data Sheet S15330EJ3V0DS
µPD8872
PACKAGE DRAWING
µ
PD8872CY
CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400) )
(Unit : mm)
44.0 0.3
1st valid pixel
1
9.25 0.3
0.5 0.3
22
12
11
1
2.0
37.5
2
10.16 0.2
(1.79)
1.02 0.15
4.39 0.4
3
2.55 0.2
(5.42)
4.21 0.5
0.25 0.05
0.46 0.1
2.54 0.25
+0.7
10.16
−0.2
Name
Dimensions
42.9×8.35×0.7
Refractive index
Plastic cap
1.5
1 1st valid pixel
The center of the pin1
2 The surface of the CCD chip
3 The bottom of the package
The top of the cap
The surface of the CCD chip
22C-1CCD-PKG14-2
19
Data Sheet S15330EJ3V0DS
µPD8872
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
Type of Through-hole Device
µPD8872CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Process
Conditions
Partial heating method
Pin temperature : 300 °C or below, Heat time : 3 seconds or less (per pin)
Cautions 1.
2.
During assembly care should be taken to prevent solder or flux from contacting the plastic
cap. The optical characteristics could be degraded by such contact.
Soldering by the solder flow method may have deleterious effects on prevention of plastic
cap soiling and heat resistance. So the method cannot be guaranteed.
20
Data Sheet S15330EJ3V0DS
µPD8872
NOTES ON HANDLING THE PACKAGES
1
DUST AND DIRT PROTECTING
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
Solvents
Ethyl Alcohol
Symbol
EtOH
MeOH
IPA
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
NMP
2
MOUNTING OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
3
4
OPERATE AND STORAGE ENVIRONMENTS
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
3. Either handle bare handed or use non-chargeable gloves, clothes or material.
4. Ionized air is recommended for discharge when handling CCD image sensor.
5. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 MΩ.
21
Data Sheet S15330EJ3V0DS
µPD8872
[MEMO]
22
Data Sheet S15330EJ3V0DS
µPD8872
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
23
Data Sheet S15330EJ3V0DS
µPD8872
•
The information in this document is current as of July, 2003. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
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appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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