PSMN6R8-40HS [NEXPERIA]
N-channel 40 V, 6.8 mOhm, standard level MOSFET in LFPAK56D using TrenchMOS technologyProduction;型号: | PSMN6R8-40HS |
厂家: | Nexperia |
描述: | N-channel 40 V, 6.8 mOhm, standard level MOSFET in LFPAK56D using TrenchMOS technologyProduction |
文件: | 总12页 (文件大小:281K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PSMN6R8-40HS
N-channel 40 V, 6.8 mOhm, standard level MOSFET in
LFPAK56D using TrenchMOS technology
19 October 2022
Product data sheet
1. General description
Dual standard level N-channel MOSFET in an LFPAK56D (Dual Power-SO8) package using
TrenchMOS technology.
2. Features and benefits
•
Dual MOSFET
•
•
•
•
Repetitive avalanche rated
High reliability LFPAK56D package
Copper-clip, solder die attach
Qualified to 175 °C
3. Applications
•
•
•
•
Brushless DC motor control
DC-to-DC converters
High-performance synchronous rectification
High performance and high efficiency server power supply
4. Quick reference data
Table 1. Quick reference data
Symbol
VDS
ID
Parameter
Conditions
Min
Typ
Max
40
Unit
V
drain-source voltage
drain current
25 °C ≤ Tj ≤ 175 °C
VGS = 10 V; Tmb = 25 °C; Fig. 2
-
-
-
-
-
-
40
A
Ptot
total power dissipation Tmb = 25 °C; Fig. 1
junction temperature
-
64
W
Tj
-55
175
°C
Static characteristics FET1 and FET2
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 20 A; Tj = 25 °C;
Fig. 12
-
-
5.8
11
6.8
mΩ
mΩ
VGS = 10 V; ID = 20 A; Tj = 175 °C;
Fig. 12; Fig. 13
13.4
Dynamic characteristics FET1 and FET2
QGD
gate-drain charge
ID = 20 A; VDS = 32 V; VGS = 20 V;
Tj = 25 °C; Fig. 14; Fig. 15
-
-
9.1
-
-
nC
nC
QG(tot)
total gate charge
ID = 20 A; VDS = 32 V; VGS = 10 V;
Tj = 25 °C; Fig. 14; Fig. 15
28.9
Avalanche ruggedness FET1 and FET2
EDS(AL)S
non-repetitive drain-
source avalanche
energy
ID = 40 A; Vsup ≤ 40 V; VGS = 10 V;
Tj(init) = 25 °C; Fig. 4
[1] [2]
-
-
130
mJ
Nexperia
PSMN6R8-40HS
N-channel 40 V, 6.8 mOhm, standard level MOSFET in LFPAK56D using TrenchMOS technology
Symbol
Source-drain diode FET1 and FET2
Qr recovered charge
Parameter
Conditions
Min
Typ
Max
Unit
IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 20 V; Tj = 25 °C
-
11.3
-
nC
[1] Refer to application note AN10273 for further information
[2] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C
5. Pinning information
Table 2. Pinning information
Pin
1
Symbol
S1
Description
source1
gate1
Simplified outline
Graphic symbol
8
7
6
5
2
G1
D1
D2
D2
D1
3
S2
source2
gate2
4
G2
5
D2
drain2
6
D2
drain2
S1
G1
S2
G2
mbk725
7
D1
drain1
1
2
3
4
8
D1
drain1
LFPAK56D; Dual
LFPAK (SOT1205)
6. Ordering information
Table 3. Ordering information
Type number
Package
Name
Description
Version
PSMN6R8-40HS
LFPAK56D;
Dual LFPAK
plastic, single ended surface mounted package
(LFPAK56D); 8 leads
SOT1205
7. Marking
Table 4. Marking codes
Type number
Marking code
6R8S40H
PSMN6R8-40HS
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
Unit
drain-source voltage
drain-gate voltage
gate-source voltage
total power dissipation
drain current
25 °C ≤ Tj ≤ 175 °C
-
40
40
20
64
40
40
V
V
V
W
A
A
VDGR
VGS
25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ
DC; Tj ≤ 175 °C
-
-20
Ptot
Tmb = 25 °C; Fig. 1
-
-
-
ID
VGS = 10 V; Tmb = 25 °C; Fig. 2
VGS = 10 V; Tmb = 100 °C; Fig. 2
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PSMN6R8-40HS
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Nexperia B.V. 2022. All rights reserved
Product data sheet
19 October 2022
2 / 12
Nexperia
PSMN6R8-40HS
N-channel 40 V, 6.8 mOhm, standard level MOSFET in LFPAK56D using TrenchMOS technology
Symbol
IDM
Parameter
Conditions
Min
-
Max
276
175
175
260
Unit
A
peak drain current
storage temperature
junction temperature
pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3
Tstg
-55
-55
-
°C
°C
°C
Tj
Tsld(M)
peak soldering
temperature
Source-drain diode FET1 and FET2
IS
source current
Tmb = 25 °C
-
-
40
A
A
ISM
peak source current
pulsed; tp ≤ 10 µs; Tmb = 25 °C
276
Avalanche ruggedness FET1 and FET2
EDS(AL)S non-repetitive drain-
ID = 40 A; Vsup ≤ 40 V; VGS = 10 V;
[1] [2]
-
130
mJ
source avalanche energy Tj(init) = 25 °C; Fig. 4
[1] Refer to application note AN10273 for further information
[2] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C
03aa16
003aaj739
120
100
80
60
40
20
0
ID
(A)
P
der
(%)
80
(1)
40
0
0
50
100
150
200
0
50
100
150
200
Tmb ( C)
°
T
(°C)
mb
VGS 10 ≥ V; (1) Capped at 40 A due to package.
Fig. 2. Continuous drain current as a function of
mounting base temperature
Fig. 1. Normalized total power dissipation as a
function of mounting base temperature
003aaj738
103
ID
(A)
Limit RDSon = VDS / ID
102
t =10
p
s
µ
100
s
µ
10
1 ms
DC
1
10 ms
100 ms
10-1
10-1
1
10
102
VDS (V)
Tmb = 25 °C; IDM is a single pulse; (1) Capped at 40 A due to package.
Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
©
PSMN6R8-40HS
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Nexperia B.V. 2022. All rights reserved
Product data sheet
19 October 2022
3 / 12
Nexperia
PSMN6R8-40HS
N-channel 40 V, 6.8 mOhm, standard level MOSFET in LFPAK56D using TrenchMOS technology
003aaj673
103
I
AL
(A)
102
(1)
10
(2)
1
(3)
10-1
10-2
10-3
10-2
10-1
1
10
t
(ms)
AL
(1) single pulse, Tj = 25 °C; (2) single pulse, Tj = 150 °C; (3) repetitive.
Fig. 4. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET1 and
FET2
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance from Fig. 5
junction to mounting
base
-
-
2.36
K/W
Rth(j-a)
thermal resistance from Minimum footprint; mounted on a
-
95
-
K/W
junction to ambient
printed circuit board
003aaj748
10
Z
th(j-mb)
(K/W)
δ = 0.5
1
0.2
0.1
0.05
0.02
t
p
-1
P
10
δ =
T
single shot
t
t
p
T
-2
10
-6
-5
-4
-3
-2
-1
10
10
10
10
10
10
1
t
p
(s)
Fig. 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
©
PSMN6R8-40HS
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Nexperia B.V. 2022. All rights reserved
Product data sheet
19 October 2022
4 / 12
Nexperia
PSMN6R8-40HS
N-channel 40 V, 6.8 mOhm, standard level MOSFET in LFPAK56D using TrenchMOS technology
10. Characteristics
Table 7. Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics FET1 and FET2
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
36
40
2.4
-
-
V
V
V
-
-
VGS(th)
gate-source threshold ID = 1 mA; VDS=VGS; Tj = 25 °C; Fig. 10;
3
4
voltage
Fig. 11
ID = 1 mA; VDS=VGS; Tj = 175 °C;
Fig. 10; Fig. 11
1
-
-
-
-
V
V
ID = 1 mA; VDS=VGS; Tj = -55 °C;
Fig. 10; Fig. 11
4.5
IDSS
drain leakage current
gate leakage current
VDS = 40 V; VGS = 0 V; Tj = 175 °C
VDS = 40 V; VGS = 0 V; Tj = 25 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
-
-
-
-
-
-
500
1
µA
µA
nA
nA
mΩ
0.02
2
IGSS
100
100
6.8
2
RDSon
drain-source on-state
resistance
VGS = 10 V; ID = 20 A; Tj = 25 °C;
Fig. 12
5.8
VGS = 10 V; ID = 20 A; Tj = 175 °C;
Fig. 12; Fig. 13
-
11
13.4
mΩ
Dynamic characteristics FET1 and FET2
QG(tot)
QGS
total gate charge
gate-source charge
gate-drain charge
ID = 20 A; VDS = 32 V; VGS = 10 V;
Tj = 25 °C; Fig. 14; Fig. 15
-
-
-
28.9
7
-
-
-
nC
nC
nC
QGD
ID = 20 A; VDS = 32 V; VGS = 20 V;
Tj = 25 °C; Fig. 14; Fig. 15
9.1
Ciss
Coss
Crss
input capacitance
output capacitance
VDS = 25 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 16
-
-
-
1460 1947 pF
324
197
389
270
pF
pF
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 32 V; RL = 1.6 Ω; VGS = 10 V;
RG(ext) = 5 Ω; Tj = 25 °C
-
-
-
-
8.9
-
-
-
-
ns
ns
ns
ns
15.4
19.4
16.5
turn-off delay time
fall time
Source-drain diode FET1 and FET2
VSD
trr
source-drain voltage
IS = 10 A; VGS = 0 V; Tj = 25 °C; Fig. 17
-
-
-
0.78
20.6
11.3
1.2
V
reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
-
-
ns
nC
VDS = 20 V; Tj = 25 °C
Qr
recovered charge
©
PSMN6R8-40HS
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Nexperia B.V. 2022. All rights reserved
Product data sheet
19 October 2022
5 / 12
Nexperia
PSMN6R8-40HS
N-channel 40 V, 6.8 mOhm, standard level MOSFET in LFPAK56D using TrenchMOS technology
003aaj729
003aaj731
60
fs
(S)
50
40
g
R
(m
DSon
)
Ω
30
20
10
0
40
30
20
10
0
0
10
20
30
40
0
4
8
12
16
20
I
(A)
V
(V)
GS
D
Tj = 25 °C; VDS = 15 V
Tj = 25 °C; ID = 20 A
Fig. 6. Forward transconductance as a function of
drain current; typical values
Fig. 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values
003aaj732
003aaj730
50
250
I
6.5
5.5
I
D
D
(A)
(A)
7
6
5
40
30
20
10
0
200
V
(V) =
4.5
GS
150
100
4
T = 175
j
C
°
T = 25
j
C
°
50
0
3.5
0
1
2
3
4
0
2
4
6
8
10
V
GS
12
(V)
V
(V)
DS
Tj = 25 °C
VDS = 10 V
Fig. 8. Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig. 9. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
©
PSMN6R8-40HS
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Nexperia B.V. 2022. All rights reserved
Product data sheet
19 October 2022
6 / 12
Nexperia
PSMN6R8-40HS
N-channel 40 V, 6.8 mOhm, standard level MOSFET in LFPAK56D using TrenchMOS technology
003aah028
003aah027
-1
-2
-3
-4
-5
-6
10
5
I
V
D
(A)
GS(th)
(V)
max
10
4
3
2
1
0
typ
max
min
typ
10
10
10
10
min
0
2
4
6
-60
0
60
120
180
V
(V)
T ( C)
°
GS
j
Tj = 25 °C; VDS = 5 V
ID = 1 mA; VDS = VGS
Fig. 10. Sub-threshold drain current as a function of
gate-source voltage
Fig. 11. Gate-source threshold voltage as a function of
junction temperature
003aaj736
003aaj813
2
50
a
R
DSon
(m
)
Ω
4
4.5
1.6
40
1.2
0.8
0.4
0
30
20
10
0
V
(V) =
5
GS
5.5
6
6.5
7
10
0
10
20
30
40
50
-60 -30
0
30
60
90 120 150 180
I
(A)
T (°C)
j
D
Tj = 25 °C
Fig. 12. Drain-source on-state resistance as a function
of drain current; typical values
Fig. 13. Normalized drain-source on-state resistance
factor as a function of junction temperature
©
PSMN6R8-40HS
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Nexperia B.V. 2022. All rights reserved
Product data sheet
19 October 2022
7 / 12
Nexperia
PSMN6R8-40HS
N-channel 40 V, 6.8 mOhm, standard level MOSFET in LFPAK56D using TrenchMOS technology
003aaj733
10
V
V
DS
GS
(V)
32 V
=
14 V
8
6
4
2
0
I
D
V
DS
V
V
GS(pl)
GS(th)
V
GS
Q
GS2
Q
GS1
Q
Q
GS
GD
0
10
20
30
Q
(nC)
G
Q
G(tot)
003aaa508
Tj = 25 °C; ID = 20 A
Fig. 14. Gate charge waveform definitions
Fig. 15. Gate-source voltage as a function of gate
charge; typical values
003aaj734
003aaj735
104
40
I
S
C
(pF)
(A)
C
30
iss
103
C
C
20
oss
rss
102
T = 175 C
T = 25 C
°
j
°
j
10
0
10
10-1
1
10
102
0
0.3
0.6
0.9
V
1.2
(V)
V
(V)
SD
DS
VGS = 0 V; f = 1 MHz
VGS = 0 V
Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Source current as a function of source-drain
as a function of drain-source voltage; typical
values
voltage; typical values
©
PSMN6R8-40HS
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Nexperia B.V. 2022. All rights reserved
Product data sheet
19 October 2022
8 / 12
Nexperia
PSMN6R8-40HS
N-channel 40 V, 6.8 mOhm, standard level MOSFET in LFPAK56D using TrenchMOS technology
11. Package outline
Plastic single ended surface mounted package LFPAK56D; 8 leads
SOT1205
E
A
A
b
c
1
1
L
1
mounting
base
D
1
D
2
D
H
L
1
2
3
4
X
b
(8x)
e
c
E
1
w
A
E
2
C
A
1
θ
L
p
y
C
detail X
0
2.5
5 mm
scale
Dimensions
Unit
D
(ref)
2
(1)
(1)
(1)
E
(1)
A
A
b
b
c
c
D
D
1
E
E
e
H
L
L
L
p
w
y
θ
1
1
1
1
2
1
°
8
0
max 1.05 0.1 0.50 4.4 0.25 0.30 4.70 4.55 3.5 5.30 1.8 0.85
nom
min 1.02 0.0 0.35 4.1 0.19 0.24 4.45 4.35 3.4 4.95 1.6 0.60
6.2 1.3 0.55 0.85
5.9 0.8 0.30 0.40
mm
1.27
0.25 0.1
°
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
sot1205_po
Issue date
References
Outline
version
European
projection
IEC
JEDEC
JEITA
14-08-21
14-10-28
SOT1205
Fig. 18. Package outline LFPAK56D; Dual LFPAK (SOT1205)
©
PSMN6R8-40HS
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Nexperia B.V. 2022. All rights reserved
Product data sheet
19 October 2022
9 / 12
Nexperia
PSMN6R8-40HS
N-channel 40 V, 6.8 mOhm, standard level MOSFET in LFPAK56D using TrenchMOS technology
12. Soldering
Footprint information for reflow soldering of LFPAK56D package
SOT1205
5.85
0.57
0.57
0.7
1.97
1.27
0.65
0.025
1.9
3.325
3.175
3.2
2.0
1.275
0.8
1.0
1.875
2.1
2.7
3.85
3.975
0.025
1.1
1.15
0.65
1.27
1.44
0.7
1.1
solder land
solder land plus solder paste
solder paste deposit
occupied area
14-07-28
solder resist
Dimensions in mm
sot1205_fr
Issue date
20-04-20
Fig. 19. Reflow soldering footprint for LFPAK56D; Dual LFPAK (SOT1205)
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PSMN6R8-40HS
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Nexperia B.V. 2022. All rights reserved
Product data sheet
19 October 2022
10 / 12
Nexperia
PSMN6R8-40HS
N-channel 40 V, 6.8 mOhm, standard level MOSFET in LFPAK56D using TrenchMOS technology
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
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13. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
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Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
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and products using Nexperia products, and Nexperia accepts no liability for
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Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
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Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
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Suitability for use — Nexperia products are not designed, authorized or
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©
PSMN6R8-40HS
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
19 October 2022
11 / 12
Nexperia
PSMN6R8-40HS
N-channel 40 V, 6.8 mOhm, standard level MOSFET in LFPAK56D using TrenchMOS technology
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Quick reference data....................................................1
5. Pinning information......................................................2
6. Ordering information....................................................2
7. Marking..........................................................................2
8. Limiting values............................................................. 2
9. Thermal characteristics............................................... 4
10. Characteristics............................................................5
11. Package outline.......................................................... 9
12. Soldering................................................................... 10
13. Legal information......................................................11
© Nexperia B.V. 2022. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 19 October 2022
©
PSMN6R8-40HS
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
19 October 2022
12 / 12
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