PSMN7R0-100BS_技术文档

PSMN7R0-100BS

AK

D2P

N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK.

Rev. 2 — 2 March 2012

Objective data sheet

1. Product profile

1.1 General description

Standard level N-channel MOSFET in D2PAK package qualified to 175C. This product is

designed and qualified for use in a wide range of industrial, communications and domestic

equipment.

1.2 Features and benefits

 High efficiency due to low switching

 Suitable for standard level gate drive

and conduction losses

1.3 Applications

 DC-to-DC converters

 Load switching

 Motor control

 Server power supplies

1.4 Quick reference data

Table 1.

Symbol

V_DS

Quick reference data

Parameter

Conditions

Min

Typ

Max

100

269

175

Unit

V

drain-source voltage

drain current

T_j≥ 25 °C; T_j≤ 175 °C

T_mb= 25 °C; V_GS= 10 V; see Figure 1

-

[1]

I_D

-

A

P_tot

total power dissipation T_mb= 25 °C; see Figure 2

junction temperature

-

W

T_j

-55

°C

Static characteristics

R_DSondrain-source on-state

resistance

Dynamic characteristics

V_GS= 10 V; I_D= 15 A; T_j= 100 °C; see Figure 12

V_GS= 10 V; I_D= 15 A; T_j= 25 °C; see Figure 13

-

12

mΩ

5.4

6.8

Q_GD

gate-drain charge

V_GS= 10 V; I_D= 25 A; V_DS= 50 V;

see Figure 15; see Figure 14

-

36

-

nC

Q_G(tot)

total gate charge

V_GS= 10 V; I_D= 25 A; V_DS= 50 V;

see Figure 14; see Figure 15

125

Avalanche ruggedness

E_DS(AL)S

non-repetitive

drain-source

V_GS= 10 V; T_j(init)= 25 °C; I_D= 100 A;

V_sup= 100 V; unclamped; R_GS= 50 Ω

-

315

mJ

avalanche energy

[1] Continuous current is limited by package.

PSMN7R0-100BS

NXP Semiconductors

N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK.

2. Pinning information

Table 2.

Pinning information

Symbol Description

1

Simplified outline

Graphic symbol

G

D

S

D

gate

drain^[1]

mb

D

S

2

3

source

G

mb

mounting base; connected to drain

mbb076

2

1

3

SOT404 (D2PAK)

[1] It is not possible to make connection to pin 2.

3. Ordering information

Table 3.

Ordering information

Type number

Package

Name

Description

Version

PSMN7R0-100BS D2PAK

plastic single-ended surface-mounted package (D2PAK); 3 leads (one

lead cropped)

SOT404

4. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DS

Parameter

Conditions

Min

Max

100

20

Unit

V

drain-source voltage

drain-gate voltage

gate-source voltage

drain current

T_j≥ 25 °C; T_j≤ 175 °C

T_j≤ 175 °C; T_j≥ 25 °C; R_GS= 20 kΩ

-

V_DGR

V_GS

-

V

-20

V

I_D

V_GS= 10 V; T_mb= 100 °C; see Figure 1

V_GS= 10 V; T_mb= 25 °C; see Figure 1

pulsed; t_p≤ 10 µs; T_mb= 25 °C; see Figure 3

T_mb= 25 °C; see Figure 2

-

85

A

[1]

-

100

475

269

175

260

A

I_DM

peak drain current

-

A

P_tot

T_stg

T_j

total power dissipation

storage temperature

junction temperature

peak soldering temperature

-

W

°C

-55

-

T_sld(M)

Source-drain diode

[1]

I_S

source current

peak source current

T_mb= 25 °C

-

100

475

A

I_SM

pulsed; t_p≤ 10 µs; T_mb= 25 °C

Avalanche ruggedness

E_DS(AL)Snon-repetitive drain-source V_GS= 10 V; T_j(init)= 25 °C; I_D= 100 A;

-

315

mJ

avalanche energy

V_sup= 100 V; unclamped; R_GS= 50 Ω

[1] Continuous current is limited by package.

PSMN7R0-100BS

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 2 — 2 March 2012

2 of 14

PSMN7R0-100BS

NXP Semiconductors

N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK.

03aa16

003aad558

120

150

I_D

P

der

(A)

(%)

80

100

(1)

40

50

0

50

100

150

200

0

50

100

150

T_mb( C)

200

°

T

(°C)

mb

Fig 1. Continuous drain current as a function of

mounting base temperature

Fig 2. Normalized total power dissipation as a

function of mounting base temperature

003aad559

10³

I

D

Limit R

= V / I

DS D

DSon

(A)

t

= 10 s

μ

p

10²

100

s

μ

10

1

DC

1 ms

10 ms

100 ms

10^-1

1

10

10²

10³

V

(V)

DS

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

PSMN7R0-100BS

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Objective data sheet

Rev. 2 — 2 March 2012

3 of 14

PSMN7R0-100BS

NXP Semiconductors

N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK.

5. Thermal characteristics

Table 5.

Symbol

R_th(j-mb)

Thermal characteristics

Parameter

Conditions

Min

Typ

Max

Unit

thermal resistance from

junction to mounting base

see Figure 4

-

0.3

0.56

K/W

R_th(j-a)

thermal resistance from

junction to ambient

Minimum footprint; mounted on

a printed circuit board

-

60

-

K/W

003aad560

1

Z

th (j-mb)

(K/W)

= 0.5

δ

10^-1

10^-2

10^-3

10^-4

0.2

0.1

0.05

0.02

t_p

T

P

δ =

single shot

t

t_p

T

10^-6

10^-5

10^-4

10^-3

10^-2

10^-1

1

10

t (s)

p

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

PSMN7R0-100BS

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Objective data sheet

Rev. 2 — 2 March 2012

4 of 14

PSMN7R0-100BS

NXP Semiconductors

N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK.

6. Characteristics

Table 6.

Symbol

Characteristics

Parameter

Conditions

Min

Typ

Max

Unit

Static characteristics

V_(BR)DSSdrain-source

breakdown voltage

I_D= 0.25 mA; V_GS= 0 V; T_j= -55 °C

I_D= 0.25 mA; V_GS= 0 V; T_j= 25 °C

90

100

1

-

V

V_GS(th)

gate-source threshold I_D= 1 mA; V_DS= V_GS; T_j= 175 °C;

voltage

see Figure 10

I_D= 1 mA; V_DS= V_GS; T_j= 25 °C;

see Figure 11; see Figure 10

2

-

3

-

4

V

I_D= 1 mA; V_DS= V_GS; T_j= -55 °C;

see Figure 10

4.6

I_DSS

drain leakage current

gate leakage current

V_DS= 100 V; V_GS= 0 V; T_j= 125 °C

V_DS= 100 V; V_GS= 0 V; T_j= 25 °C

V_GS= 20 V; V_DS= 0 V; T_j= 25 °C

V_GS= -20 V; V_DS= 0 V; T_j= 25 °C

-

150

5

µA

nA

mΩ

0.08

10

-

I_GSS

100

12

R_DSon

drain-source on-state

resistance

V_GS= 10 V; I_D= 15 A; T_j= 100 °C;

see Figure 12

V_GS= 10 V; I_D= 15 A; T_j= 175 °C;

see Figure 12

-

15

19

6.8

-

mΩ

Ω

V_GS= 10 V; I_D= 15 A; T_j= 25 °C;

5.4

0.74

see Figure 13

R_G

internal gate resistance f = 1 MHz

(AC)

Dynamic characteristics

Q_G(tot)

total gate charge

I_D= 25 A; V_DS= 50 V; V_GS= 10 V;

see Figure 14; see Figure 15

-

125

-

nC

I_D= 0 A; V_DS= 0 V; V_GS= 10 V

-

100

28

-

nC

Q_GS

gate-source charge

I_D= 25 A; V_DS= 50 V; V_GS= 10 V;

see Figure 15; see Figure 14

Q_GS(th)

Q_GS(th-pl)

Q_GD

pre-threshold

gate-source charge

I_D= 25 A; V_DS= 50 V; V_GS= 10 V;

see Figure 15

-

19.4

9

-

nC

V

post-threshold

gate-source charge

gate-drain charge

I_D= 25 A; V_DS= 50 V; V_GS= 10 V;

see Figure 15; see Figure 14

36

V_GS(pl)

gate-source plateau

voltage

V_DS= 50 V; see Figure 15;

see Figure 14

4.3

C_iss

C_oss

C_rss

input capacitance

output capacitance

V_DS= 50 V; V_GS= 0 V; f = 1 MHz;

T_j= 25 °C; see Figure 16

-

6686

438

-

pF

reverse transfer

capacitance

272

PSMN7R0-100BS

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Objective data sheet

Rev. 2 — 2 March 2012

5 of 14

PSMN7R0-100BS

NXP Semiconductors

N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK.

Table 6.

Symbol

t_d(on)

t_r

Characteristics …continued

Parameter

Conditions

Min

Typ

Max

Unit

ns

turn-on delay time

rise time

V_DS= 50 V; R_L= 2 Ω; V_GS= 10 V;

R_G(ext)= 4.7 Ω; T_j= 25 °C

-

34.6

45.6

103.9

49.5

-

ns

t_d(off)

t_f

turn-off delay time

fall time

ns

Source-drain diode

V_SD

source-drain voltage

I_S= 25 A; V_GS= 0 V; T_j= 25 °C;

see Figure 17

-

0.8

1.2

V

t_rr

reverse recovery time I_S= 25 A; dI_S/dt = 100 A/µs; V_GS= 0 V;

-

64

-

ns

V_DS= 50 V

Q_r

recovered charge

167

nC

003aad562

003aad566

300

I_D

(A)

240

12000

20

6

5.5

C

(pF)

10

C_{is s}

10000

8000

6000

4000

2000

5

180

120

60

C_{rs s}

4.5

V_GS(V) = 4

0

1

2

3

4

0

5

10

15

20

_GS(V)

V

_DS(V)

V

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values

Fig 6. Input and reverse transfer capacitances as a

function of gate-source voltage; typical values

PSMN7R0-100BS

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Objective data sheet

Rev. 2 — 2 March 2012

6 of 14

PSMN7R0-100BS

NXP Semiconductors

N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK.

003aad572

003aad568

240

60

I_D

g_fs

(A)

(S)

180

120

60

45

30

T = 175 C

°

j

15

0

T = 25 C

°

j

0

50

100

150

200

250

_D(A)

0

2

4

6

I

V

_GS(V)

Fig 7. Forward transconductance as a function of

drain current; typical values

Fig 8. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

003aad571

003aad280

5

40

V

GS(th)

(V)

R_DSon

(m

)

Ω

4

3

2

1

0

max

30

20

10

0

typ

min

−60

0

60

120

180

0

5

10

15

20

V

_GS(V)

T (°C)

j

Fig 9. Drain-source on-state resistance as a function

of gate-source voltage; typical values

Fig 10. Gate-source threshold voltage as a function of

junction temperature

PSMN7R0-100BS

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 2 — 2 March 2012

7 of 14

PSMN7R0-100BS

NXP Semiconductors

N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK.

03aa35

003aad774

−1

10

3.2

I

D

(A)

a

min

typ

max

−2

−3

−4

−5

−6

10

2.4

10

1.6

0.8

0

-60

0

60

120

180

0

2

4

6

T (°C)

j

V

GS

(V)

Fig 11. Sub-threshold drain current as a function of

gate-source voltage

Fig 12. Normalized drain-source on-state resistance

factor as a function of junction temperature

003aad563

003aad569

10

20

V_GS(V) = 4.5

V

GS

R_DSon

(m

(V)

80 V

)

Ω

8

15

10

5

20 V

6

4

2

0

V

= 50 V

DS

5

6

10

80

20

0

50

100

150

0

20

40

60

100

_D(A)

Q

(nC)

I

G

Fig 13. Drain-source on-state resistance as a function

of drain current; typical values

Fig 14. Gate-source voltage as a function of gate

charge; typical values

PSMN7R0-100BS

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Objective data sheet

Rev. 2 — 2 March 2012

8 of 14

PSMN7R0-100BS

NXP Semiconductors

N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK.

003aad567

10⁴

C_iss

C

V

DS

(pF)

I

D

10³

V

GS(pl)

C_oss

V

GS(th)

GS

V

C_rss

Q

GS1

GS2

Q

GD

GS

10²

10^-1

Q

G(tot)

1

10

10²

V

(V)

003aaa508

DS

Fig 15. Gate charge waveform definitions

Fig 16. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical

values

003aad570

100

I_S

(A)

80

60

40

20

T = 175 C

°

j

25 C

°

0

0.3

0.6

0.9

1.2

V

_SD(V)

Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values

PSMN7R0-100BS

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Objective data sheet

Rev. 2 — 2 March 2012

9 of 14

PSMN7R0-100BS

NXP Semiconductors

N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK.

7. Package outline

Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)

SOT404

A

E

1

mounting

base

D

1

D

H

D

2

L

p

1

3

c

b

e

Q

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

D

E

A

b

UNIT

c

D

e

L

H

Q

1

p

D

max.

4.50

4.10

1.40

1.27

0.85

0.60

0.64

0.46

1.60

1.20

10.30

9.70

2.90 15.80 2.60

2.10 14.80 2.20

mm

11

2.54

REFERENCES

JEDEC JEITA

EUROPEAN

PROJECTION

OUTLINE

VERSION

ISSUE DATE

IEC

05-02-11

06-03-16

SOT404

Fig 18. Package outline SOT404 (D2PAK)

PSMN7R0-100BS

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Objective data sheet

Rev. 2 — 2 March 2012

10 of 14

PSMN7R0-100BS

NXP Semiconductors

N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK.

8. Revision history

Table 7.

Document ID

PSMN7R0-100BS v.2 20120302

Revision history

Release date

Data sheet status

Change notice

Supersedes

Objective data sheet

-

PSMN7R0-100BS v.1

Modifications:

• Various changes to content.

PSMN7R0-100BS v.1 20111025

Objective data sheet

-

PSMN7R0-100BS

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Objective data sheet

Rev. 2 — 2 March 2012

11 of 14

PSMN7R0-100BS

NXP Semiconductors

N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK.

9. Legal information

9.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term 'short data sheet' is explained in section "Definitions".

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URLhttp://www.nxp.com.

Right to make changes— NXP Semiconductors reserves the right to make

9.2 Definitions

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Preview— The document is a preview version only. The document is still

subject to formal approval, which may result in modifications or additions.

NXP Semiconductors does not give any representations or warranties as to

the accuracy or completeness of information included herein and shall have

no liability for the consequences of use of such information.

Suitability for use— NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft— The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet— A short data sheet is an extract from a full data sheet with

the same product type number(s) and title. A short data sheet is intended for

quick reference only and should not be relied upon to contain detailed and full

information. For detailed and full information see the relevant full data sheet,

which is available on request via the local NXP Semiconductors sales office.

In case of any inconsistency or conflict with the short data sheet, the full data

sheet shall prevail.

Quick reference data— The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Applications— Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Product specification— The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

9.3 Disclaimers

Limited warranty and liability— Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Limiting values— Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with theTerms and conditions of commercial saleof NXP Semiconductors.

PSMN7R0-100BS

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Objective data sheet

Rev. 2 — 2 March 2012

12 of 14

PSMN7R0-100BS

NXP Semiconductors

N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK.

Terms and conditions of commercial sale— NXP Semiconductors

In the event that customer uses the product for design-in and use in

products are sold subject to the general terms and conditions of commercial

sale, as published athttp://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

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liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

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Translations— A non-English (translated) version of a document is for

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between the translated and English versions.

Export control— This document as well as the item(s) described herein may

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Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Non-automotive qualified products— Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

Adelante,Bitport,Bitsound,CoolFlux,CoReUse,DESFire,EZ-HV,FabKey,G

reenChip,HiPerSmart,HITAG,I²C-buslogo,ICODE,I-CODE,ITEC,Labelution

,MIFARE,MIFARE Plus,MIFARE Ultralight,MoReUse,QLPAK,Silicon

Tuner,SiliconMAX,SmartXA,STARplug,TOPFET,TrenchMOS,TriMediaand

UCODE— are trademarks of NXP B.V.

non-automotive qualified products in automotive equipment or applications.

HD RadioandHD Radiologo — are trademarks of iBiquity Digital Corporation.

10. Contact information

For more information, please visit:http://www.nxp.com

For sales office addresses, please send an email to:salesaddresses@nxp.com

PSMN7R0-100BS

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 2 — 2 March 2012

13 of 14

PSMN7R0-100BS

NXP Semiconductors

N-channel 100V 6.8 mΩ standard level MOSFET in D2PAK.

11. Contents

1

Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General description . . . . . . . . . . . . . . . . . . . . . .1

Features and benefits. . . . . . . . . . . . . . . . . . . . .1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Quick reference data . . . . . . . . . . . . . . . . . . . . .1

1.1

1.2

1.3

1.4

2

3

4

5

6

7

8

Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

Ordering information. . . . . . . . . . . . . . . . . . . . . .2

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2

Thermal characteristics . . . . . . . . . . . . . . . . . . .4

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5

Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10

Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11

9

Legal information. . . . . . . . . . . . . . . . . . . . . . . .12

Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13

9.1

9.2

9.3

9.4

10

Contact information. . . . . . . . . . . . . . . . . . . . . .13

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 2 March 2012

Document identifier: PSMN7R0-100BS


型号：	PSMN7R0-100BS
厂家：	NXP
描述：	N-channel 100V 6.8 mÎ© standard level MOSFET in D2PAK. N沟道100V 6.8英里© D2PAK在标准水平的MOSFET 。晶体晶体管功率场效应晶体管开关脉冲 PC
文件：	总14页 (文件大小：229K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PSMN7R0-100BS [NXP]

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