PHD71NQ03LT,118 [NXP]
N-channel TrenchMOS logic level FET DPAK 3-Pin;
| 型号： | PHD71NQ03LT,118 |
| 厂家： | 
NXP |
| 描述： | N-channel TrenchMOS logic level FET DPAK 3-Pin 开关 脉冲 晶体管 |
| 文件： | 总13页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PHD71NQ03LT
N-channel TrenchMOS logic level FET
Rev. 02 — 9 March 2010
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Simple gate drive required due to low
Suitable for logic level gate drive
gate charge
sources
1.3 Applications
DC-to-DC convertors
Switched-mode power supplies
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min
Typ
Max Unit
VDS
ID
drain-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
-
-
30
75
V
A
Tmb = 25 °C; VGS = 10 V;
see Figure 1 and 3
Ptot
total power dissipation Tmb = 25 °C; see Figure 2
-
-
-
120
-
W
Dynamic characteristics
QGD gate-drain charge
VGS = 5 V; ID = 50 A;
VDS = 15 V; Tj = 25 °C;
see Figure 11
4.6
nC
Static characteristics
RDSon drain-source on-state VGS = 10 V; ID = 25 A;
resistance Tj = 25 °C; see Figure 9
-
8
10
mΩ
PHD71NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pinning information
Pin
1
Symbol Description
Simplified outline
Graphic symbol
G
D
S
D
gate
mb
D
[1]
2
drain
source
3
G
mb
mounting base; connected to
drain
mbb076
S
2
1
3
SOT428 (DPAK)
[1] It is not possible to make a connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PHD71NQ03LT
DPAK
plastic single-ended surface-mounted package (DPAK); 3 leads (one
lead cropped)
SOT428
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
Unit
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 175 °C
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
-
30
V
VDGR
VGS
-
30
V
-20
-
20
V
ID
VGS = 10 V; Tmb = 100 °C; see Figure 1
VGS = 10 V; Tmb = 25 °C; see Figure 1 and 3
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3
57.5
75
A
-
A
IDM
Ptot
Tstg
Tj
peak drain current
-
240
120
175
175
25
A
total power dissipation Tmb = 25 °C; see Figure 2
storage temperature
-
W
°C
°C
V
-55
-55
-25
junction temperature
VGSM
peak gate-source
voltage
pulsed; δ = 25 %; tp ≤ 50 µs
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
75
A
A
ISM
tp ≤ 10 µs; pulsed; Tmb = 25 °C
57.7
PHD71NQ03LT_2
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2010
2 of 13
PHD71NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
03aa16
03ai74
120
120
P
(%)
I
der
der
(%)
80
80
40
40
0
0
0
50
100
150
200
0
50
100
150
200
°
T
( C)
T
mb
(°C)
mb
Fig 1. Normalized continuous drain current as a
function of mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
03ai76
3
10
I
D
Limit R
= V / I
DS D
DSon
(A)
t
= 10 μs
p
2
10
100 μs
DC
1 ms
10
10 ms
1
2
1
10
10
V
DS
(V)
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHD71NQ03LT_2
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2010
3 of 13
PHD71NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
Min
Typ
Max
Unit
thermal resistance from junction to
mounting base
see Figure 4
-
-
1.25
K/W
Rth(j-a)
thermal resistance from junction to
ambient
mounted on a printed-circuit
board; minimum footprint
-
75
-
K/W
03ai75
10
Z
th(j-mb)
(K/W)
1
δ = 0.5
0.2
t
0.1
p
P
δ =
10-1
T
0.05
0.02
t
t
single pulse
p
T
t
10-2
−5
−4
−3
−2
−1
10
10
10
10
10
(s)
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PHD71NQ03LT_2
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2010
4 of 13
PHD71NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
27
30
0.6
-
-
-
V
-
-
V
VGS(th)
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 8
voltage
-
-
V
ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 8
-
2.9
2.5
1
V
ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 8
1
1.9
0.05
-
V
IDSS
drain leakage current
gate leakage current
VDS = 30 V; VGS = 0 V; Tj = 25 °C
VDS = 30 V; VGS = 0 V; Tj = 175 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
-
µA
µA
nA
nA
mΩ
-
500
100
100
27.4
IGSS
-
10
10
21.6
-
RDSon
drain-source on-state
resistance
VGS = 5 V; ID = 25 A; Tj = 175 °C; see Figure 9
and 10
-
VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 9
-
-
8
10
mΩ
mΩ
VGS = 5 V; ID = 25 A; Tj = 25 °C; see Figure 9
and 10
12
15.2
Dynamic characteristics
QG(tot)
QGS
QGD
Ciss
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
ID = 50 A; VDS = 15 V; VGS = 5 V; Tj = 25 °C;
see Figure 11
-
-
-
-
-
-
13.2
5.3
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
4.6
VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C;
see Figure 12
1220
330
140
Coss
Crss
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 15 V; RL = 0.6 Ω; VGS = 4.5 V;
RG(ext) = 5.6 Ω; Tj = 25 °C; ID = 25 A
-
-
-
-
15
-
-
-
-
ns
ns
ns
ns
150
13.5
18
turn-off delay time
fall time
Source-drain diode
VSD
trr
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 13
-
-
-
0.9
29
20
1.2
V
reverse recovery time
recovered charge
IS = 10 A; dIS/dt = -100 A/µs; VGS = 0 V;
VDS = 25 V; Tj = 25 °C
-
-
ns
nC
Qr
PHD71NQ03LT_2
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2010
5 of 13
PHD71NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
03ai77
03ai79
80
80
60
40
20
0
T = 25 °C
V
DS
> I × R
j
D
DSon
10 V 7 V 6 V 5.5 V
I
I
D
(A)
D
(A)
5 V
60
4.5 V
40
20
0
4 V
3.5 V
= 3 V
175 °C
T = °C
V
j
GS
0
2
4
6
0
0.2
0.4
0.6
0.8
1
V
GS
(V)
V
(V)
DS
Fig 6. Transfer characteristics: drain current as a
function of gate-source voltage; typical values
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values
03ai28
03ai29
10-1
3.2
ID
(A)
10-2
10-3
VGS(th)
(V)
max
2.4
typ
min
typ
max
1.6
10-4
10-5
10-6
min
0.8
0
-60
0
0.8
1.6
2.4
3.2
0
60
120
180
VGS(V)
Tj (°C)
Fig 7. Sub-threshold drain current as a function of
gate-source voltage
Fig 8. Gate-source threshold voltage as a function of
junction temperature
PHD71NQ03LT_2
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2010
6 of 13
PHD71NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
03ai78
03af18
20
2
T = 25 °C
j
V
GS
= 4.5 V
R
DSon
a
(mΩ)
15
1.5
1
5 V
5.5 V
6 V
7 V
10
5
10 V
0.5
0
0
0
20
40
60
80
-60
0
60
120
180
Tj (°C)
I
(A)
D
Fig 9. Drain-source on-state resistance as a function
of drain current; typical values
Fig 10. Normalized drain-source on-state resistance
factor as a function of junction temperature
03ai82
03ai81
4
10
10
I
D
= 50 A
V
(V)
GS
T = 25 °C
DD
j
V
= 15 V
8
6
4
2
0
C
(pF)
C
iss
3
10
C
C
oss
rss
2
10
10
−1
2
1
10
10
0
5
10
15
20
Q
25
(nC)
V
(V)
DS
G
Fig 11. Gate-source voltage as a function of gate
charge; typical values
Fig 12. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
PHD71NQ03LT_2
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2010
7 of 13
PHD71NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
03ai80
80
V
GS
= 0 V
I
S
(A)
60
40
20
0
T = 25 °C
175 °C
j
0
0.3
0.6
0.9
1.2
V
(V)
SD
Fig 13. Source current as a function of source-drain voltage; typical values
PHD71NQ03LT_2
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2010
8 of 13
PHD71NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
7. Package outline
Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped)
SOT428
y
E
A
A
A
1
b
2
E
1
mounting
base
D
2
D
1
H
D
2
L
L
2
L
1
1
3
b
1
b
M
c
w
A
e
e
1
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
y
max
D
min
E
min
L
1
min
2
1
UNIT
A
A
1
b
b
b
c
D
E
e
e
1
H
D
L
L
2
w
1
2
1
2.38
2.22
0.93
0.46
0.89
0.71
1.1
0.9
5.46
5.00
0.56
0.20
6.22
5.98
6.73
6.47
10.4
9.6
2.95
2.55
0.9
0.5
4.0
4.45
0.5
mm
2.285 4.57
0.2
0.2
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
JEDEC
JEITA
06-02-14
06-03-16
SOT428
SC-63
TO-252
Fig 14. Package outline SOT428 (DPAK)
PHD71NQ03LT_2
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2010
9 of 13
PHD71NQ03LT
NXP Semiconductors
N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
PHD71NQ03LT_2
Modifications:
Release date Data sheet status
20100309 Product data sheet
Change notice
Supersedes
-
PHP_PHB_PHD71NQ03LT-01
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Type number PHD71NQ03LT separated from data sheet
PHP_PHB_PHD71NQ03LT-01.
PHP_PHB_PHD71NQ03LT-01 20020625
Product data
-
-
PHD71NQ03LT_2
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2010
10 of 13
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NXP Semiconductors
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
Document status [1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
Suitability for use — NXP Semiconductors products are not designed,
9.2 Definitions
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
9.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PHD71NQ03LT_2
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2010
11 of 13
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NXP Semiconductors
N-channel TrenchMOS logic level FET
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
9.4 Trademarks
non-automotive qualified products in automotive equipment or applications.
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PHD71NQ03LT_2
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© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 9 March 2010
12 of 13
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NXP Semiconductors
N-channel TrenchMOS logic level FET
11. Contents
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1
1.2
1.3
1.4
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits. . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
Ordering information. . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
Thermal characteristics . . . . . . . . . . . . . . . . . . .4
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9
Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . .11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12
9.1
9.2
9.3
9.4
10
Contact information. . . . . . . . . . . . . . . . . . . . . .12
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 March 2010
Document identifier: PHD71NQ03LT_2
相关型号：
PHD78NQ03LT/T3
TRANSISTOR 75 A, 25 V, 0.0135 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252, PLASTIC, SC-63, DPAK-3, FET General Purpose Power
NXP
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