TEA5760UK/N1/S21,0_技术文档

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TEA5760UK

Single chip FM stereo radio

Rev. 01 — 14 December 2006

Product data sheet

1. General description

The TEA5760UK is a single chip electronically tuned FM stereo radio for low voltage

applications with fully integrated Intermediate Frequency (IF) selectivity and

demodulation.

The radio is completely adjustment free and only requires a minimum of small and low

cost external components.

The TEA5760UK does not meet all of the requirements from EN55020, a trade off was

done to make possible the previously stated features.

The TEA5760UK application software is compatible to the TEA5761UK software to enable

easy design in for customers.

2. Features

I High sensitivity due to integrated low noise Radio Frequency (RF) input ampliﬁer

I FM mixer for conversion of the US/Europe (87.5 MHz to 108 MHz) and Japanese FM

band (76 MHz to 90 MHz) to IF

I Preset tuning to receive Japanese TV audio up to 108 MHz and raster 100 kHz

I Autonomous search tuning, 100 kHz grid

I RF Automatic Gain Control (AGC) circuit

I LC tuner oscillator operating with one low cost chip inductor (external varicap not

required)

I Fully integrated FM IF selectivity

I Fully integrated FM demodulator

I 32.768 kHz external reference frequency

I Phase-Locked Loop (PLL) synthesizer tuning system

I IF counter; 7-bit output via control interface

I Level detector, 4-bit level information output via the control interface

I Soft mute, signal level dependent mute function

I Signal level dependent mono/stereo blend, Stereo Noise Cancelling (SNC)

I Soft mute and SNC can be switched off via control interface

I Adjustment free stereo decoder

I I²C-bus interface

I Standby mode

I One software programmable port

I Interrupt ﬂag

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

3. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Version

TEA5760UK

WLCSP25 wafer level chip-size package; 25 bumps; die 3 × 2.8 × 0.6 mm TEA5760UK

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

2 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

5. Pinning information

5.1 Pinning

bump A1

index area

TEA5760UK

1

2

3

4

5

6

A

B

C

D

E

001aaf252

Transparent top view

Fig 2. Ball conﬁguration TEA5760UK

5.2 Pin description

Table 2.

Pin description

Symbol

CPOUT

LOOPSW

LO1

A1

A2

A3

A4

A5

A6

B1

B2

B5

B6

C1

C2

C5

C6

D1

D2

D3

D5

D6

E1

E2

E3

Description

charge pump output of synthesizer PLL

switch output of synthesizer PLL loop ﬁlter

local oscillator coil connection

Voltage Controlled Oscillator (VCO) supply voltage

analog supply voltage

LO2

V_CC(VCO)

V_CCA

SWPORT

INTX

software programmable port

interrupt

GND(A1)

RFIN1

analog ground 1

RF input 1

FREQIN

BUSEN

GND(RF)

RFIN2

input for 32.768 kHz reference frequency

bus enable input for control interface

RF ground

RF input 2

V_CCD

digital supply voltage

GND(D1)

GND(D2)

GND(A2)

TMUTE

DATA

digital ground 1

digital ground 2

analog ground 2

time constant for soft mute

control interface data line input/output

control interface clock line input

digital reference voltage for control interface

CLOCK

VREFDIG

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

4 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

Table 2.

Pin description …continued

Symbol

MPXOUT

VAFL

E4

E5

E6

Description

multiplex signal (MPX) output pin

left audio output

VAFR

right audio output

6. Functional description

6.1 Low noise RF ampliﬁer

The Low Noise Ampliﬁer (LNA) input impedance together with the LC RF input circuit

deﬁnes an FM band ﬁlter. The gain of the LNA is controlled by the RF AGC circuit to

prevent overdrive of the subsequent circuits.

6.2 FM mixer

The FM quadrature mixer converts the received RF (76 MHz to 108 MHz) to an IF of

225 kHz. Downconversion is achieved by multiplying the RF with the Local Oscillator (LO)

frequency. Image frequency suppression is achieved by using quadrature signal

processing.

6.3 VCO

The LC tuned VCO provides the LO signal for the FM quadrature mixer. The VCO

frequency range is 150 MHz to 217 MHz. No external varactor is required.

6.4 Reference frequency

An external 32.768 kHz reference frequency is used as the system clock. The reference

frequency speciﬁcations are given in Section 10.

The reference frequency is used for:

• Synthesizer PLL reference frequency

• Timing for the IF counter

• Adjustment of the frequency of the stereo decoder VCO

• Auto alignment of the selectivity as well as the demodulator ﬁlters

6.5 PLL tuning system

The PLL synthesizer tuning system is designed to operate with a 32.768 kHz reference

frequency. A 14-bit word is used to tune the radio (see Table 11 and Table 12). Calculation

of this 14-bit word is as follows.

[4 × ( f _RF+ f _IF)]

Formula for high-side injection: N_DEC

Formula for low-side injection: N_DEC

=

------------------------------------------

f _ref

[4 × ( f _RF– f _IF)]

=

------------------------------------------

f _ref

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

5 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

where:

N_DEC= decimal value of PLL word

f_RF= wanted tuning frequency (Hz)

f_IF= intermediate frequency (Hz): 225 kHz

f_ref= reference frequency (Hz): 32.768 kHz

Example for receiving a channel at 100.1 MHz:

[4 × (100.e6 + 225e3)]

N_DEC

=

= 12246.704

---------------------------------------------------------

32768

The result must always be rounded to the lowest integer value. If rounded down to the

lowest integer value of N_DEC= 12246, the PLL word becomes 2FD6h.

Via the control interface this value can be written to register FRQSET and the

TEA5760UK will then start an autonomous search beginning at this frequency or go to a

preset channel at this frequency. When the application is built according the application

diagram (see Figure 11) and with the preferred components, the tuning system will settle

to the new frequency within 40 ms.

The PLL is triggered by writing one of the following bytes: FRQSETMSB, FRQSETLSB,

TNCTRL1, TNCTRL2, TESTBITS and TESTMODE.

Accurate validation of the PLL locking onto the new frequency can take 40 ms. Bit LD in

register TUNCHK (see Table 18) is set when a lock is detected.

6.6 Band limits

The TEA5760UK can be switched to the Japanese FM band or the US/Europe FM band.

With bit BLIM in register TNCTRL (see Table 13) set to logic 0 it enables the US/European

FM band (87.5 MHz to 108 MHz), while setting bit BLIM to logic 1 enables the Japanese

FM band (76 MHz to 90 MHz).

6.7 RF AGC

The RF AGC prevents overloading and limits the amount of intermodulation products

created by strong adjacent channels. The default setting for the RF AGC is on and it can

be turned off via the control interface. The TEA5760UK also has an inband AGC to

prevent overloading by the wanted channel itself. The inband AGC is always on.

6.8 IF ﬁlter

Fully integrated IF ﬁlter with a center frequency of 225 kHz.

6.9 FM demodulator

Fully integrated FM quadrature demodulator.

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

6 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

6.10 IF counter

The received RF signal is converted down to a 225 kHz IF. The IF is measured by means

of a frequency counter. A correct IF frequency measurement result indicates that the radio

is tuned to a valid channel and not to an image or a channel with high interference. The

7-bit IF counter output can be read via the control interface. The IF counter is active when

the tuning algorithm is active (see Figure 3) and the outcome can be read via the control

interface. It activates a ﬂag if the IF count result lies outside a predeﬁned window. The IF

count period can be set to 1.953 ms or 15.625 ms with bit IFCTC in register TNCTRL (see

Table 13).

6.11 Level voltage generator and analog-to-digital converter

The level voltage reﬂects the received ﬁeld strength at the antenna. The analog level

voltage is digitized to 4 bits by the level Analog-to-Digital Converter (ADC). During a

search or preset tuning cycle the level ADC is activated and the recorded level ADC

information is stored in the registers. The level ADC information is used during search as

well as preset tuning to compare the received signal strength with a search stop level (see

Section 7.1.4.3). A ﬂag will be set to indicate that the level voltage is below the predeﬁned

search stop level (see Figure 3). When the tuning algorithm is ﬁnished the level ADC is

deactivated.

6.12 Mute

6.12.1 Soft mute

The low-pass ﬁltered level voltage drives the soft mute attenuator. At low RF input levels,

the audio output is faded and hence also the noise. The soft mute function can be

disabled with bit SMUTE in register TNCTRL (see Table 13).

6.12.2 Hard mute

With bit MU in register TNCTRL (see Table 14) the audio outputs VAFL and VAFR can be

hard muted, this means they are put in high ohmic mode. The same can be done by

setting bits LHM (Left Hard Mute) or RHM (Right Hard Mute) in register TESTREG (see

Table 19), which mutes only one output at a time (or both when both set). When one

output is muted, the stereo decoder switches to mono. If the TEA5760UK is in Standby

mode the audio outputs are in high impedance mode, see Table 3.

Table 3.

Type

Speciﬁcation of mute modes

Description

Left

Impedance Mode

Right

Impedance Mode

AFM

Audio Frequency

Mute

350 Ω

muted

350 Ω

muted

MU

Hard Mute

500 kΩ

350 Ω

1 MΩ

muted

500 kΩ

350 Ω

muted

LHM

Left Hard Mute

Right Hard Mute

Standby

mono audio

muted

RHM

mono audio 500 kΩ

muted 1 MΩ

Standby

SMUTE

muted

Soft Mute

RF level sensitive audio level. Has no inﬂuence on mute

or pin impedance.

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

7 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

6.12.3 Audio Frequency Mute (AFM)

With bit AFM in register TNCTRL (see Table 13), the audio signal can be muted. The

audio pins maintain their functional impedance and DC-biasing level while the audio

signal is muted. The audio frequency mute is automatically activated during preset as well

as search tuning modes as shown in the ﬂowchart of Figure 3.

6.13 MPX decoder

The PLL stereo decoder is adjustment free. The stereo decoder can be switched to mono

via the control interface.

6.14 Signal depending mono/stereo blend (stereo noise cancellation)

With decreasing RF input level the MPX decoder blends from stereo to mono to limit the

output noise. The continuous mono-to-stereo blend can also be programmed via the

control interface to an RF level depending on the switched mono-to stereo transition.

Stereo Noise Cancellation (SNC) can be switched on/off via the control interface using bit

SNC in register TNCTRL (see Table 13). The RF input voltage where blending starts can

be switched with bit SNCLEV in register TESTREG (see Table 20).

6.15 Software programmable port

One software programmable port (CMOS output) is available and can be controlled via

the control interface.

• Bit SWPM = 1; the software port (SWPORT) functions as the output for bit FRRFLAG

• Bit SWPM = 0; the software port outputs bit SWP of the registers

In software test mode the software port outputs signals according to Table 21. Software

test mode is selected setting bit TM of register TESTREG. The software port is not

disabled by bit PUPD (see Section 6.16).

6.16 Standby

With the Power-Up/Power-Down (PUPD) bit the radio can be put in Standby mode.

Standby mode is deﬁned as where the TEA5760UK has all supply voltages available but

the circuits are powered down via software or after power-on reset. The TEA5760UK is

still accessible via the control interface, but takes only a very limited amount of power from

the supply. The software programmable port remains active to allow peripheral devices to

be controlled. The audio outputs are hard muted.

When pin BUSEN is HIGH and the circuits are powered down via software (PUPD) the

TEA5760UK is in Sleep mode. In Sleep mode the TEA5760UK is accessible via the

I²C-bus, but the radio part is not active. The digital supply current (I_CCD) is higher than in

Standby mode.

When the supply voltage V_CCAand V_CCDare at 0 V and pin VREFDIG is HIGH, all I/Os,

the audio outputs and the reference clock input are high-ohmic.

The power supplies can be switched on in any order.

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

8 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

6.17 Power-on reset

After start-up of V_CCAand V_CCD, a power-on-reset circuit will generate a reset pulse and

the registers will be set to their default values as shown in Table 8. The power-on reset is

effectively generated by V_CCD. To prevent any uncontrolled control interface response,

before power is switched on, pin BUSEN must be LOW. The audio output pins are

high-ohmic (hard mute), all other bits are set default according to Table 8.

6.18 Control interface

The I²C-bus operates with a maximum clock frequency of 400 kHz.

6.19 Auto search and preset mode

6.19.1 Search mode

In Search mode the TEA5760UK can search channels automatically.

When the INTX signal is used as an interrupt to the host processor to indicate a search

stop, the INTMSK register must be reset and only the FRRMSK must be set. In this way

the host processor will only be interrupted when the search/preset algorithm is ready.

Search mode is initiated by setting the SM bit to logic 1 in the FRQSET register. When bit

SUD = 0 then it searches down, when SUD = 1 it searches up. The tuner starts searching

at the frequency where it is or at a new start frequency programmed to the tuner. In the

case the programmed frequency is a valid channel and auto search is initiated, the radio

will stay tuned to programmed frequency. To continue the auto search tune algorithm

under such conditions, an offset frequency relative to the tuned frequency has to be

programmed (for example 100 kHz) to search for subsequent channels. With the Search

Stop Level (SSL) bits the minimum ﬁeld strength of channels to be found can be set. The

tuner will stop on a channel with a ﬁeld strength equal to or higher than this reference level

and then will check the IF frequency. When both are valid the Search mode terminates. If

the level check or the IF count fails, it keeps on searching. When no channels are found

the TEA5760UK stops searching when it has reached the band limit and the BLFLAG

goes HIGH. A search always stops with the FRRFLAG being set and a hardware interrupt.

Figure 3 describes this procedure.

After this interrupt the TEA5760UK will keep its status and will not update the INTREG,

FRQCHK and TUNCHK tuner registers for a period of 15.625 ms. The state of the

TEA5760UK can be checked by reading tuning registers INTREG, FRQCHK and

TUNCHK. Table 4 shows the possible states after an auto search or a preset.

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

9 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

start

mute the audio

outputs

reset flags

set PLL frequency

wait for PLL to settle

false

level OK

true

set LEVFLAG

IF OK

true

set IFFLAG

false

AHLSI

true

false

search mode

true

false

search up

true

increment current_pll

by 100 kHz

decrement current_pll

by 100 kHz

false

band limit

true

BLFLAG = 0

FRRFLAG = 1

no mute

BLFLAG = 0

FRRFLAG = 1

mute

BLFLAG = 1

FRRFLAG = 1

no mute

001aaf262

Fig 3. Flowchart auto search or preset (IF statement down = true)

6.19.2 Preset mode

A preset is done by setting bit SM to logic 0 and writing a frequency to register FRQSET.

The tuner jumps to the selected frequency and sets the FRRFLAG when it is ready. After

this interrupt the TEA5760UK will not update the tuner registers for a period of 15.625 ms.

The state of the TEA5760UK can be checked by reading registers INTREG, FRQCHK and

TUNCHK. Table 4 shows the possible states after an auto search or preset.

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

10 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

Table 4.

Tuner truth table

Bit

Comment

IFFLAG

BLFLAG

FRRFLAG

0

if INTX has gone low and IFMSK, LEVMSK,

FRRMSK and BLMSK were set then this cannot

occur

0

1

channel found during search, BLMSK and

FRRMSK set

0

1

0

1

not a valid combination

no channel found and the band limit has been

reached during a search, BLMSK and FRRMSK

set

1

0

1

not possible during a preset or a search

A preset or search has been done, but the

wanted channel has a valid RSSI level but fails

the IF count. When AHLSI was set HLSI must be

toggled and a new PLL value must be

programmed.

1

0

1

not a valid combination

band limit is reached during search, no valid

channel found

6.19.3 Auto high-side and low-side injection stop switch

The channel quality can sometimes be improved in case of image frequency interference.

This can be achieved if the LO injection is positioned at the opposite side of the wanted

channel (see Figure 4). Indication for image frequency interference can be derived from

the IF frequency counter. To enable this feature bit AHLSI has to be set to logic 1.

The search/preset algorithm will stop and generate an interrupt event after detection of a

valid RSSI level in combination with a frequency outside the IF frequency window. The

host processor can detect this state by reading the interrupt register. Swap of the LO

injection is achieved by inversion of bit HLSI in combination with a new tuning word for the

changed oscillator frequency (see Section 6.5).

image on low-side

wanted channel

image on high-side

switch LO from high-side to low-side

001aab460

Fig 4. Switch from high-side injection of LO to low-side injection using the HLSI bit

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

11 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

6.19.4 Muting during search or preset

During a preset and search tuning the tuner is always muted, this is done by the algorithm

itself. When bit AHLSI is set and the tuner stopped during a preset or a search because of

a wrong IF count, the tuner stays muted and generates an interrupt event. In this way the

host processor can switch the Hi-Lo setting quietly and wait for the new result.

All these mute actions are done by blocking the audio signal inside the soft mute

attenuator, so the audio output will keep its DC level and stay low-ohmic i.e. 350 Ω (a hard

mute with bit MU will cause a plop) (see Table 3).

7. Interrupt handling

7.1 Interrupt register

The ﬁrst two bytes of the I²C-bus register contain the interrupt masks and the interrupt

ﬂags. A ﬂag is set when it is 1.

Table 5.

Bit

INTREG byte0R

7

6

5

4

3

2

1

0

Symbol

-

IFFLAG

LEVFLAG

-

FRRFLAG

BLFLAG

Table 6.

Bit

INTREG byte0W

7

6

5

4

3

2

1

0

Symbol

-

IFMSK

LEVMSK

-

FRRMSK

BLMSK

The interrupt ﬂag register contains the ﬂags set according to the behavior outlined in

Section 7.1.4. When these are set they can also cause the INTX to go active [HardWare

(HW) interrupt line] depending on the status of the corresponding mask bit in Table 6. A

logic 1 in the mask register enables the HW interrupt for that ﬂag.

Hence it is conceivable that, with all the mask bits cleared, the SoftWare (SW) could

operate in a polling mode by continuous read operation of the interrupt ﬂag register to look

for bits being set.

Interrupt mask bits are always cleared after reading the interrupt register of the ﬁrst two

I²C-bus bytes. This is to control multiple HW interrupts (see Figure 5).

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

12 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

7.1.1 Interrupt clearing

The interrupt ﬂag and mask bits are always cleared after:

• They have been read via the control interface

• A power-on reset

7.1.2 Timing

The timing sequence for the general operation interrupts is shown in Figure 5 shows a

read access of the interrupt register INTREG and a subsequent (though not necessarily

immediate) write to the mask register. It also indicates two key timing points A and B.

If an interrupt event occurs while the register is being read (after point A) it must be held

until after the mask register is cleared at the end of the read operation (point B).

Point A is deﬁned as: the R/W bit has been decoded. Point B is where the acknowledge

has been received from the master after the ﬁrst two bytes have been sent.

The low time for the INTX line (t_p) has a maximum value speciﬁed in Section 11. It can be

shorter when a read action of the INTREG registers occurs within t_p.

7.1.3 Reset

A reset can be performed (at any time) by a simple read of the interrupt register (byte0R

and byte1R), which automatically clears the interrupt ﬂags and masks.

7.1.4 Interrupt ﬂags and behavior

7.1.4.1 Multiple interrupt events

If the interrupt mask register bit is set then the setting of an interrupt ﬂag for that bit

causes a HW interrupt (INTX goes LOW). If the event occurs again, before the ﬂag is

cleared, then this does not trigger any further HW interrupts until that speciﬁc ﬂag is

cleared. However two different events can occur in sequence and generate a sequence of

HW interrupts.

Only when read, followed by a write of the INTMSK byte has been done, can a second

interrupt can be generated, as the ﬁrst interrupt blocks the input of the INTX oneshot

generator.

If subsequent interrupts occur within the INTX LOW period then these do not cause the

INTX period to extend beyond its speciﬁed maximum period (see Section 7.2).

7.1.4.2 IF frequency: IFFLAG

During automatic frequency search or preset, the FM part of the TEA5760UK performs a

check on the received IF frequency. If an incorrect IF frequency is received then this

indicates the presence of strong interference or tuning to the image frequency. In case of

preset tuning or search tuning with the AHLSI bit set the IFFLAG will be set and the

algorithm will stop. When a search or preset is ﬁnished the FRRFLAG will be set and an

interrupt is generated if the corresponding mask bit is set. The host processor can now

read the outcome of the registers which will contain the IF count value and the IFFLAG

status of the channel it is tuned to.

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

14 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

7.1.4.3 RSSI threshold: LEVFLAG

The level voltage reﬂects the ﬁeld strength received by the antenna. The level voltage is

analog-to-digital converted with 4 bits and output via the control interface. This 4-bit level

value can be compared to a threshold level set by the SSL bits (see Table 14). The level

ADC (which converts the analog value to digital) is triggered by a search or preset cycle.

During a tuning step, which can be a search or a preset it is triggered by these algorithms

and compares the level with the threshold set by the SSL bits. The LEVFLAG bit is set if

the RSSI level drops below the threshold level set by the SSL bits (see Table 14), the HW

interrupt is only generated if the corresponding mask bit is set.

7.1.4.4 Frequency ready ﬂag: FRRFLAG

The frequency ready ﬂag bit FRRFLAG is set to logic 1 when the automatic tuning has

ﬁnished a search or preset. The description of this bit is given in Table 9. This bit is

cleared by a read of the ﬂag register.

7.1.4.5 Band limit: BLFLAG

The band limit bit BLFLAG is set to logic 1 when the automatic tuning has detected the

end of the tuning band. This bit is described in Table 9. This bit is cleared by a read of the

ﬂag register.

7.2 Interrupt line

The interrupt line driver is a MOS transistor with a nominal sink current of 900 µA. It is

pulled HIGH by an 18 kΩ resistor connected to pin VREFDIG. The interrupt line can be

connected to one other similar device with an interrupt output and an 18 kΩ pull-up

resistor, providing a wired-OR function. This allows any of the drivers to pull the interrupt

line LOW by sinking the current (see Section 11). When a ﬂag is set and not masked it

generates an interrupt.

V

CCA

(1)

flag

INTX

<10 ms

10 ms

read clears INTX

(2)

read INTMSK

write

(3)

INTMSK

001aab489

(1) When Flag is set next interrupts are blocked until Read/Write INTMSK.

(2) Read INTMSK clears Flag, INTMSK and INTX.

(3) Write INTMSK enables INTX.

Fig 6. Interrupt line behavior

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

15 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

8. I²C-bus interface

The I²C-bus interface is based on The I²C-bus speciﬁcation, version 2.1 January 2000,

expanded by the following deﬁnitions.

8.1 Write and read mode

S

BYTE 1

chip address

0010 0000

A

BYTE 2

byte0W

A

BYTE n

.....

A

BYTE 8

byte6W

NAK

P

R/W

0

xxxx xxxx

001aac341

Fig 7. Write mode

S

BYTE 1

A

BYTE 2

byte0R

A

BYTE n

.....

A

BYTE 17

byte15R

xxxx xxxx

A

P

chip address

0010 0000

R/W

1

xxxx xxxx

001aac342

Fig 8. Read mode

Table 7.

Code

S

I²C-bus transfer description

Description

START condition

Byte 1

I²C-bus chip address (7 bits)

R/W = 0 for write action and R/W = 1 for read action

acknowledge (SDA = LOW)

data byte (8 bits)

A

Byte 2, etc.

NAK

P

non acknowledge (SDA = HIGH)

STOP condition

8.2 Data transfer

Structure of the I²C-bus:

• Slave transceiver

• Subaddresses not used

Remark: The I²C-bus operates at a maximum clock rate of 400 kHz. It is not allowed to

connect the TEA5760UK to an I²C-bus operating at a higher clock rate.

Data transfer to the TEA5760UK:

• Bit 7 of each byte is considered the MSB and has to be transferred as the ﬁrst bit of

the byte.

• The LSB indicates the write or read action.

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

16 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

• The data becomes valid byte-wise at the appropriate falling edge of the SCL clock.

• A STOP condition after any byte can shorten transmission times. When writing to the

receiver by using the STOP condition before completion of the whole transfer:

– The remaining bytes will contain the old information.

– If the transfer of a byte is not completed the new bits will be used, but a new tuning

cycle will not be started.

I²C-bus activity:

• With bit PUPD the TEA5760UK can be switched in a low current Standby mode. The

I²C-bus is then still active.

• When the I²C-bus interface is de activated, by making pin BUSENABLE LOW and

without programmed Standby mode, the TEA5760UK keeps its normal operation, but

is isolated from the I²C-bus lines.

• Bus trafﬁc can be started 10 µs after activating the bus again by making

pin BUSENABLE HIGH.

SDA

SCL

t

f

t

BUF

t

r

t

P

S

Sr

t

SU;STO

t

SU;STA

HD;STA

SU;DAT

HD;DAT

HIGH

LOW

t

h(BUSEN)

su(BUSEN)

BUSEN

001aaf518

t_f= fall time of both SDA and SCL signals: 20 + 0.1 C_b< t_f< 300 ns, where C_b= total capacitance on bus line in pF.

t_r= rise time of both SDA and SCL signals: 20 + 0.1 C_b< t_r< 300 ns, where C_b= total capacitance on bus line in pF.

t_HD;STA= hold time (repeated) START condition. After this period, the ﬁrst clock pulse is generated: > 600 ns.

t_HIGH= HIGH period of the SCL clock: > 600 ns.

t_SU;STA= set-up time for a repeated START condition: > 600 ns.

t_HD;DAT= data hold time: 300 < t_HD;DAT< 900 ns.

Remark: 300 ns lower limit is added because the ASIC has no internal hold time for the SDA signal.

t_SU;DAT= data set-up time: t_SU;DAT> 100 ns. If ASIC is used in a standard mode I²C-bus system, t_SU;DAT> 250 ns.

t_SU;STO= set-up time for STOP condition: > 600 ns.

t_BUF= bus free time between a STOP and a START condition: > 600 ns.

C_b= capacitive load of one bus line: < 400 pF.

t_su(BUSEN)= set-up time on pin BUSEN: t_su(BUSEN)> 10 µs.

t_h(BUSEN)= hold time on pin BUSEN: t_h(BUSEN)> 10 µs.

Fig 9. Bus timing diagram

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

17 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

8.3 Register map

Table 8.

Register overview

Register name

I²C-bus byte number

Access

Reset value

Reference

Read

0R

Write

INTREG

R

00h

80h

00h

08h

D2h

-

Table 9

1R

0W

1W

2W

3W

4W

R/W

R

Table 10

Table 11

Table 12

Table 13

Table 14

Table 15

Table 16

Table 17

Table 18

Table 19

Table 20

Table 22

Table 23

Table 24

Table 25

FRQSET

TNCTRL

FRQCHK

TUNCHK

TESTREG

MANID

2R

3R

4R

5R

6R

7R

R

-

8R

R

-

9R

R

-

10R

11R

12R

13R

14R

15R

5W

6W

R/W

R

00h

20h

2Bh

57h

60h

R

CHIPID

R

8.4 Register description

8.4.1 Register INTREG

Table 9.

Register INTREG - byte0R

Legend: * reset value

Bit

7 to 5

4

Symbol

-

Access Value

Description

-

not used

IFFLAG

R

0*

1

IF count is correct

IF count is not correct

3

LEVFLAG

R

0*

1

RSSI level is above VSSL[1:0]

RSSI level has dropped below VSSL[1:0]

not used

2

1

-

FRRFLAG

R

0*

1

tuner state machine is not ready

tuner state machine is ready

0

BLFLAG

R

0*

during a search the band limit has not been

reached or no time-out

1

during a search the band limit has been

reached or time-out

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

18 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

Table 10. Register INTREG - byte1R/byte0W description

Legend: * reset value

Bit

7 to 5

4

Symbol

-

Access Value

Description

-

not used

IFMSK

R/W

0*

1

does not mask bit IFFLAG

masks bit IFFLAG

3

LEVMSK

R/W

0*

1

does not mask bit LEVFLAG

masks bit LEVFLAG

2

1

-

restricted for RDS usage

does not mask bit FRRFLAG

masks bit FRRFLAG

FRRMSK

R/W

0*

1

0

BLMSK

R/W

0*

1

does not mask bit BLFLAG

masks bit BLFLAG

8.4.2 Register FRQSET

Table 11. Register FRQSET - byte2R/byte1W description

Legend: * reset value

Bit

Symbol

Access Value

Description

search down

search up

7

SUD

R/W

0

1*

0*

1

6

SM

Preset mode

Search mode

5 to 0

FR_[13:08]

00 0000* frequency set; FR_13 is MSB

Table 12. Register FRQSET - byte3R/byte2W description

Legend: * reset value

Bit

Symbol

Access Value

R/W 00*h

Description

7 to 0

FR_[07:00]

frequency set; FR_00 is LSB

8.4.3 Register TNCTRL

Table 13. Register TNCTRL - byte4R/byte3W

Legend: * reset value

Bit

7

Symbol

-

Access Value Description

R/W

-

not used

6

PUPD

power-up power-down MSB

FM off

0*

1

FM on

5

4

3

BLIM

R/W

0*

1

US/Europe FM band 87.5 MHz to 108 MHz

Japan FM band 76 MHz to 90 MHz

software port is output of bit SWP

software port is output of bit FRRFLAG

IF count time = 1.953 ms

IF count time = 15.625 ms

SWPM

IFCTC

0*

1

0

1*

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

19 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

Table 13. Register TNCTRL - byte4R/byte3W …continued

Legend: * reset value

Bit

Symbol

Access Value Description

2

AFM

R/W

0*

1

audio not muted

left and right audio muted

soft mute off

1

0

SMUTE

SNC

0*

1

soft mute on

0*

1

stereo noise cancellation off

stereo noise cancellation on

Table 14. Register TNCTRL - byte5R/byte4W description

Legend: * reset value

Bit

Symbol

Access Value

Description

7

MU

R/W

1

1 = L- and R- audio hard muted;

0 = no hard mute

6 and 5

SSL_[1:0]

R/W

search stop level

ADC3

00

01

10*

11

0

ADC5

ADC7

ADC10

4

3

2

1

0

HLSI

MST

SWP

DTC

R/W

low-side injection

high-side injection

stereo on

1*

0*

1

forced mono

0*

1

SWPORT = LOW

SWPORT = HIGH

de-emphasis time constant = 75 µs

de-emphasis time constant = 50 µs

tuner will search continuously

0

1*

0*

1

AHLSI

tuner will stop during search on failed IF

count and correct level

8.4.4 Register FRQCHK

Table 15. Register FRQCHK - byte6R description

Bit

Symbol

Access Value

Description

7 and 6

5 to 0

-

not used

PLL_[13:08]

R

frequency found; PLL_13 is MSB

Table 16. Register FRQCHK - byte7R description

Bit

Symbol

Access Value

Description

7 to 0

PLL_[07:00]

R

-

frequency found; PLL_00 is LSB

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

20 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

8.4.5 Register TUNCHK

Table 17. Register TUNCHK - byte8R description

Bit

7 to 1

0

Symbol

IF_[6:0]

TUNTO

Access Value

Description

R

-

IF count; IF_6 is MSB, IF_0 is LSB

PLL has settled

0

1

PLL tuning time-out

Table 18. Register TUNCHK - byte9R description

Bit

7 to 4

3

Symbol

LEV_[3:0]

LD

Access Value

Description

R

-

level count; LEV_3 is MSB, LEV_0 is LSB

0

1

0

1

-

PLL is not locked

PLL is locked

mono

2

STEREO

-

R

-

stereo

1 and 0

not used

8.4.6 Register TESTREG

Table 19. Register TESTREG - byte10R/byte5W description

Legend: * reset value

Bit

Symbol

Access Value

Description

7

LHM

R/W

0*

1

left audio output is not muted

left audio output is hard muted

right audio output is not muted

right audio output is hard muted

not used

6

RHM

R/W

0*

1

5 to 3

2

-

R/W

-

TUN

0

no tuning programming error

tuning programming error

RFAGC on

1

0

RFAGC

R/W

0*

1

RFAGC off

INTCTRL

0*

1

no interrupt generated on INTX

when INTCTRL is set to 1 and TM = 1;

generates an interrupt on INTX

Table 20. Register TESTREG - byte11R/byte6W description

Legend: * reset value

Bit

Symbol

-

Access Value

Description

7 and 6

5

R/W

-

not used

SNCLEV

1*

starting point mono/stereo blending, this is a

write only bit

0

30 µV (EMF value)

15 µV (EMF value)

1*

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

21 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

Table 20. Register TESTREG - byte11R/byte6W description …continued

Legend: * reset value

Bit

Symbol

Access Value

Description

4

TM

R/W

0*

1

normal operation

TEA5760UK in Test mode and software port

outputs according to Table 21

3 to 0

TB_[3:0]

R/W

0*h

test bits, Table 21 describes selection of

output signals available at the SWPORT

Table 21. SWPORT

Bit

Output signal

Output pin

TM

TB_3 TB_2 TB_1 TB_0

0/1

0

bit SWP of byte4W (SWPM = 0) or

SWPORT

FRRFLAG (SWPM = 1)

oscillator output 32.768 kHz

lock detect bit LD

1

0

1

0

1

0

1

0

1

0

1

SWPORT

INTX

stereo bit STEREO

programmable divider

8.4.7 Register MANID

Table 22. Register MANID - byte12R description

Legend: * reset value

Bit

Symbol

Access Value

Description

7 to 4

3 to 0

VERSION[3:0]

MAN_ID[10:07}

R

0010*

0000*

version code

manufacturer ID code

Table 23. Register MANID - byte13R description

Legend: * reset value

Bit

7 to 1

0

Symbol

Access Value

Description

MAN_ID[06:00]

IDAV

R

000 0101* manufacturer ID code

0

chip has no manufacturer ID

1*

chip has manufacturer ID (available in IIC

mode)

8.4.8 Register CHIPID

Table 24. Register CHIPID - byte14R description

Legend: * reset value

Bit

Symbol

Access Value

57*h

Description

7 to 0

CHIP_ID[15:08]

R

TEA5760UK chip identiﬁcation code

Table 25. Register CHIPID - byte15R description

Legend: * reset value

Bit

Symbol

Access Value

60*h

Description

7 to 0

CHIP ID[07:00]

R

TEA5760UK chip identiﬁcation code

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

22 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

9. Limiting values

Table 26. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

The quality requirements are derived from the GQS - General Quality Speciﬁcation.

Symbol Parameter

Conditions

Min

−0.6

−40

Max

+3.6

+125

+85

Unit

V

V_LO1

V_LO2

V_CCD

V_CCA

V_I

voltage on pin LO1

voltage on pin LO2

digital supply voltage

analog supply voltage

input voltage

V

with respect to ground

V

V_O

output voltage

V

T_stg

storage temperature

ambient temperature

°C

T_amb

TEA5760UK

functional,

−35

speciﬁcation not

guaranteed

[1]

[2]

V_esd

electrostatic discharge voltage

MM

−200

+200

V

HBM

all pins, except pin

FREQIN

−2000 +2000

pin FREQIN

CDM

−1750

−500

+1750

+500

V

[3]

[1] MM: Machine Model; R = 0 Ω and C = 200 pF.

[2] HBM: Human Body Model; R = 1.5 kΩ and C = 100 pF.

[3] CDM: Charged Device Model; JEDEC Standard JESD22-C101.

10. Recommended operating conditions

Table 27. Recommended operating conditions

Symbol Parameter Conditions

Reference clock 32.768 kHz

Min

Typ

Max

Unit

f

frequency

T_amb= 25 °C

-

32.768 -

kHz

∆f/f

relative

frequency

difference

T_amb= 25 °C

−20 × 10^-6

−150 × 10^-6

-

+20 × 10^-6

+150 × 10^-6

T_amb= −20 °C to +85 °C

δ

duty cycle

rise time

fall time

square wave

30

-

70

%

ns

V

t_r

50

t_f

-

50

V_IH

HIGH-level

square wave

1.0

V_CCD

input voltage

V_IL

LOW-level input square wave

voltage

0

-

0.7

V

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

23 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

11. Characteristics

The IEC ﬁlter as mentioned in the characteristics is deﬁned in IEC60315-4. The audio

bandwidth of this ﬁlter is between 200 Hz and 15 kHz.

The characteristics are valid under restriction of the reference clock as speciﬁed in

Section 10.

Table 28. General characteristics

Symbol

V_CCA

Parameter

Conditions

Min

Typ

2.7

8.7

1

Max

3.6

10

3

Unit

V

analog supply voltage

VCO supply voltage

digital supply voltage

analog supply current

2.6

V_CC(VCO)

V_CCD

2.6

V

2.6

V

I_CCA

operational

-

mA

µA

mA

µA

Standby mode

operational

I_CC(VCO)

VCO supply current

digital supply current

5

7

Standby mode

operational

0.8

350

5

2

I_CCD

450

10

25

Standby mode

Sleep mode;

16

BUSEN = HIGH

V_VREFDIG

I_VREFDIG

voltage on pin VREFDIG

current on pin VREFDIG

V_VREFDIG

V_CCD

≤

1.65

1.8

3.6

V

operational

-

1

-

10

µA

Standby mode

-

1

µA

f_i(FM)

T_amb

FM input frequency

ambient temperature

76

−20

108

+85

MHz

°C

[1]

[2]

-

[1] Fulﬁll speciﬁcations.

[2] Functional, indication required for reduced performance.

Table 29. Characteristics

All AC values are given in RMS unless otherwise speciﬁed. The minimum and maximum values include spread due to:

voltage between 2.6 V and 3.6 V; T_amb= −20 °C to +85 °C; reference frequency offset plus deviation and process spread.

V

_VREFDIG= 1.65 V to 3.6 V.

Symbol Parameter

Antenna input including matching circuit

Conditions

Min

Typ

Max

Unit

Z_i

input impedance

input return loss

f_RF= 76 MHz to 108 MHz

-

50

-

Ω

2

|s₁₁

|

−5

dB

Voltage controlled oscillator

f_VCOVCO frequency

Reference frequency input: pin FREQIN

150

-

217

MHz

V_FREQIN

voltage on pin FREQIN switching level

input resistance

0.7

500

-

0.925 1.0

V

R_i

C_i

-

kΩ

pF

input capacitance

7

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

24 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

Table 29. Characteristics …continued

All AC values are given in RMS unless otherwise speciﬁed. The minimum and maximum values include spread due to:

voltage between 2.6 V and 3.6 V; T_amb= −20 °C to +85 °C; reference frequency offset plus deviation and process spread.

V_VREFDIG= 1.65 V to 3.6 V.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Synthesizer

Programmable divider

t_s

settling time

single frequency jump in any direction

to a frequency within the frequency

band (87.5 MHz to 108 MHz or

76 MHz to 90 MHz); settling limit is

±5 kHz of target frequency

-

40

ms

D_prog

programmable divider maximum;

FRQSET[15:8] = XX01 1111;

-

8191

-

FRQSET[7:0] = 1111 1111

minimum;

2048

FRQSET[15:8] = XX00 1000;

FRQSET[7:0] = 0000 0000

D_prog(step)programmable divider

step

-

1

-

f_step

step frequency

synthesizer auto search frequency

100

kHz

IF counter

N_IFc

IF counter length

sensitivity voltage

-

7

-

bit

V_sens

-

3^[1]

3C

60

-

µV

hex

dec

µs

N_IFc(result)IF counter result

for search stop;

31

49

-

stop level 3 V < V_RF^[1]< 2 V

-

T

period

IFCTC = 1

IFCTC = 0

15625

1953

4096

-

µs

N_IFc(res)

IF counter resolution

-

Hz

Logic pins: pins BUSEN, CLOCK and DATA

R_I

input resistance

10

-

MΩ

V_IH

HIGH-level input

voltage

0.7 ×

V_VREFDIG

V_VREFDIG+ V

0.3

V_IL

LOW-level input

voltage

−0.3

-

0.3 ×

V_VREFDIG

V

Software multi functional port pin: SWPORT

V_O(max)

maximum output

voltage

I_load= 150 µA

V_VREFDIG

0.25

−

V_VREFDIG

0.45

V

V_O(min)

minimum output

voltage

I_load= 150 µA

0

0.2

I_sink

sink current

V_SWPORT= 1.8 V

V_SWPORT= 0 V

500

-

µA

I_source

source current

Pin INTX

V_O(max)

maximum output

voltage

V

0.2

_VREFDIG− -

V_VREFDIG+ V

0.2

V_O(min)

minimum output

voltage

1.65 V ≤ V_VREFDIG; pull-up resistor of

second device connected to INTX

18 kΩ ± 20 %

0

-

0.22 ×

V_VREFDIG

V

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

25 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

Table 29. Characteristics …continued

All AC values are given in RMS unless otherwise speciﬁed. The minimum and maximum values include spread due to:

voltage between 2.6 V and 3.6 V; T_amb= −20 °C to +85 °C; reference frequency offset plus deviation and process spread.

V_VREFDIG= 1.65 V to 3.6 V.

Symbol

Parameter

Conditions

Min

600

14.4

Typ

900

18

Max

1100

24

Unit

µA

I_sink

sink current

including internal R_pu(int)

R_pu(int)

internal pull-up

resistance

kΩ

t_p

pulse duration

9

-

10

ms

FM signal channel

FM RF input

V_sens

sensitivity voltage

f_RF= 76 MHz to 108 MHz;

-

2^[1]

3.0^[1]

µV

∆f = 22.5 kHz; f_mod= 1 kHz;

S+N/N = 26 dB; τ_deemp= 50 µs; L = R;

IEC ﬁlter + A-weighting ﬁlter

S/N

signal-to-noise ratio

f_RF= 76 MHz to 108 MHz;

45

-

dBa

∆f = 22.5 kHz; f_mod= 1 kHz; L = R;

τ_deemp= 50 µs; V_RF= 10 µV (EMF

value); IEC ﬁlter + A-weighting ﬁlter

IP3_ib

in-band third-order

intercept point

∆f1 = 200 kHz; ∆f2 = 400 kHz;

82^[1]

88^[1]

95^[1]

-

dBµV

f_RF= 76 MHz to 108 MHz; RF AGC is

off

IP3_ob

out-band third-order

intercept point

∆f1 = 4 MHz; ∆f2 = 8 MHz;

100^[1]

f_RF= 76 MHz to 108 MHz; RF AGC is

off

IF ﬁlter

f_c

center frequency

220

16

225

-

230

-

kHz

dB

S₂₀₀

200 kHz selectivity

∆f = ±200 kHz; f_RF= 76 MHz to

108 MHz;measured according to

EN55020; τ_deemp= 50 µs

S_FM

FM selectivity

∆f_min= 300 kHz; f_RF= 76 MHz to

108 MHz; except image frequency

band measured according to

EN55020; τ_deemp= 50 µs

35

25

-

dB

α_f(image)

image frequency

rejection

∆f = 450 kHz; measured according to

EN55020; image rejection deﬁned as

difference between image and

co-channel response; τ_deemp= 50 µs

FM IF level detector and mute voltage; see Figure 10

∆G

gain deviation

deviation from average curve

extrapolated

−2

0.75^[1]

+2

2.5^[1]

dB

µV

dB

V_ADC(start)start ADC voltage

G_ADC(step)step of ADC gain

Soft mute

1.6^[1]

2.8

average

2.5

3

V_mute(start)start mute voltage

SMUTE = 1

V_RF= 1.26 µV^[1], L = R; ∆f = 22.5 kHz;

3^[1]

5

3.8^[1]

5.8

5^[1]

8

µV

α_mute

mute attenuation

dB

f_mod= 1 kHz; τ_deemp= 75 µs; IEC ﬁlter;

SMUTE = 1

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

26 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

Table 29. Characteristics …continued

All AC values are given in RMS unless otherwise speciﬁed. The minimum and maximum values include spread due to:

voltage between 2.6 V and 3.6 V; T_amb= −20 °C to +85 °C; reference frequency offset plus deviation and process spread.

V

_VREFDIG= 1.65 V to 3.6 V.

Symbol Parameter

Stereo decoder; pins VAFL and VAFR

Conditions

Min

Typ

Max

Unit

V_O

output voltage

V_RF= 2 mV^[1]; L = R; ∆f = 22.5 kHz;

_mod= 1 kHz; τ_deemp= 75 µs

60

75

350

-

90

400

-

mV

Ω

f

R_O

output resistance

MU = LHM = RHM = 0; AFM = 0 or

AFM = 1

250

500

hard mute; MU = LHM = RHM = 1;

AFM = 0 or AFM = 1

kΩ

Standby mode; PUPD = 0

1

-

MΩ

µA

dB

I_O

output current

minimum load resistance = 10 kΩ

80

−0.5

100

-

120

+0.5

|∆G_v|

voltage gain difference V_RF= 2 mV^[1]; L = R; ∆f = 75 kHz;

_mod= 1 kHz; IEC ﬁlter; τ_deemp= 75 µs

f

α_cs(stereo)stereo channel

V_RF= 2 mV^[1]; ∆f = 75 kHz including

9 % pilot; R = 0 and L = 1 or R = 1 and

L = 0; f_mod= 1 kHz; IEC ﬁlter; MST = 0;

SNC = 1

separation

SNCLEV = 1 or SNC = 0

30

27

-

40

36

-

dB

Hz

SNCLEV = 0

audio band; V_RF= 2 mV^[1];

∆f = 22.5 kHz, L = R,

-

f_−3dB(l)

low frequency −3 dB

point

20

pre-emphasis = 75 µs; τ_deemp= 75 µs

f_−3dB(h)

(S+N)/N

high frequency −3 dB audio band; V_RF= 2 mV^[1];

15

-

kHz

point

∆f = 22.5 kHz, L = R,

pre-emphasis = 75 µs; τ_deemp= 75 µs

signal plus

V_RF= 2 mV^[1]; ∆f = 22.5 kHz; L = R;

noise-to-noise ratio

f_mod= 1 kHz; τ_deemp= 50 µs; IEC ﬁlter

+ A-weighting ﬁlter

mono

53

49

-

57

53

-

dBA

stereo; ∆f_pilot= 6.75 kHz

-

α_resp(sp)

spurious response

relative to ∆f = 22.5 kHz; fm = 1 kHz

(mono); V_RF= 2 mV^[1]; τ_deemp= 50 µs;

IEC ﬁlter + A-weighting ﬁlter

−60

THD

total harmonic

distortion

mono; V_RF= 2 mV^[1]; L = R;

τ_deemp= 75 µs

∆f = 75 kHz; f_mod= 400 Hz

∆f = 75 kHz; f_mod= 1 kHz

∆f = 75 kHz; f_mod= 3 kHz

∆f = 100 kHz; f_mod= 1 kHz

-

0.4

0.5

0.8

1

%

stereo; V_RF= 2 mV^[1]; ∆f = 75 kHz;

L = R including 9 % pilot;

τ_deemp= 75 µs

f_mod= 1 kHz

f_mod= 3 kHz

-

0.5

1.5

%

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

27 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

Table 29. Characteristics …continued

All AC values are given in RMS unless otherwise speciﬁed. The minimum and maximum values include spread due to:

voltage between 2.6 V and 3.6 V; T_amb= −20 °C to +85 °C; reference frequency offset plus deviation and process spread.

V_VREFDIG= 1.65 V to 3.6 V.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

α_AM

AM suppression

L = R; ∆f = 22.5 kHz; f_mod= 1 kHz;

m = 0.3; τ_deemp= 75 µs, IEC ﬁlter

[1]

V_RF= 20 µV

40

45

40

-

dB

V_RF= 200 µV to 20 mV

-

α_pilot

pilot suppression

related to ∆f = 75 kHz; including 9 %

pilot; L = 0 and R = 1 or L = 1 and

R = 0; f_mod= 1 kHz; τ_deemp= 75 µs

50

[1]

∆f_pilot

pilot frequency

deviation

stereo; required for pilot detection;

1.8

3.6

5.8

kHz

V_RF= 2 mV

α_hys(pilot)

τ_deemp

pilot hysteresis

switch of pilot; V_RF= 2 mV

DTC = 1

2

2.5

50

75

5

dB

µs

de-emphasis time

constant

40

60

90

DTC = 0

Mono/stereo blend

V_start(blend)blend start voltage

stereo channel separation = 1 dB;

SNC = 1

SNCLEV = 0

SNCLEV = 1

20^[1]

10^[1]

4

30^[1]

15^[1]

10

40^[1]

20^[1]

16

µV

dB

α_cs(stereo)stereo channel

V_RF= 80 µV (EMF value); ∆f = 75 kHz;

R = 0 + L = 1 or R = 1 + L = 0;

including 9 % pilot; f_mod= 1 kHz;

MST = 0; SNC = 1 + SNCLEV = 1 or

SNC = 0

separation

Mono/stereo switching

V_sw

switch voltage

∆f = 75 kHz, including 9 % pilot;

60^[1]

2

80^[1]

3

110^[1]

4

µV

f

_mod= 1 kHz; SNC = 0

∆f = 75 kHz, including 9 % pilot;

_mod= 1 kHz; SNC = 0

|∆V_sw/V_sw| switch voltage

deviation over switch

dB

f

voltage ratio

Bus driven mute functions

Tuning mute

α_mute

mute attenuation

∆f = 75 kHz; mono, IEC ﬁlter

AFM = 1 or RHM = 1

AFM = 1 or LHM = 1

MU = 1

-

−60

−80

dB

[1] EMF value.

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

28 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

15

ADC

level

10

5

0

2

3

1

V

10

V

(µV)

sens

G

∆G

001aaf263

start(ADC)

V_ADC(start)is the starting point of the curve. Taking the starting point the curve shows a

monotone increase, increasing with the average step size G_ADC(step). The maximum deviation

from the average curve is ∆G

Fig 10. FM IF level detector and mute voltage

12. Application information

Table 30. List of components

Symbol

Value

Type

L1

120 nH

Murata LQW15ANR12J00 or equivalent, minimum

Q = 20 (f = 100 MHz), tolerance = ±5 %

L2

47 nH

Murata LQW15AN47NJ00 or equivalent, minimum

Q = 25 (f = 250 MHz), tolerance = ±5 %

R

C

10 kΩ, 100 kΩ

tolerance = ±10 % (max).

27 pF, 47 pF,

100 pF, 10 nF,

100 nF (2 ×)

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

29 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

13. Package outline

WLCSP25: wafer level chip-size package; 25 bumps; 3 x 2.8 x 0.6 mm

TEA5760UK

B

A

E

D

bump A1

index area

A

2

A

1

detail X

e

1

1/2 e

C

M

v

C

A

B

e

b

y

w

E

e

D

C

B

A

e

2

e

3

1

2

3

4

5

6

X

0

1

2

3 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

1

e

2

e

3

v

w

y

max

0.26 0.38 0.34

0.22 0.34 0.30

3.1

3.0

2.9

2.8

mm

0.64

0.5

2.5

2

0.028 0.01 0.04 0.02

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

05-12-09

06-07-06

TEA5760UK

Fig 12. Package outline TEA5760UK (WLCSP25)

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

31 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

14. Soldering

14.1 Introduction to soldering WLCSP packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in Application Note

AN10439 “Wafer Level Chip Scale Package” and in Application Note AN10365 “Surface

mount reﬂow soldering description”.

Wave soldering is not suitable for this package.

14.2 Board mounting

Board mounting of a WLCSP requires several steps:

1. Solder paste printing on the PCB

2. Component placement with a pick and place machine

3. The reﬂow soldering itself

14.3 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 13) than a PbSn process, thus

reducing the process window

• Solder paste printing issues, such as smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature), and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic) while being low enough that the packages and/or boards are not

damaged. The peak temperature of the package depends on package thickness and

volume and is classiﬁed in accordance with Table 31 and 32

Table 31. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 32. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

260

> 2000

260

< 1.6

1.6 to 2.5

> 2.5

260

250

245

250

245

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

32 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 13.

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 13. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

14.3.1 Stand off

The stand off between the substrate and the chip is determined by:

• The amount of printed solder on the substrate

• The size of the solder land on the substrate

• The bump height on the chip

The higher the stand off, the better the stresses are released due to TEC (Thermal

Expansion Coefﬁcient) differences between substrate and chip.

14.3.2 Quality of solder joint

A ﬂip-chip joint is considered to be a good joint when the entire solder land has been

wetted by the solder from the bump. The surface of the joint should be smooth and the

shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps

after reﬂow can occur during the reﬂow process in bumps with high ratio of bump diameter

to bump height, i.e. low bumps with large diameter. No failures have been found to be

related to these voids. Solder joint inspection after reﬂow can be done with X-ray to

monitor defects such as bridging, open circuits and voids.

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

33 of 36

TEA5760UK

NXP Semiconductors

14.3.3 Rework

Single chip FM stereo radio

In general, rework is not recommended. By rework we mean the process of removing the

chip from the substrate and replacing it with a new chip. If a chip is removed from the

substrate, most solder balls of the chip will be damaged. In that case it is recommended

not to re-use the chip again.

Device removal can be done when the substrate is heated until it is certain that all solder

joints are molten. The chip can then be carefully removed from the substrate without

damaging the tracks and solder lands on the substrate. Removing the device must be

done using plastic tweezers, because metal tweezers can damage the silicon. The

surface of the substrate should be carefully cleaned and all solder and ﬂux residues

and/or underﬁll removed. When a new chip is placed on the substrate, use the ﬂux

process instead of solder on the solder lands. Apply ﬂux on the bumps at the chip side as

well as on the solder pads on the substrate. Place and align the new chip while viewing

with a microscope. To reﬂow the solder, use the solder proﬁle shown in Application Note

AN10365 “Surface mount reﬂow soldering description”.

14.3.4 Cleaning

Cleaning can be done after reﬂow soldering.

15. Revision history

Table 33. Revision history

Document ID

Release date

20061214

Data sheet status

Change notice

Supersedes

TEA5760UK_1

Product data sheet

-

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

34 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

result in personal injury, death or severe property or environmental damage.

16.2 Deﬁnitions

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

I²C-bus — logo is a trademark of NXP B.V.

17. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

TEA5760UK_1

Product data sheet

Rev. 01 — 14 December 2006

35 of 36

TEA5760UK

NXP Semiconductors

Single chip FM stereo radio

18. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

7.1.4.5

7.2

Band limit: BLFLAG . . . . . . . . . . . . . . . . . . . . 15

Interrupt line . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

8

8.1

8.2

8.3

I²C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 16

Write and read mode . . . . . . . . . . . . . . . . . . . 16

Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Register map . . . . . . . . . . . . . . . . . . . . . . . . . 18

Register description . . . . . . . . . . . . . . . . . . . . 18

Register INTREG . . . . . . . . . . . . . . . . . . . . . . 18

Register FRQSET . . . . . . . . . . . . . . . . . . . . . 19

Register TNCTRL. . . . . . . . . . . . . . . . . . . . . . 19

Register FRQCHK . . . . . . . . . . . . . . . . . . . . . 20

Register TUNCHK . . . . . . . . . . . . . . . . . . . . . 21

Register TESTREG . . . . . . . . . . . . . . . . . . . . 21

Register MANID . . . . . . . . . . . . . . . . . . . . . . . 22

Register CHIPID. . . . . . . . . . . . . . . . . . . . . . . 22

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

8.4

8.4.1

8.4.2

8.4.3

8.4.4

8.4.5

8.4.6

8.4.7

8.4.8

6

Functional description . . . . . . . . . . . . . . . . . . . 5

Low noise RF ampliﬁer . . . . . . . . . . . . . . . . . . . 5

FM mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Reference frequency . . . . . . . . . . . . . . . . . . . . 5

PLL tuning system . . . . . . . . . . . . . . . . . . . . . . 5

Band limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

RF AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

IF ﬁlter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

FM demodulator . . . . . . . . . . . . . . . . . . . . . . . . 6

IF counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Level voltage generator and analog-to-digital

converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Hard mute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Audio Frequency Mute (AFM). . . . . . . . . . . . . . 8

MPX decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Signal depending mono/stereo blend (stereo

noise cancellation) . . . . . . . . . . . . . . . . . . . . . . 8

Software programmable port . . . . . . . . . . . . . . 8

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9

Control interface . . . . . . . . . . . . . . . . . . . . . . . . 9

Auto search and preset mode. . . . . . . . . . . . . . 9

Search mode . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Preset mode . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Auto high-side and low-side injection stop

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10

6.11

9

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 23

Recommended operating conditions . . . . . . 23

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24

Application information . . . . . . . . . . . . . . . . . 29

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 31

10

11

12

13

6.12

14

14.1

14.2

14.3

14.3.1

14.3.2

14.3.3

14.3.4

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Introduction to soldering WLCSP packages. . 32

Board mounting . . . . . . . . . . . . . . . . . . . . . . . 32

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 32

Stand off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Quality of solder joint . . . . . . . . . . . . . . . . . . . 33

Rework. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Cleaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6.12.1

6.12.2

6.12.3

6.13

6.14

6.15

6.16

6.17

6.18

15

Revision history . . . . . . . . . . . . . . . . . . . . . . . 34

16

Legal information . . . . . . . . . . . . . . . . . . . . . . 35

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 35

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35

16.1

16.2

16.3

16.4

6.19

6.19.1

6.19.2

6.19.3

switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Muting during search or preset. . . . . . . . . . . . 12

17

18

Contact information . . . . . . . . . . . . . . . . . . . . 35

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6.19.4

7

7.1

Interrupt handling . . . . . . . . . . . . . . . . . . . . . . 12

Interrupt register . . . . . . . . . . . . . . . . . . . . . . . 12

Interrupt clearing. . . . . . . . . . . . . . . . . . . . . . . 14

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Interrupt ﬂags and behavior . . . . . . . . . . . . . . 14

Multiple interrupt events . . . . . . . . . . . . . . . . . 14

IF frequency: IFFLAG . . . . . . . . . . . . . . . . . . . 14

RSSI threshold: LEVFLAG . . . . . . . . . . . . . . . 15

Frequency ready ﬂag: FRRFLAG . . . . . . . . . . 15

7.1.1

7.1.2

7.1.3

7.1.4

7.1.4.1

7.1.4.2

7.1.4.3

7.1.4.4

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 14 December 2006

Document identifier: TEA5760UK_1


型号：	TEA5760UK/N1/S21,0
厂家：	NXP
描述：	IC SPECIALTY CONSUMER CIRCUIT, PBGA25, 3 X 2.80 MM, 0.60 MM HEIGHT, WLCSP-25, Consumer IC:Other 商用集成电路
文件：	总37页 (文件大小：209K)
中文：	中文翻译
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TEA5760UK/N1/S21,0 [NXP]

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