FAN53741UC108X [ONSEMI]
1.3A Synchronous buck Regulator with I2C interface;
| 型号： | FAN53741UC108X |
| 厂家： | 
ONSEMI |
| 描述： | 1.3A Synchronous buck Regulator with I2C interface 开关 |
| 文件： | 总18页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Synchronous Buck
Regulator, 2.5 MHz
WLCSP6 1.38x0.94x0.625
FAN53741
CASE 567UH
Description
MARKING DIAGRAM
The FAN53741 is a 2.5 MHz step−down switching voltage
regulator, that delivers a fixed output from an input voltage supply of
2.3 V to 5.5 V. Using a proprietary architecture with synchronous
rectification, the FAN53741 is capable of delivering a peak efficiency
of 97% and can support a max load of 1300 mA.
1
2
K
Y
K
Z
Pin−1
Mark
X
The regulator operates at a nominal fixed frequency of 2.5 MHz,
which reduces the value of the external components achieving a total
solution size of 5.24 mm . At moderate and light load, Pulse
Frequency Modulation (PFM) is used to operate the device with a low
quiescent current of 60 mA. Even with such a low quiescent current,
the part exhibits excellent transient response during load swings. At
higher loads, the system automatically switches to fixed−frequency
control, operating at 2.5 MHz. In Shutdown Mode, the supply current
drops below 0.5 mA, reducing power consumption.
12
KK
X
Y
Z
= Alphanumeric Device Marking
= Lot Rune Code
= Alphabetical Year Code
= 2−weeks Date Code
= Assembly Plant Code
2
TYPICAL APPLICATION
SW
L
VIN
The FAN53741 is available in 6−bump, 0.4 mm pitch, Wafer−Level
Chip−Scale Package (WLCSP).
CIN
COUT
FB
FAN53741
SCL
SDA
Features
• 60 mA Typical Quiescent Current
2
• 5.24 mm Total Solution Size
• 1300 mA Output Current Capability
Figure 1. Typical Application
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
2
• Programmable Output Voltage 0.6 V to 3.3 V in 25 mV Steps via I C
Functionality
• Programmable Current Limit 530 mA to 2150 mA in 108 mA Steps
2
via I C Functionality
• 2.3 V to 5.5 V Input Voltage Range
• 2.5 MHz Fixed−Frequency Operation
• Best−in−Class Load Transient Response
• Internal Soft−Start Limits Battery Current Below 150 mA to avoid
Brown−out Scenarios
• Protection Faults (UVLO, OCP and TSP)
• Thermal Shutdown and Overload Protection
• 6−Bump WLCSP, 0.4 mm Pitch
• This is a Pb−Free Device
Applications
• Smart Phones
• Wearables
• Smart Watch
• Health Monitoring
• Sensor Drive
• Energy Harvesting
• Utility and Safety Modules
• RF Modules
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
March, 2022 − Rev. 5
FAN53741/D
FAN53741
ORDERING INFORMATION
Max. Output
Current
Temperature
Range
Device
Marking
†
Part Number
Output Voltage
0.6 V to 3.3 V
Package
Shipping
FAN53741UC108X
1300 mA
−40 to 85°C
WLCSP
3000 / Tape & Reel
GM
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
RECOMMENDED EXTERNAL COMPONENTS
Table 1. RECOMMENDED EXTERNAL COMPONENTS
Component
Description
Vendor
Parameter
Typ.
0.47
2.2
Unit
mH
L
0.47 mH, 20%, 3.1 A, 43 mW
2.2 mF, 20%, 6.3 V, X5R, 0402
10 mF, 20%, 6.3 V, X5R, 0402
HTEH20161T−R47MSR−89 (Cyntec)
C1005X5R0J225M050BC (TDK)
C1005X5R0J106M050BC (TDK)
L
C
C
CIN
mF
COUT
10
PIN CONFIGURATION
SDA
SCL
A1
B1
A2
B2
C2
A2
B2
C2
A1
B1
C1
VIN
SW
SDA
SCL
FB
VIN
SW
C1
GND
FB
GND
Figure 2. Top View (Bumps Down)
Figure 3. Bottom View (Bumps Up)
PIN DEFINITIONS
Pin #
A1
Name
SDA
VIN
Description
SDA. Serial Interface Data. Do not leave this pin floating.
A2
Input Voltage. Connect to input power source on positive terminal of input capacitor.
SCL. Serial Interface Clock. Do not leave this pin floating.
Switching Node. Connect to SW pad of inductor.
B1
SCL
SW
B2
C1
C2
FB
Feedback. Connect to positive side of output capacitor.
GND
Ground. Power and IC ground. All signals are referenced to this pin.
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2
FAN53741
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−0.3
−0.3
−0.3
−0.3
Max
Unit
V
VIN
Input Voltage
6.5
V
Voltage on SW Pin
SDA and SDA Pin Voltage
Other Pins
VIN + 0.3 (Note 1)
VIN + 0.3 (Note 1)
VIN + 0.3 (Note 1)
V
SW
V
CTRL
V
V
ESD
Human Body Model per JESD22−A114
Charged Device Model per JESD22−C101
Junction Temperature
2.0
1.0
kV
T
J
−40
−40
−
+150
+150
+260
°C
°C
°C
T
STG
Storage Temperature
T
L
Lead Soldering Temperature, 10 Seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Lesser of 6 V or VIN + 0.3 V.
RECOMMENDED OPERATING CONDITIONS
Symbol
VIN
Parameter
Supply Voltage Range
Min
2.3
−
Max
−
Max
5.5
1300
−
Unit
V
IOUT
CIN
Output Current
−
mA
mF
mF
mH
°C
Input Capacitor
−
2.2
10
0.47
−
COUT
L
Output Capacitor
−
−
Inductor
−
−
T
A
Operating Ambient Temperature
Operating Junction Temperature
−40
+85
+125
T
J
−
°C
−40
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
THERMAL PROPERTIES
Symbol
Parameter
Min
Max
Max
Unit
q
Junction−to−Ambient Thermal Resistance (Note 2)
−
125
−
°C/W
JA
2. Junction−to−ambient thermal resistance is a function of application and board layout. This data is simulated with four−layer 2s2p boards
without vias in accordance to JESD51− JEDEC standard. Special attention must be paid not to exceed the junction temperature.
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3
FAN53741
ELECTRICAL CHARACTERISTICS (Minimum and maximum values are at VIN = 3.8 V, T = −40°C to +85°C, unless otherwise
A
noted. Typical values are at T = 25°C, VIN = 3.8 V, VOUT = 3.3 V.)
A
Symbol
Parameter
Condition
Min
Typ
Max
Unit
I
PFM Quiescent Current
ENABLE Bit = 1, PFM Mode, no load,
non−switching
−
60
90
mA
Q,PFM
I
Shutdown Supply Current
ENABLE Bit = 0, no load
VIN Rising
−
0.5
2.15
2.05
100
2.50
−
2
mA
V
SD
V
V
Under−Voltage Lockout Threshold
2.10
2.00
2.22
2.11
UVLO_RISE
UVLO_FALL
VIN Falling
V
V
UVLO Hysteresis
mV
MHz
mV
UVLO_HYS
F
Switching Frequency
Output Voltage Accuracy
PWM, no load
2.25
2.75
+20
SW
V
VOUT = 0.6 V to 2.0 V, IOUT = 0 A,
PWM Mode
−20
OACC
VOUT = 2.0 V to 3.3 V, IOUT = 0 A,
PWM Mode
−1
−50
−2.5
1550
530
−
−
+1
%
VOUT = 0.6 V to 2.0 V, IOUT = 0 A,
PFM Mode
+50
mV
%
VOUT = 2.0 V to 3.3 V, IOUT = 0 A,
PFM Mode
−
+2.5
2350
2150
I
Peak Inductor Current Limit Accuracy
Programmed to 1934 mA Current Limit
Setting
1934
−
mA
mA
LIM_ACC
LIM_PRG
LIM_NEG
I
I
Programmable Peak Inductor Current
Limit Range
Negative Current Limit
PMOS Resistance
NMOS Resistance
−
−
−
−1000
0.125
0.082
−
−
−
mA
W
R
R
VIN = VGS = 3.6 V
VIN = VGS = 3.6 V
DSON
DSON
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
SYSTEM CHARACTERISTICS (The following System Characteristics are guaranteed by design and are not performed in production
testing. Recommended operating conditions, unless otherwise noted, V = 2.3 V to 5.5 V, T = −40°C to 85°C, V = 3.3 V. Typical values
IN
A
OUT
are given V = 3.6 V, V
= 3.3 V and T = 25°C. System Characteristics are based on circuit per Figure 1. L = 0.47 mH (0603
IN
OUT
A
DFE160808S−R47M − MURATA, 3.4 A / 53 mW) CIN = 2.2 mF (0402 − C1005X5R0J225M050BC − TDK) COUT = 10 mF (0402
C1005X5R0J106M050BC −TDK).)
Symbol
Parameter
Efficiency
Condition
Min
Typ
87
96
97
96
95
Max
−
Unit
Eff
I
I
I
I
I
= 1 mA
−
−
%
OUT
OUT
OUT
OUT
OUT
= 100 mA
= 300 mA
= 500 mA
= 700 mA
−
−
−
−
−
−
−
IOUT
IOUT MAX
1300
−
−
mA
mV/A
mV/V
mV
LOAD
Load Regulation
Line Regulation
Load Transient
0 mA < IOUT < 1200 mA, VIN = 3.8 V
26
−0.6
0
−
REG
REG
LINE
3.8 V < VIN < 4.35 V, IOUT = 300 mA, PWM Mode
−
−
V
TRRP
I
= 10 mA ⇔ 150 mA, T = T = 1 ms, Auto
−
−
OUT
R
F
Mode, VIN = 3.8 V
V
Load Transient
Ripple Voltage
I
= 100 mA ⇔ 1200 mA, T = T = 5 ms, Auto
−
60
−
mV
mV
TRRP
OUT
R
F
Mode, VIN = 3.8 V
V
I
I
= 20 mA, PFM Mode, VIN = 4.35 V
= 200 mA, PWM Mode, VIN = 4.35 V
−
−
50
12
−
−
OUT_RIPPLE
OUT
OUT
System Characteristics are tested closed loop while using the recommended external components table.
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4
FAN53741
TYPICAL CHARACTERISTICS
(Unless otherwise specified, V = 3.8 V, V
= 3.3 V, Auto Mode, T = 25°C; circuit and components according to Figure 1 and Table 1.)
IN
OUT
A
Figure 4. Quiescent Current vs. Input Voltage and
Temperature, VOUT = 1.9 V, Auto Mode
Figure 5. Quiescent Current vs. Input Voltage and
Temperature, VOUT = 3.3 V, Auto Mode
Figure 6. Efficiency vs. Load Current and Input
Voltage, VOUT = 1.9 V, Auto Mode
Figure 7. Efficiency vs. Load Current and Input
Voltage, VOUT = 3.3 V, Auto Mode
Figure 8. Load Regulation vs. Load Current and
Input Voltage, VOUT = 1.9 V, Auto Mode
Figure 9. Load Regulation vs. Load Current and
Input Voltage, VOUT = 3.3 V, Auto Mode
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5
FAN53741
OPERATION DESCRIPTION
The FAN53741 is a 2.5 MHz, step−down switching
voltage regulator from an input voltage supply of 2.3 V to
5.5 V. Using a proprietary architecture with synchronous
rectification, the FAN53741 is capable of delivering a peak
efficiency of 97%. The regulator operates at a nominal fixed
frequency of 2.5 MHz, which reduces the value of the
external components to 0.47 mH for the output inductor and
10 mF for the output capacitor.
restart. If the fault is caused by short circuit, the soft−start
circuit attempts to restart and produces an over−current fault
after about 20 ms. The Peak Inductor Current Limit can be
programmed via I C and range from 530 mA to 2150 mA
max in 108 mA steps.
2
Under−Voltage Lockout (UVLO)
When EN is HIGH, the under−voltage lockout keeps the
part from operating until the input supply voltage rises high
enough to properly operate. This ensures no misbehavior of
the regulator during startup or shutdown.
The FAN53741 provides a fixed output voltage ranging
from 0.6 V to 3.3 V, and can be programmed in 25 mV steps
2
via I C. The FAN53741 can support a max current 1300 mA.
Thermal Shutdown Protection (TSP)
MODES OF OPERATIONS
When the die temperature increases, due to a high load
condition and/or a high ambient temperature, the output
switching is disabled until the die temperature falls
sufficiently. The junction temperature at which the thermal
shutdown activates is nominally 150°C with a 15°C
hysteresis.
PFM Mode
At light load operation in AUTO Mode, the device enters
PFM mode when load current is below 124 mA typically.
PFM mode reduces switching frequency as well as battery
current draw, which yields high efficiency.
Negative Current Limit
PWM Mode
The FAN53741 has a negative current limit protection
which limits the current through the NFET. If a voltage is
applied to output of buck which is higher than VOUT target
while in PWM, then a negative current is detected. Once the
inductor current hits −1 A for one cycle, then the output
begins to tristate until the applied voltage is released and the
output voltage falls below the regulated voltage.
In PFM mode, the Zero Crossing Detection does not allow
any negative current to flow within inductor , any voltage
higher > vout target applied to output will cause the regulator
to enter tri−state and block current back through inductor
If voltage applied to VOUT is greater than VIN, then body
diode of high side FET will conduct.
During PWM mode, the device switches at a nominal
fixed frequency of 2.5 MHz, which reduces the values of the
external components. The part enters PWM when load
currents exceed 140 mA typically. In PWM mode, the device
has excellent load regulation ideal for power sensitive
accurate loads. The FAN53741 can be forced into PWM
regardless of the load current by inserting a 1 to the
FORCE_PWM register bit.
PROTECTION FEATURES
VOUT Fault
If the VOUT fails to reach 95% of VOUT target in 7 ms,
a VOUT fault is declared. During the fault condition the part
restarts every 20 ms to achieve the 95% target voltage. Once
the output voltage reaches the 95% VOUT target voltage the
VOUT fault clears.
Over−Current Limit (OCP)
A heavy load or short circuit on the output causes the
current in the inductor to increase until a maximum current
threshold is reached in the high−side switch. Upon reaching
this point, the high−side switch turns off, preventing high
currents from causing damage. After 500 ms of current limit,
the regulator triggers an over−current fault, causing the
regulator to shut down for about 20 ms before attempting a
Figure 10.
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6
FAN53741
OPERATION MODE
Programmable Output Voltage
Active Pull Down
The FAN53741 output voltage can be programmed via
The FAN53741 has an active pull down to discharge the
output capacitance. During a negative VOUT transition or
when the ENABLE reg is set from 1 to 0, within one clock
cycle, the active pull down is active and discharges the
VOUT via a internal resistor. This functionality is enabled
by setting Reg6[2] to 1 if required while having four options
of pull down strength to choose from in Reg6[1:0]: Open,
50 W, 100 W, and 200 W.
2
I C from 0.6 V to 3.3 V in 25 mV steps. The voltage
transition going from a lower to a higher voltage is a single
step with transition time dependent on output current and
output capacitance. The output current drives the voltage
slew rate from higher to lower voltage transitions. The
FAN53741 does not have DVS functionality.
Startup Description
2
To enable the FAN53741, the ENABLE reg must be set
to 1. FAN53741 has internal soft−start which limits the
battery current to 150 mA minimizing any brown out
applications.
Once the target VOUT voltage reaches 95% then the full
current limit operation enters. The device starts up within
600 ms typical with the recommended external components
table.
I C
Slave Address
The hex slave address is different for all parts in the
family. Other slave addresses can be accommodated upon
request. Contact your onsemi representative.
Device
Hex
Decimal
Binary
If the part fails to startup within about 7 ms, then the part
will declare a startup fault and will reattempt to start within
20 ms.
FAN53741
7h’52
82
1010010
2
I C Slave Address Byte for FAN53741.
Shutdown
To disable the FAN53741, the ENABLE reg should be
configured to code 0. When part is disabled, output voltage
will tristate and discharge via load or pull down resistor.
7
1
6
0
5
1
4
0
3
0
2
1
1
0
0
R/W
Read = 1, Write = 0
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7
FAN53741
TIMING DIAGRAMS
t SU;STA
t F
t BUF
SDA
t R
T SU;DAT
t
HD;STO
t LOW
t HIGH
t HD;DAT
SCL
t
HD;STA
t
HD;STA
REPEATED
START
START
STOP
START
Figure 11. I2C Interface Timing for Fast Plus, Fast, and Slow Modes
REPEATED
START
STOP
tFDA
tRDA
tSU;DAT
SDAH
tSU;STA
tRCL1
tLOW
tFCL
tRCL
tSU;STO
tHIGH
SCLH
tHD;STA
tHD;DAT
NOTE
REPEATED
START
= MCS Current Source Pull−up
= RP Resistor Pull−up
NOTE: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 12. I2C Interface Timing for High−Speed Mode
Bus Timing
tHD;STA
As shown in Figure 13 data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow sufficient time for the data to set up before
the next SCL rising edge.
Slave Address
MS Bit
SDA
SCL
Figure 14. START Bit
Data change allowed
A transaction ends with a STOP condition, defined as
SDA transitioning from 0 to 1 with SCL high, as shown in
Figure 15.
SDA
t H
Slave Releases Master Drives
t HD;STO
t SU
ACK(0) or
NACK(1)
SCL
SDA
Figure 13. Data Transfer Timing
SCL
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which
is defined as SDA transitioning from 1 to 0 with SCL HIGH,
as shown in Figure 14.
Figure 15. STOP Bit
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8
FAN53741
During a read from the FAN53741, the master issues a
bus master sends the HS master code 00001XXX after a
START condition (Figure 14). The master code is sent in Fast
or Fast−Plus Mode (less than 1 MHz clock); slaves do not
ACK this transmission.
REPEATED START after sending the register address and
before resending the slave address. The REPEATED
START is a 1 to 0 transition on SDA while SCL is HIGH, as
shown in Figure 16.
The master generates a REPEATED START condition
(Figure 16) that causes all slaves on the bus to switch to HS
2
t SU;STA t HD;STA
Slave Releases
Mode. The master then sends I C packets, as described
above, using the HS Mode clock rate and timing.
ACK(0) or
NACK(1)
SLADDR
MS Bit
SDA
SCL
The bus remains in HS Mode until a STOP bit (Figure 15)
is sent by the master. While in HS Mode, packets are
separated by REPEATED START conditions (Figure 16).
Figure 16. REPEATED START Timing
Read and Write Transactions
The following figures outline the sequences for data read
and write. Bus control is signified by the shading of the
High−Speed (HS) Mode
The protocols for High−Speed (HS), Low−Speed (LS),
and Fast−Speed (FS) Modes are identical; except the bus
speed for HS Mode is 3.4 MHz. HS Mode is entered when the
Master Drives Bus
packet,
defined
as
and
Slave Driver Bus
. All addresses and data are MSB first.
Table 2. I2C BIT DEFINITIONS FOR FIGURE 17 AND FIGURE 18
Symbol
Definition
S
P
R
A
A
START, see Figure 14
STOP, see Figure 15
REPEATED START, see Figure 16
ACK. The slave drives SDA to 0 to acknowledge the preceding packet.
NACK. The slave sends a 1 to NACK the preceding packet.
7 bits
8 bits
8 bits
Data
0
0
0
S
Slave Address
0
A
Reg Addr
A
A
P
Figure 17. Write Transaction
7 bits
Slave Address
8 bits
Reg Addr
7 bits
8 bits
Data
0
0
0
1
S
0
A
A
R
Slave Address
1
A
A
P
Figure 18. Write Transaction Followed by a Read Transaction
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FAN53741
REGISTER MAP
Table 3. REGISTER MAP
Read Only Write Only
Read / Write
Bit[2]
Read / Clear
Bit[1]
Write / Clear
Bit[0]
Address
Name
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
0x00
Product
ID_REV
Product ID
Silicon Revision
0x01
0x02
Fault Flag
Status
0
POR
UVLO
Fault
Over Temp
Fault
Current Limit
Fault
Startup Timeout Vout Short Fault
Fault
Fault Live
Status
0
UVLO
Over Temp
Current Limit
Startup Timeout
Vout Short
0x03
0x04
0x05
0x06
0x07
MODE
0
0
ENABLE
FORCE_PWM
VSEL
0
BUCK_VOUT
ILIMIT
0
ILIM
PULLDOWN
RESET
PULLDOWN
SOFT_RESET
PULL DOWN SEL
REGISTER DETAILS
Table 4. REGISTER DETAILS 1
0x00 Product ID_REV
Default = 00010000
Description
Bit
Name
Default
Type
7:4
Product ID
0001
Read
Capture Product configuration to allow customers to identify a device (if they have
2
access to I C) and allow read−back of desired configuration in the event of a
customer return
Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
<<Effect>>
−
FAN53741
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3:0
Silicon
Revision
0000
Read
To allow identification of silicon revision through ATE test. Customer visible when
2
there is I C bus that the customer has access to
Code
000
001
010
011
100
101
110
111
<<Effect>>
Initial Silicon
Increment register with each iteration
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FAN53741
Table 5. REGISTER DETAILS 2
0x01 Fault Flag Status
Default = 00100000
Description
Bit
7:6
5
Name
Unused
POR
Default
Type
1
R/CL R
Displays POR fault status. This indicator is latched when POR occurs and causes
a fault. The flag is clear upon read.
Code
0
1
||−− Effect −−||
Default
Power−on reset occurred
4
3
2
1
0
UVLO Fault
0
0
0
0
0
R/CL R
R/CL R
R/CL R
R/CL R
R/CL R
Displays UVLO fault status. This indicator is latched when UVLO occurs and
causes a fault. The flag is clear upon read.
Code
||−− Effect −−||
0
1
No UVLO fault
A UVLO fault occurred
Over Temp
Fault
Displays over temp fault status. This indicator is latched when over temp occurs
and causes a fault. The flag is clear upon read.
Code
||−− Effect −−||
0
1
No over temp fault
An over temp fault occurred
Current Limit
Fault
Displays over current fault status. This indicator is latched when over current
occurs and causes a fault. The flag is cleared upon read.
Code
||−− Effect −−||
0
1
No over current fault
An over current fault occurred
Startup
Timeout
Fault
Displays startup timeout fault status. This indicator is latched when startup timeout
occurs and causes a fault. The flag is cleared upon read.
Code
||−− Effect −−||
0
1
No startup timeout fault
A startup timeout fault occurred
Vout Short
Fault
Displays Vout short fault status. This indicator is latched when Vout short occurs
and causes a fault. The flag is clear upon read.
Code
||−− Effect −−||
0
1
No Vout short fault
A Vout short fault occurred
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FAN53741
Table 6. REGISTER DETAILS 3
0x02 Fault Live Status
Default = 00011000
Description
Bit
7:5
4
Name
Unused
UVLO
Default
Type
1
Read
Displays UVLO comparator status only when EN is set HIGH. Otherwise, this bit
reads as 1.
Code
0
1
||−− Effect −−||
No UVLO fault
UVLO fault
3
2
Over Temp
1
0
Read
Read
Displays over temp comparator status only when EN is set HIGH. Otherwise, this
bit reads as 1.
Code
||−− Effect −−||
0
1
No over temp fault
Over temp fault
Current
Limit
Displays over current comparator status only. A 1 will only be captured at the
moment that a fault is declared which last for one clock cycle. Thereafter, it will go
into FAULT state while setting this Live Flag to 0.
Code
||−− Effect −−||
0
1
No over current fault
Over current fault
1
0
Startup
Time
0
0
Read
Read
Displays startup timeout timer status. A 1 will only be captured at the moment that
a fault is declared which last for one clock cycle. Thereafter, it will go into FAULT
state while setting this Live Flag to 0.
Code
||−− Effect −−||
0
1
No startup timeout fault
Startup timeout fault
Vout Short
Displays Vout short comparator status. A 1 will only be captured at the moment
that a fault is declared which last for one clock cycle. Thereafter, it will go into
FAULT state while setting this Live Flag to 0.
Code
||−− Effect −−||
0
1
No Vout short fault
Vout short fault
Table 7. REGISTER DETAILS 4
0x03 MODE
Default = 00000000
Description
Bit
7:3
1
Name
Unused
ENABLE
Default
Type
0
R/W
This register enables/disables the buck regulator. Setting a code 0, shutdowns the
device, where as code 1 enables the device.
Code
Effect
0
1
Regulation Disabled
Regulation Enabled
0
FORCE_
PWM
0
R/W
Forces the part to operate in PWM mode regardless of the load current.
Code
Effect
0
1
Auto ( PFM / PWM depending on load current)
PWM
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12
FAN53741
Table 8. REGISTER DETAILS 5
0x04 VSEL
Default = 0111 101
Description
Bit
7
Name
Default
Type
Unused
6:0
BUCK_
VOUT
1111011
R/W
Sets buck regulation target voltage.
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
VOUT
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
VOUT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
600 mV
625 mV
650 mV
675 mV
700 mV
725 mV
750 mV
775 mV
800 mV
825 mV
850 mV
875 mV
900 mV
925 mV
950 mV
975 mV
1.000 V
1.025 V
1.050 V
1.075 V
1.100 V
1.125 V
1.150 V
1.175 V
1.200 V
1.225 V
1.250 V
1.275 V
1.300 V
1.325 V
1.350 V
1.375 V
1.400 V
1.425 V
1.450 V
1.475 V
1.825 V
1.850 V
1.875 V
1.900 V
1.925 V
1.950 V
1.975 V
2.000 V
2.025 V
2.050 V
2.075 V
2.100 V
2.125 V
2.150 V
2.175 V
2.200 V
2.225 V
2.250 V
2.275 V
2.300 V
2.325 V
2.350 V
2.375 V
2.400 V
2.425 V
2.450 V
2.475 V
2.500 V
2.525 V
2.550 V
2.575 V
2.600 V
2.625 V
2.650 V
2.675 V
2.700 V
2.725 V
2.750 V
2.775 V
2.800 V
2.825 V
2.850 V
2.875 V
2.900 V
2.925 V
2.950 V
2.975 V
3.000 V
3.025 V
3.050 V
3.075 V
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13
FAN53741
Table 8. REGISTER DETAILS 5 (continued)
0x04 VSEL
Default = 0111 101
Description
Bit
Name
Default
Type
6:0
BUCK_
VOUT
1111011
R/W
Hex
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
VOUT
Hex
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
VOUT
1.500 V
1.525 V
1.550 V
1.575 V
1.600 V
1.625 V
1.650 V
1.675 V
1.700 V
1.725 V
1.750 V
1.775 V
1.800 V
3.100 V
3.125 V
3.150 V
3.175 V
3.200 V
3.225 V
3.250 V
3.275 V
3.300 V
Reserved
Reserved
Reserved
Reserved
Table 9. REGISTER DETAILS 6
0x05 ILIMIT
Default = 00001111
Description
Bit
7:4
3:0
Name
Unused
ILIM
Default
Type
1111
R/W
This Register sets the peak inductor current limit thresholds. The Range is from
530 mA to 2150 mA in 108 mA steps.
Code
0000
0010
0011
0100
1000
1111
||−− Effect −−||
530 mA Current Limit (Open Loop)
746 mA Current Limit (Open Loop)
854 mA Current Limit (Open Loop)
962 mA Current Limit (Open Loop)
1394 mA Current Limit (Open Loop)
2150 mA Current Limit (Open Loop)
Table 10. REGISTER DETAILS 7
0x06 PULLDOWN
Default = 00000000
Description
Bit
7:3
2
Name
Unused
Default
Type
Pull Down
0
R/w
This register activates/deactivates the internal pull down resistor. Setting to
Code 1, the pull down is active when ENABLE goes from 1 to 0 and on any
negative V
transitions.
OUT
Code
Status of Pull down
0
1
Pull down not used (OFF)
Pull down active during transition
1:0
Pull Down
SEL
00
R/w
This register sets the strength of the pull down resistor.
Code
00
01
10
11
Strength of Pull down
OPEN
200 W
100 W
50 W
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14
FAN53741
Table 11. REGISTER DETAILS 7
0x07 RESET
Default = 00000000
Bit
Name
Default
Type
Description
2
7:0
SOFT_RESET 00000000
Write
The software reset register allows all I C settings to be reverted to POR defaults
when 0x60h code is written to it.
APPLICATIONS INFORMATION
Selecting the Inductor
The increased RMS current produces higher losses through
The output inductor must meet both the required
inductance and the energy−handling capability of the
application. The inductor value affects average current limit,
output voltage ripple, and efficiency.
the R
DCR.
of the IC MOSFETs, as well as the inductor
DS(ON)
Increasing the inductor value produces lower RMS
currents, but degrades transient response. For a given
physical inductor size, increased inductance usually results
in an inductor with lower saturation current and higher DCR.
Table 12 shows the effects of inductance higher or lower
than the recommended 1.0 mH on regulator performance.
The ripple current (DI) of the regulator is:
VOUT
VIN
VIN * VOUT
@ ǒ Ǔ
DI ≈
(eq. 1)
L @ fSW
The maximum average load current, I
is
MAX(LOAD),
related to the peak current limit, I
current, given by:
, by the ripple
LIM(PK)
Output Capacitor
Increasing C
has no effect on loop stability and can
OUT
DI
2
therefore be increased to reduce output voltage ripple or to
improve transient response. Vice versa, lower C can be
IMAX(LOAD) + ILIM(PK)
*
(eq. 2)
OUT
used but with a compromise of load transient response.
The transition between PFM and PWM operation is
determined by the point at which the inductor valley current
crosses zero. The regulator DC current when the inductor
OUT
Output voltage ripple, DV
, is:
f
SW @ COUT @ ESR2
1
+ DI ƪ
ƫ
DVOUT
)
current crosses zero, I , is:
DCM
L
(eq. 5)
2 @ D @ (1 * D)
8 @ fSW @ COUT
DI
2
IDCM
+
(eq. 3)
Input Capacitor
The FAN53741 is optimized for operation with
L = 0.47 mH. The inductor should be rated to maintain at
The 2.2 mF ceramic input capacitor should be placed as
close as possible between the VIN pin and GND to minimize
the parasitic inductance. If a long wire is used to bring power
to the IC, additional “bulk” capacitance (electrolytic or
least 80% of its value at I . It is recommended to
LIM_ACC
select an inductor where its saturation current is above the
MAX value.
I
tantalum) should be placed between C and the power
LIM_ACC
IN
Efficiency is affected by the inductor DCR and inductance
source lead to reduce the ringing that can occur between the
value. Decreasing the inductor value for a given physical
size typically decreases the DCR; but because DI increases,
the RMS current increases, as do the core and skin effect
losses.
inductance of the power source leads and C .
The effective capacitance value decreases as V
increases due to DC bias effects.
IN
IN
DI2
12
2
+ Ǹ
IRMS
IOUT(DC)
)
(eq. 4)
Table 12. EFFECTS OF CHANGES IN INDUCTOR VALUE (FROM 0.47 mH RECOMMENDED VALUE) ON REGULATOR
PERFORMANCE
Inductor Value
Increase
IMAX(LOAD)
Increase
DVOUT
Decrease
Increase
Transient Response
Degraded
Decrease
Decrease
Improved
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15
FAN53741
RECOMMENDED LAYOUT
LAYOUT CONSIDERATION
To minimize spikes at VOUT, COUT must be placed as
close as possible to PGND and VOUT, as shown in
Recommended Layout. For thermal reasons, it is suggested
to maximize the pour area for all planes other than SW.
Especially the ground pour should be set to fill all available
PCB surface area and tied to internal layers with a cluster of
thermal via
2
onsemi is licensed by the Philips Corporation to carry the I C bus protocol.
www.onsemi.com
16
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP6 1.38x0.94x0.625
CASE 567UH
ISSUE O
DATE 31 APR 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13465G
WLCSP6 1.38x0.94x0.625
PAGE 1 OF 1
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