FAN53763 [ONSEMI]
1.5 A Synchronous Buck Regulator;
| 型号： | FAN53763 |
| 厂家： | 
ONSEMI |
| 描述： | 1.5 A Synchronous Buck Regulator |
| 文件： | 总12页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FAN53763
1.5 A Synchronous Buck
Regulator
Description
The FAN53763 is a Super Low Iq, step−down switching voltage
regulator, that delivers a fixed output from an input voltage supply of
2.3 V to 5.5 V. Using a proprietary architecture with synchronous
rectification, the FAN53763 is capable of delivering a peak efficiency
of 93%, while maintaining efficiency over 90% at load currents as low
as 1 mA.
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The regulator operates with 0402 and 0603 input and output
capacitors, respectively, which reduces the total solution size to
5.5 mm . At moderate and light load, Pulse Frequency Modulation
WLCSP6
CASE 567UH
2
(PFM) is used to operate the device with a low quiescent current. Even
with such a low quiescent current, the part exhibits excellent transient
response during load swings. In Shutdown Mode, the supply current
drops to 100 nA, reducing power consumption. The Mode pin allows
the part to be in a Super Low IQ (SLIQ) mode with a typical quiescent
current of 2 mA.
MARKING DIAGRAM
12KK
XYZ
The FAN53763 is available in 6−bump, 0.4 mm pitch, Wafer−Level
Chip−Scale Package (WLCSP).
Features
12
KK
X
Y
Z
= Alphanumeric Device Code
= Lot Run Code
= Alphabetical Year Code
= 2−weeks Date Code
= Assembly Plant Code
• 2 mA Typical Quiescent Current
2
• 5.5 mm Total Solution Size
• 1.5 A Output Current Capability
• 0.6 V to 1.8 V Fixed Output Voltage
• 2.3 V to 5.5 V Input Voltage Range
• Best−in−Class Load Transient Response
• Best−in−Class Efficiency with Sub 1 mA Output Currents
• Internal Soft−Start Limits Battery Current Below 150 mA to Avoid
Brown−out Scenarios
SW
L1
VIN
VOUT
1.0μH
CIN
2.2μF
COUT
22μF
FAN53763
• Protection Faults (UVLO, OCP and OTP)
• Thermal Shutdown and Overload Protection
• 6−Bump WLCSP, 0.4 mm Pitch
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MODE
FB
EN
GND
Figure 1. Typical Application
ORDERING INFORMATION
Applications
• Wearables
• Smart Watch
• Health Monitoring
• Sensor Drive
See detailed ordering and shipping information on page 2 of
this data sheet.
• Energy Harvesting
• Utility and Safety Modules
• RF Modules
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
October, 2017 − Rev. 1
FAN53763/D
FAN53763
Table 1. ORDERING INFORMATION
Output Voltage
Max. Output
Temperature
(Note 1)
Current (Note 1)
Range
Part Number
Package
Packing Method
Device Marking
FAN53763UC24X
1.8 V
1.5 A
−40 to 85°C
WLCSP
Tape & Reel
GP
1. Other voltage and output current options are available. Contact an On Semiconductor representative
Table 2. RECOMMENDED EXTERNAL COMPONENTS
Component
Description
Vendor
Parameter
Typ
1.0
2.2
22
Unit
L
1.0 mH, 20%, 2.3 A, 107 mW, 1608
2.2 mF, 20%, 6.3 V, X5R, 0402
22 mF, 20%, 6.3 V, X5R, 0603
DFE160810S−1R0M (Murata)
C1005X5R0J225M050BC (TDK)
C1608X5R0J226M080AC (TDK)
L
C
C
mH
C
IN
mF
C
(Note 2)
OUT
2. A 10 mF, 0402 capacitor can be used to reduce total solution size at the expense of load transient performance.
Pin Configuration
A2
A1
B1
C1
EN
MODE
FB
VIN
SW
VIN
SW
EN
A1
B1
C1
A2
B2
C2
MODE
FB
B2
C2
GND
GND
Figure 2. Top View
Figure 3. Bottom View
Table 3. PIN DEFINITIONS
Pin #
Name
EN
Description
A1
Enable. The device is in Shutdown Mode when voltage to this pin is <0.4 V and enabled when >1.2 V.
Do not leave this pin floating. Recommended for GPIO 1.8 V to drive this pin.
A2
B1
VIN
Input Voltage. Connect to input power source across C .
IN
MODE
MODE. Logic “LOW” allows the IC to be in a Super Low IQ (SLIQ) state. A Logic HIGH allows the part
to be in normal Iq state Auto Mode.
B2
C1
C2
SW
FB
Switching Node. Connect to SW pad of inductor.
Feedback. Connect to positive side of output capacitor.
Ground. Power and IC ground. All signals are referenced to this pin.
GND
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−0.3
−0.3
−0.3
Max
Unit
V
V
IN
Input Voltage
6.5
V
SW
Voltage on SW Pin
V
V
+0.3 (Note 3)
+0.3 (Note 3)
V
IN
V
CTRL
EN, FB and Mode Pin Voltage
Human Body Model per JESD22−A114
Charged Device Model per JESD22−C101
Junction Temperature
V
IN
ESD
2.0
1.0
kV
T
J
−40
−40
+150
+150
+260
°C
°C
°C
T
STG
Storage Temperature
T
L
Lead Soldering Temperature, 10 Seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. Lesser of 6 V or V +0.3 V
IN
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2
FAN53763
Table 5. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.3
0
Typ
Max
5.5
Unit
V
V
IN
Supply Voltage Range
Output Current
I
1.5
A
OUT
C
Input Capacitor
2.2
1.0
mF
mF
mH
°C
°C
IN
C
(Note 4) Output Capacitor
3
100
1.3
OUT
L
Inductor
0.47
−40
−40
T
Operating Ambient Temperature
Operating Junction Temperature
+85
+125
A
T
J
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. Effective capacitance after DC bias.
Table 6. THERMAL PROPERTIES
Symbol
Parameter
Min
Typ
Max
Unit
θ
JA
Junction−to−Ambient Thermal Resistance (Note 5)
125
°C/W
5. Junction−to−ambient thermal resistance is a function of application and board layout. This data is simulated with four−layer 2s2p boards with
vias in accordance to JESD51− JEDEC standard. Special attention must be paid not to exceed the junction temperature.
Table 7. ELECTRICAL CHARACTERISTICS Minimum and maximum values are at V = V = 3.6 V, T = −40°C to +85°C,
IN
EN
A
unless otherwise noted. Typical values are at T = 25°C, V = V = 3.6 V, VOUT = 1.8 V.
A
IN
EN
Symbol
Parameter
Quiescent Current
Condition
Min
Typ
Max
Unit
mA
mA
nA
V
I
SLIQ Mode, no load, non−switching
PFM Mode, no load, non−switching
2
Q,SLIQ
I
PFM Quiescent Current
Shutdown Supply Current
5
Q,PFM
I
EN=GND, V =3.6 V, no load
100
2.15
2.05
SD
IN
V
V
Under−Voltage Lockout Threshold
V
Rising
Falling
2.10
2.00
1.2
2.21
2.10
UVLO_RISE
UVLO_FALL
IN
IN
V
V
V
IH
HIGH−Level Input Voltage
LOW−Level Input Voltage
Peak Current Limit
V
0.4
V
VIL
I
V
V
V
V
V
=4.35 V, open−loop
2215
mA
mV
mV
mW
mW
°C
°C
LIM
IN
V
R
Output Voltage Accuracy
=0.6V to 1.8V, I
=0.6V to 1.8V, I
=0, PWM Mode
=0, PFM Mode
−25
−40
+25
+40
OACC
OUT
OUT
OUT(DC)
OUT(DC)
PMOS On Resistance
NMOS On Resistance
Thermal Shutdown
= V = 3.6 V
135
95
DS(on)
IN
IN
GS
= V = 3.6 V
GS
T
TSD
150
15
T
HYS
Thermal Shutdown Hysteresis
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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FAN53763
Table 8. SYSTEM CHARACTERISTICS Recommended operating conditions, unless otherwise noted, V = 2.3 V to 5.5 V, T =
IN
A
−40°C to +85°C, V
= 1.8 V. Typical values are given at T = 25°C, V = 3.6 V. System characteristics are based on circuit per
OUT
A
IN
Figure 1. L = 1.0 mH, 2.3A, 107 mW DCR, DFE160810S−1R0M (Murata), C = 1x 2.2 mF, 6.3 V, 0402 (1005 metric),
IN
C1005X5R0J225M050BC (TDK) and C
= 1x 22 mF, 6.3 V, 0603 (1608 metric), C1608X5R0J226M080AC (TDK).
OUT
Symbol
Parameter
Conditions
Min
Typ
−9.0
−2.0
−0.5
Max
Units
mV/mA
mV/A
LOAD
Load Regulation
I
I
= 10 mA to 1 mA, SLIQ Mode
= 200 mA to 1500 mA, PWM
REG
OUT
OUT
LINE
Line Regulation
Ripple Voltage
3.0 V ≤ V ≤ 4.35 V,
mV/V
REG
IN
I
I
I
I
I
I
I
I
I
I
I
I
= 300 mA, PWM
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
V
40
25
mV
%
= 250 mA, SLIQ Mode
= 20 mA, PFM Mode
= 200 mA, PWM Mode
= 100 mA, SLIQ Mode
= 500 mA, SLIQ Mode
= 1 mA, PFM Mode
= 100 mA, PFM Mode
= 300 mA, PWM Mode
= 500 mA, PWM Mode
= 700 mA, PWM Mode
= 10 mA⇔150 mA,
OUT_RIPPLE
5
Eff
Efficiency
88
91
90
87
91
90
88
ΔV
Load Transient
Line Transient
−40/+25
mV
mV
mV
OUT_LOAD
T
= T = 1 ms, Auto Mode
R
F
I
= 100 mA⇔ 500 mA,
= T = 1 ms, SLIQ Mode
15
20
OUT
T
R
F
ΔV
V
= 3.0 V⇔3.6 V, T = T = 10 ms,
OUT_LINE
IN
R
F
I
= 300 mA, PWM Mode
OUT
NOTE: The above system characteristics are guaranteed by design and are not performed in production testing.
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FAN53763
Typical Characteristics
Unless otherwise specified, V = 3.6 V, V
= 1.8 V, Auto Mode, T = 25°C; circuit and components according to Figure 1 and Table 2.
IN
OUT
A
95
90
85
80
75
70
65
60
95
90
85
80
75
70
V
IN
V
IN
V
IN
V
IN
V
IN
= 2.50 V
= 3.00 V
= 3.80 V
= 4.35 V
= 5.00 V
65
60
−40°C
+25°C
+85°C
55
50
55
50
0
0.01
0.1
1
0
0.01
0.1
1
I
(A)
I
(A)
LOAD
LOAD
Figure 4. Efficiency vs. Load Current and Input
Voltage, VOUT = 1.8 V, Auto Mode
Figure 5. Efficiency vs. Load Current and
Temperature, VIN = 3.6 V, VOUT = 1.8 V, Auto
Mode
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
V
IN
V
IN
V
IN
V
IN
V
IN
= 2.5 V
= 3.0 V
= 3.6 V
= 4.2 V
= 5.0 V
−40°C
+25°C
+85°C
55
50
55
50
0.01
0.1
1
0.01
0.1
1
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 6. Efficiency vs. Load Current and Input
Voltage, VOUT = 1.8 V, SLIQ Mode
Figure 7. Efficiency vs. Load Current and
Temperature, VIN = 3.6 V , VOUT = 1.8 V, SLIQ
Mode
2.0%
1.5%
1.0%
0.5%
0%
2.0%
1.5%
1.0%
0.5%
0%
−40°C
+25°C
+85°C
V
IN
V
IN
V
IN
V
IN
V
IN
= 2.50 V
= 3.00 V
= 3.80 V
= 4.35 V
= 5.00 V
−0.5%
−1.0%
−0.5%
−1.0%
−1.5%
−2.0%
−1.5%
−2.0%
0
0.25
0.50
0.75
(A)
1.00
1.25
1.50
0
0.25
0.50
0.75
I (A)
LOAD
1.00
1.25
1.50
I
LOAD
Figure 8. Output Regulation vs. Load Current
and Input Voltage, VOUT = 1.8 V, Auto Mode
Figure 9. Output Regulation vs. Load Current
and Temperature, VIN = 3.6 V, VOUT = 1.8 V,
Auto Mode
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FAN53763
Typical Characteristics
Unless otherwise specified, V = 3.6 V, V
= 1.8 V, Auto Mode, T = 25°C; circuit and components according to Figure 1 and Table 2.
IN
OUT
A
3000
2500
2000
1500
60
V
IN
V
IN
V
IN
V
IN
= 3.00 V
= 3.80 V
= 4.35 V
= 5.00 V
50
40
30
20
V
IN
V
IN
V
IN
V
IN
V
IN
= 2.50 V
= 3.00 V
= 3.80 V
= 4.35 V
= 5.00 V
1000
500
0
10
0
0
0.25
0.50
0.75
(A)
1.00
1.25
1.50
0
0.25
0.50
0.75
I (A)
LOAD
1.00
1.25
1.50
I
LOAD
Figure 10. Frequency vs. Load Current and
Input Voltage, Auto Mode, VOUT = 1.8 V, Auto
Mode
Figure 11. Output Ripple vs. Load Current and
Input Voltage, VOUT = 1.8 V, Auto Mode
8
7
4
3
2
6
5
4
1
0
−40°C
+25°C
+85°C
−40°C
+25°C
+85°C
3
2
2.3
2.8
3.3
3.8
4.3
4.8
5.3
2.3
2.8
3.3
3.8
4.3
4.8
5.3
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 12. Quiescent Current vs. Input Voltage
and Temperature, VOUT = 1.8 V, Auto Mode
Figure 13. Quiescent Current vs. Input Voltage
and Temperature, VOUT = 1.8 V, SLIQ Mode
0.5
0.4
0.3
0.2
−40°C
+25°C
+85°C
VOUT(50mV/DIV, AC Coupled)
0.1
0
IOUT(100mA/DIV)
2.3
2.8
3.3
3.8
4.3
4.8
5.3
INPUT VOLTAGE (V)
Figure 14. Shutdown Current vs. Input Voltage
and Temperature
Figure 15. Load Transient, VIN= 3.6 V, VOUT
1.8 V, 10 mA ⇔ 150 mA, 1 ms Edge, Auto Mode
=
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FAN53763
Typical Characteristics
Unless otherwise specified, V = 3.6 V, V
= 1.8 V, Auto Mode, T = 25°C; circuit and components according to Figure 1 and Table 2.
IN
OUT
A
VOUT(50mV/DIV, AC Coupled)
IOUT(200mA/DIV)
Figure 16. Load Transient, VIN = 3.6 V, VOUT
1.8 V, 5 mA ⇔ 300 mA, 1 ms Edge, Auto Mode
=
Figure 17. Load Transient, VIN = 3.6 V, VOUT
1.8 V, 100 mA ⇔ 300 mA, 1 ms Edge, Auto
Mode
=
VOUT(100mV/DIV, AC Coupled)
IOUT(1A/DIV)
Figure 18. Load Transient, VIN = 3.6 V, VOUT
1.8 V, 10 mA ⇔ 1500 mA, 1 ms Edge, Auto
Mode
=
Figure 19. Line Transient, VIN = 3.0 V ⇔ 3.6 V,
V
OUT = 1.8 V, 10 ms Edge, 300 mA Load, Auto
Mode
Figure 20. Start−up, VIN = 3.6 V, VOUT = 1.8 V,
50 mA Resistive Load, Auto Mode
Figure 21. Start−up, VIN = 3.6 V, VOUT = 1.8 V,
300 mA Resistive Load, Auto Mode
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FAN53763
Operation Description
The FAN53763 is a Super Low Iq (SLIQ), step−down
switching voltage regulator, typically operating at 2.5 Mhz
currents from causing damage. The regulator continues to
limit the current cycle−by−cycle. After 500 ms of current
limit, the regulator triggers an over−current fault, causing
the regulator to shut down for about 20ms before attempting
a restart.
in Continuous Conduction Mode(CCM). Using
a
proprietary architecture with synchronous rectification, the
FAN53763 is capable of delivering a peak efficiency of
93%, while maintaining efficiency over 90% at load currents
sub 1 mA.
In SLIQ mode the device is very efficient with load
currents in the mA range. In SLIQ mode the device draws
less than 2 mA typical from the battery with no load. The load
transients in SLIQ mode are best in class.
Under−Voltage Lockout (UVLO)
When EN is HIGH, the under−voltage lockout keeps the
part from operating until the input supply voltage rises high
enough to properly operate. This ensures no misbehavior of
the regulator during startup or shutdown.
Over−Temperature Protection (OTP)
The FAN53763 provides a fixed output voltage of 0.6 V
to 1.8 V and load capability of 1.5 A, which can support
wearable or mobile phone applications which Li−Ion
batteries. Specialized soft−start limits the battery current to
150 mA to limit any brown out occurrences.
When the die temperature increases, due to a high load
condition and/or a high ambient temperature, the output
switching is disabled until the die temperature falls
sufficiently. The junction temperature at which the thermal
shutdown activates is nominally 150°C with a 15°C
hysteresis. Once the junction temperature falls below the
hysteresis threshold, the regulator performs a soft−start.
Control Scheme
Enable and Disable
When EN pin is Low, all circuits are off and the IC draws
Modes of Operations
100 nA current. When EN is High and V is above its
UVLO threshold, the regulator begins a soft−start cycle. The
FAN53763 has internal soft−start which limits the battery
IN
SLIQ (Super Low IQ)
In SLIQ Mode the device acts in a modified PFM mode
with a super low Iq state. The part draws 2 mA with no load.
The part enters SLIQ Mode when the Mode pin is set to
logic “LOW”. Before pulling the Mode Pin Low, the load
current should drop below 1 mA to maintain output voltage
regulation in SLIQ mode. The maximum load current in
SLIQ Mode that the device can support is 1 mA. If load
current exceeds 1 mA, it is recommended to place part in
Auto Mode by pulling Mode pin High so that the device can
support more current.
current draw to 150 mA. Once the part reaches 95% of V
OUT
target, the part will transition to the correct mode of
operation depending on load current. The part starts up
within 400 ms typical with the recommended external
components listed in Table 1.
MODE Pin
Setting Mode Pin Low sets the device in SLIQ mode;
setting Mode Pin High sets the device in normal Iq Auto
Mode.
The part can support more than 1mA in SLIQ Mode if the
output capacitor is increased.
Protection Features
VOUT Fault
PFM
At light load operation in Auto Mode, the device enters
PFM mode when load current is below 20 mA typically.
PFM mode reduces switching frequency as well as battery
current draw, which yields high efficiency.
When Mode pin goes High, the part will transition from
SLIQ Mode into normal PFM mode within 10 ms typically.
If the V
fails to reach 95% of V
target within
OUT
OUT
1.8 ms during startup, a VOUT fault is declared. During the
fault condition the part restarts every 20 ms to achieve the
95% target voltage. Once the output voltage reaches the 95%
V
OUT
target voltage within 1.8 ms, the VOUT fault clears.
PWM
Over−Current Protection (OCP)
When load is high, the part transitions smoothly from
PFM mode to PWM mode. The part enters PWM mode
when load current exceeds 50 mA typically.
A heavy load or short circuit on the output causes the
current in the inductor to increase until a maximum current
threshold is reached in the high−side switch. Upon reaching
this point, the high−side switch turns off, preventing high
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FAN53763
Applications Information
physical inductor size, increased inductance usually results
in an inductor with lower saturation current and higher DCR.
Table 9 shows the effects of inductance higher or lower
than the recommended 1.0 mH on regulator performance.
Selecting the Inductor
The output inductor must meet both the required
inductance and the energy-handling capability of the
application. The inductor value affects average current limit,
output voltage ripple, and efficiency.
Output Capacitor
Increasing C
has no effect on loop stability and can
OUT
The ripple current (DI) of the regulator is:
therefore be increased to reduce output voltage ripple or to
improve transient response. Vice versa, lower C can be
OUT
VOUT
VIN
VIN * VOUT
@ ǒ Ǔ
L @ fSW
used but with a compromise of load transient response.
Output voltage ripple, DV , is:
DI [
(eq. 1)
OUT
The maximum average load current, I
is
MAX(LOAD),
fSW @ COUT @ ESR2
2 @ D @ (1 * D)
1
related to the peak current limit, I
, by the ripple
+ DI ƪ
ƫ
DVOUT
)
LIM(PK)
L
8 @ fSW @ COUT
current, given by:
(eq. 5)
DI
2
IMAX(LOAD) + ILIM(PK)
*
(eq. 2)
Input Capacitor
The transition between PFM and PWM operation is
determined by the point at which the inductor valley current
crosses zero. The regulator DC current when the inductor
The 2.2 mF ceramic input capacitor should be placed as
close as possible between the VIN pin and GND to minimize
the parasitic inductance. If a long wire is used to bring power
to the IC, additional “bulk” capacitance (electrolytic or
tantalum) should be placed between C and the power
source lead to reduce the ringing that can occur between the
inductance of the power source leads and C .
The effective capacitance value decreases as V
increases due to DC bias effects.
current crosses zero, I , is:
DCM
DI
2
IDCM
+
(eq. 3)
IN
The FAN53763 is optimized for operation with L =
1.0 mH, but is stable with inductances up to 1.3 H (nominal).
The inductor should be rated to maintain at least 80% of its
IN
IN
value at I
.
LIM(PK)
Efficiency is affected by the inductor DCR and inductance
value. Decreasing the inductor value for a given physical
size typically decreases the DCR; but because DI increases,
the RMS current increases, as do the core and skin effect
losses.
PCB Layout Guidelines
1. The input capacitor (C ) should be connected as
IN
close as possible to the VIN and GND pins.
Connect to VIN and GND using only top metal.
Do not route through vias (see Figure 27.)
2. Place the inductor (L) as close as possible to the
IC. Use short wide traces for the main current
paths.
DI2
12
2
+ Ǹ
IRMS
IOUT(DC)
)
(eq. 4)
The increased RMS current produces higher losses
3. An output capacitor (C
) should be placed as
OUT
through the R
of the IC MOSFETs, as well as the
DS(ON)
close as possible to the IC. Connection to GND
should only be on top metal. Feedback signal
connection to VOUT should be routed away from
noisy components and traces (e.g. SW line).
inductor DCR.
Increasing the inductor value produces lower RMS
currents, but degrades transient response. For a given
Table 9. EFFECTS OF CHANGES in Inductor Value (from 1.0 mH Recommended Value) on Regulator Performance
Inductor Value
Increase
I
DV
Transient Response
Degraded
MAX(LOAD)
OUT
Increase
Decrease
Increase
Decrease
Decrease
Improved
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FAN53763
Connect VIN pin and CIN
using only top metal.
Connect COUT and GND
pin only on top layer;
VOUT trace should be
as wide and as short
as possible, for low im
pedance, also should
be routed away from
noisy components and
traces (e.g. SW line).
Put as many as possible
vias connected to ground
plane (layer 2), to help dis
sipate heat. Connect GND
vias to system ground.
The ground area should be
made as large as possible
to help dissipate heat.
Figure 22. Top Layer
Layer 2 should be a solid
ground layer, to shield VOUT
from capacitive coupling of
the fast edges of SW node.
Logic signals can be routed
on this layer.
Figure 23. Layer 1
SW trace should be as wide
and as short as possible,
and be isolated with GND
area from any other sensi
tive traces.
Figure 24. Layer 3
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10
FAN53763
PACKAGE DIMENSIONS
WLCSP6 1.38x0.94x0.625
CASE 567UH
ISSUE O
PRODUCT−SPECIFIC DIMENSIONS
D
E
X
Y
1.380 0.030
0.940 0.030
0.270
0.290
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11
FAN53763
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