FDMD82100L [ONSEMI]
双 N 沟道，PowerTrench® MOSFET，100V，24A，19.5mΩ;
| 型号： | FDMD82100L |
| 厂家： | 
ONSEMI |
| 描述： | 双 N 沟道，PowerTrench® MOSFET，100V，24A，19.5mΩ 开关 光电二极管 晶体管 |
| 文件： | 总9页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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June 2014
FDMD82100L
Dual N-Channel PowerTrench® MOSFET
100 V, 24 A, 19.5 mΩ
Features
General Description
Max rDS(on) = 19.5 mΩ at VGS = 10 V, ID = 7 A
Max rDS(on) = 30 mΩ at VGS = 4.5 V, ID = 5.7 A
Ideal for flexible layout in primary side of bridge topology
Termination is Lead-free and RoHS Compliant
100% UIL tested
This device includes two 100V N-Channel MOSFETs in a dual
Power (3.3 mm X 5 mm) package. HS source and LS Drain
internally connected for half/full bridge, low source inductance
package, low rDS(on)/Qg FOM silicon.
Applications
Synchronous Buck : Primary Switch of Half / Full bridge
converter for telecom
Kelvin High Side MOSFET drive pin-out capability
Motor Bridge : Primary Switch of Half / Full bridge converter
for BLDC motor
MV POL : 48V Synchronous Buck Switch
Pin 1
1
2
3
4
5
6
12
11
10
9
D1
D1
D1
G2
S2
S2
G1
G1R
D2/S1
D2/S1
8
D2/S1
D2/S1
7
Power 3.3 x 5
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
Parameter
Ratings
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
100
V
V
±20
TC = 25 °C
TA = 25 °C
TA = 25 °C
24
ID
(Note 1a)
(Note 4)
(Note 3)
7
A
mJ
W
-Pulsed
80
EAS
PD
Single Pulse Avalanche Energy
Power Dissipation
150
TC = 25 °C
TA = 25 °C
TA = 25 °C
38
Power Dissipation
(Note 1a)
(Note 1b)
2.1
1
Power Dissipation
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +150
°C
Thermal Characteristics
RθJC
RθJA
RθJA
Thermal Resistance, Junction to Case
3.3
60
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
(Note 1a)
(Note 1b)
°C/W
130
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ’’
Tape Width
12 mm
Quantity
82100L
FDMD82100L
Power 3.3 x 5
3000 units
1
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
www.fairchildsemi.com
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
100
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
I
D = 250 μA, referenced to 25 °C
70
mV/°C
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
VDS = 80 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
1
μA
±100
nA
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
1.0
1.7
-6
3.0
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
I
D = 250 μA, referenced to 25 °C
mV/°C
V
GS = 10 V, ID = 7 A
13.5
17.9
25
19.5
30
rDS(on)
gFS
Static Drain to Source On Resistance
Forward Transconductance
VGS = 4.5 V, ID = 5.7 A
VGS = 10 V, ID = 7 A, TJ = 125 °C
VDD = 5 V, ID = 7 A
mΩ
36
29
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
1130
173
8.1
1585
245
15
pF
pF
pF
Ω
VDS = 50 V, VGS = 0 V
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
0.1
1.8
3.6
Switching Characteristics
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
7.9
2.8
21
2.9
17
8
16
10
34
10
24
12
ns
ns
VDD = 50 V, ID = 7 A
V
GS = 10 V, RGEN = 6 Ω
Turn-Off Delay Time
Fall Time
ns
ns
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VGS = 0 V to 10 V
VGS = 0 V to 4.5 V
nC
nC
nC
nC
Qg(TOT)
VDD = 50 V
D = 7 A
I
Qgs
Qgd
3
2.3
Drain-Source Diode Characteristics
VSD
trr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
VGS = 0 V, IS = 7 A
(Note 2)
0.8
42
39
1.2
67
62
V
ns
nC
IF = 7 A, di/dt = 100 A/μs
Qrr
Reverse Recovery Charge
NOTES:
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R is determined by
θCA
θJA
θJC
the user's board design.
b. 130 °C/W when mounted on
a minimum pad of 2 oz copper
a. 60 °C/W when mounted on
a 1 in padof 2oz copper
2
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
o
3. E of 150 mJ is based on starting T = 25 C, L = 3 mH, I = 10 A, V = 90 V, V = 10 V. 100% tested at L = 0.1 mH, I = 31 A.
AS
J
AS
DD
GS
AS
4. Pulse Id refers to Figure.11 Forward Bias Safe Operation Area.
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
www.fairchildsemi.com
2
Typical Characteristics (N-Channel) TJ = 25 °C unless otherwise noted
80
60
40
20
0
5
4
3
2
1
0
VGS = 10 V
VGS = 6 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3 V
VGS = 4.5 V
VGS = 3.5 V
VGS = 4 V
VGS = 4 V
VGS = 3.5 V
VGS = 6 V
VGS = 4.5 V
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3 V
0
1
2
3
4
5
0
20
40
60
80
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
F i g u r e 2 . No rma li zed O n-Re si stan ce
vs Drain Current and Gate Voltage
2.4
100
ID = 7 A
PULSE DURATION = 80 μs
VGS = 10 V
DUTY CYCLE = 0.5% MAX
2.0
1.6
1.2
0.8
0.4
80
60
40
20
0
ID = 7 A
TJ = 125 o
C
TJ = 25 o
C
-75 -50 -25
0
25 50 75 100 125 150
2
4
6
8
10
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figure4. On-Resistance vs Gate to
Source Voltage
80
60
40
20
0
80
VGS = 0 V
TJ = 150 o
TJ = -55 o
C
TJ = 150 o
C
10
1
C
TJ = 25 o
C
TJ = 25 o
C
0.1
VDS = 5 V
TJ = -55 o
C
0.01
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0.001
1
2
3
4
5
6
7
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
www.fairchildsemi.com
3
Typical Characteristics (N-Channel) TJ = 25 °C unless otherwise noted
10
2000
1000
ID = 7 A
Ciss
8
Coss
VDD = 75 V
100
10
1
6
VDD = 50 V
VDD = 25 V
Crss
4
2
f = 1 MHz
GS = 0 V
V
0
0
3
6
9
12
15
18
0.1
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
100
40
30
20
10
0
RθJC = 3.3 oC/W
TJ = 25 oC
TJ = 100 o
VGS = 10 V
C
10
Limited by Package
TJ = 150 o
C
VGS = 4.5 V
1
0.001
0.01
0.1
1
10
100
25
50
75
100
125
150
TC, CASE TEMPERATURE (oC)
tAV, TIME IN AVALANCHE (ms)
F i g u r e 9 . U n c l a m p e d I n d u c t i v e
Switching Capability
Figure10.M a x i m u m C o n t i n u o u s D r a i n
Current vs Case Temperature
300
100
10000
THIS AREA
IS LIMITED
BY r
DS(on)
10 μs
10
1
1000
100
10
SINGLE PULSE
RθJC = 3.3 oC/W
T
C = 25 oC
100 μs
SINGLE PULSE
TJ = MAX RATED
1 ms
10 ms
DC
R
θJC = 3.3 o C/W
C = 25 o
T
C
0.1
0.01
CURVE BENT TO
MEASURED DATA
10-5
10-4
10-3
t, PULSE WIDTH (sec)
10-2
10-1
0.1
1
10
100 300
1
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure11. Forward Bias Safe
Operating Area
Figure12. Single Pulse Maximum
Power Dissipation
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
www.fairchildsemi.com
4
Typical Characteristics (N-Channel) TJ = 25 °C unless otherwise noted
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
PDM
0.05
0.02
0.01
0.1
t1
t2
NOTES:
0.01
0.001
SINGLE PULSE
ZθJC(t) = r(t) x RθJC
RθJC = 3.3 oC/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
10-5
10-4
10-3
10-2
10-1
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
www.fairchildsemi.com
5
Dimensional Outline and Pad Layout
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, spe-
cifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
https://www.fairchildsemi.com/package/packageDetails.html?id=PN_PQDE$-X12
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
www.fairchildsemi.com
6
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Datasheet contains the design specifications for product development. Specifications
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Datasheet contains preliminary data; supplementary data will be published at a later
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Rev. I68
©2014 Fairchild Semiconductor Corporation
FDMD82100L Rev.C1
www.fairchildsemi.com
7
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designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
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