NB7N017MMNR2G [ONSEMI]
3.3V SiGe 8-Bit Dual Modulus Programmable Divider/Prescaler with CML Outputs; 3.3V SiGe半导体的8位双模可编程分频器/预分频器带CML输出
| 型号： | NB7N017MMNR2G |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V SiGe 8-Bit Dual Modulus Programmable Divider/Prescaler with CML Outputs |
| 文件： | 总20页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB7N017M
3.3V SiGe 8−Bit Dual
Modulus Programmable
Divider/Prescaler with CML
Outputs
The NB7N017M is a high speed 8–bit dual modulus
programmable divider/prescaler with 16 mA CML outputs capable
of switching at input frequencies greater than 3.5 GHz. The CML
output structure contains internal 50 W source termination resistor to
http://onsemi.com
V
. The device generates 400 mV output amplitude with 50 W
CC
receiver resistor to V . This I/O structure enables easy
CC
implementation of the NB7N017M in 50 W systems.
The differential inputs contain 50 W termination resistors to VT
pads and all differential inputs accept RSECL, ECL, LVDS,
LVCMOS, LVTTL, and CML.
1
52
QFN−52
MN SUFFIX
CASE 485M
Internally, the NB7N017M uses a > 3.5 GHz 8–bit programmable
down counter. A select pin, SEL, is used to select between two
words, Pa[0:7] and Pb[0:7], that are stored in REGa and REGb
respectively. Two parallel load pins, PLa and PLb, are used to load
the level triggered programming registers, REGa and REGb,
respectively. A differential clock enable, CE, pin is available.
The NB7N017M offers a differential output, TC. Terminal count
output, TC, goes high for one clock cycle when the counter has
reached the all zeros state. To reduce output phase noise, TC is
retimed with the rising edge triggered latches.
MARKING DIAGRAM*
52
1
NB7N
017M
AWLYYWW
• Maximum Input Clock Frequency > 3.5 GHz Typical
• Differential CLK Clock Input
NB7N017M = Device Code
A
= Assembly Site
= Wafer Lot
= Year
WL
YY
WW
• Differential CE Clock Enable Input
• Differential SEL Word Select Input
= Work Week
• 50 W Internal Input and Output Termination Resistors
• Differential TC Terminal Count Output
*For additional marking information, refer to
Application Note AND8002/D.
• All Outputs 16 mA CML with 50 W Internal Source Termination
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
to V
CC
• All Single–Ended Control Pins CMOS and PECL/NECL
Compatible
*For additional information on our Pb−Free strategy
and soldering details, please download the ON Semi-
conductor Soldering and Mounting Techniques Ref-
erence Manual, SOLDERRM/D.
• Counter Programmed Using One of Two Single−Ended Words,
Pa[0:7] and Pb[0:7], Stored in REGa and REGb
• REGa and REGb Implemented with Level Triggered Latch
• Compatible with Existing 3.3 V LVEP, EP, and SG Devices
• Ability to Program the Divider without Disturbing Current Settings
• Positive CML Output Operating Range: V = 3.0 V to 3.465 V
CC
with V = 0 V
EE
• Negative CML Output Operating Range: V = 0 V
CC
with V = –3.0 V to –3.465 V
EE
• V Reference Voltage Output
BB
• CML Output Level: 400 mV Peak−Peak Output with 50 W Receiver
Resistor to V
CC
• Pb−Free Packages are Available*
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
November, 2004 − Rev. 0
NB7N017M/D
NB7N017M
Exposed Pad (EP)
V
39
38
37
36
35
34
V
EE
1
2
CC
PLb
Pb0
PLa
Pa0
Pa1
Pa2
3
Pb1
Pb2
4
5
V
V
6
CC
CC
7
33 Pb3
Pa3
NB7N017M
V
V
8
32
31
30
EE
EE
9
Pb4
Pb5
Pa4
Pa5
Pa6
Pa7
NC
10
11
12
13
29 Pb6
Pb7
NC
28
27
Figure 1. Pinout (Top View)
http://onsemi.com
2
NB7N017M
Table 1. PIN DESCRIPTION
Default Single/Differential
State
(Notes 1 and 2)
Pin Name
CLK
I/O
Description
ECL, CML, LVCMOS,
LVDS, LVTTL Input
−
Differential
Clock
CE
ECL, CML, LVCMOS,
LVDS, LVTTL Input
−
Differential
Single
Clock Enable
MR
CMOS, ECL Input
Low
Asynchronous Master Reset: Counter set to 0000 0000 to
reload at next CLK pulse, REGa and REGb = 1111 1111 and
TC = 1.
SEL
ECL, CML, LVCMOS,
LVDS, LVTTL Input
−
Differential
Single
Divide Select
PLa, PLb
TC
CMOS, ECL Input
Low
−
Parallel Load Counter Latch from Pa[0:7], Pb[0:7] (Level
Triggered)
CML Output
Differential
Single
Terminal Count, 16 mA CML output with 50 W Source
Termination to V (Note 5)
CC
Pa[0:7], Pb[0:7]
CMOS, ECL Input
High
Counter Program Pins. CMOS and PECL/NECL compatible
Pa7 = MSB, Pb7 = MSB
V
V
Power
Power
−
−
Positive Supply
CC
−
−
Negative Supply
EE
VTCLK, VTCLK,
VTSEL, VTSEL
VTCE, VTCE
Termination
−
Differential
50 W Internal Input Termination Resistor (Note 6)
V
Output
N/A
−
−
−
−
CMOS/ECL Reference Voltage Output
No Connect (Note 4)
BB
−
NC
EP
−
−
Exposed Pad (Note 3)
1. All high speed inputs and outputs are differential to improve performance.
2. All single−ended inputs are CMOS and NECL/ECL compatible.
3. All V and V pins must be externally connected to external power supply voltage to guarantee proper device operation. The thermally
CC
EE
exposed pad (EP) on package bottom (see case drawing) must be attached to a heat−sinking conduit. Exposed pad is bonded to the lowest
voltage potential, V
.
EE
4. The NC pins are electrically connected to the die and must be left open.
5. CML outputs require 50 W receiver termination resistor to V for proper operation.
CC
6. In the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied
then the device will be susceptible to self−oscillation.
http://onsemi.com
3
NB7N017M
Table 2. CE Truth Table
CE
Table 3. SEL Truth Table
Clock Status
SEL
Active Register
LOW
HIGH
Clock Disabled
Clock Enabled
LOW
HIGH
REGa
REGb
Table 4. Register Programming Values for Various Divide Ratios
Pa7/Pb7
Pa6/Pb6 Pa5/Pb5 Pa4/Pb4 Pa3/Pb3 Pa2/Pb2 Pa1/Pb1
Pa0/Pb0
Divide By
0
0
0
0
−
−
1
1
1
0
0
0
0
−
−
1
1
1
0
0
0
0
−
−
1
1
1
0
0
0
0
−
−
1
1
1
0
0
0
0
−
−
1
1
1
0
0
0
0
−
−
1
1
1
0
0
1
1
−
−
0
1
1
0
1
0
1
−
−
1
0
1
undefined
2
3
4
−
−
254
255
256
Table 5. Function Table
MR Pla PLb SEL CE CLK
Function
H
X
X
X
X
X
Master Reset (Counter programmed to 0000 0000, REGa and REGb programmed to 1111 1111 and
TC to 1)
L
L
L
L
L
H
L
L
L
X
L
H
L
X
X
L
X
X
H
H
L
X
X
Z
Z
X
REGa is transparent to Pa[0:7]
REGb is transparent Pb[0:7]
Count; At TC pulse, load counter from REGa
Count; At TC pulse, load counter from REGb
Hold
L
H
X
X
X − Don’t Care
H − HIGH
L − LOW
Z − Rising Edge
http://onsemi.com
4
NB7N017M
V
CC
R
1
R
2
Q
Q
INTERNAL
INTERNAL
CLK
CLK
R
T
= 50 W
R = 50 W
T
VTCLK
VTCLK
V
EE
Figure 2. Input Structure
V
CC
R
T
= 50 W
R = 50 W
T
Q
Q
D
D
INTERNAL
INTERNAL
16 mA
V
EE
Figure 3. Output Structure
http://onsemi.com
5
NB7N017M
CLK
CLK
CE
CLK_INT
CLK_INT
GENERATOR
TC_INT
Counter_State [7:0]
8−BIT
COUNTER
TC
TC
CE
DFF
MR
TC
GENERATOR
MUX_OUT[7:0]
CLK_INT
MR
MR
SEL
SEL
TCLD MUX
Pa_INT[7:0]
Pb_INT[7:0]
8−BIT REGa
8−BIT REGb
PLb
PLa
Pa[7:0]
Pb[7:0]
Figure 4. Block Diagram
Table 6. Interface Options
CLK INPUT interfacing options
CLK INPUT INTERFACING OPTIONS
Connect VTCLK and VTCLK to V
CML
LVDS
CC
Connect VTCLK and VTCLK together
AC−COUPLED
Bias VTCLK and VTCLK Inputs within (VIHCMR)
Common Mode Range
RSECL, PECL, NECL
LVTTL, LVCMOS
Standard ECL Termination Techniques or connect VTCLK and
VTCLK to V
TT
An Entered Voltage Should be Applied to the unused
Complementary Differential Input. Nominal Voltage is 1.5 V for
LVTTL and V /2 for LVCMOS Inputs.
CC
Table 7. ATTRIBUTES
Characteristic
Value
Internal Input Pulldown Resistor (MR, PLa, PLb)
Internal Input Pullup Resistor (Pa[0:7], Pb[0:7])
75 k to V
75 k to V
EE
CC
ESD Protection
Human Body Model
Machine Model
Charged Device Model
>500 V
>10 V
>2 kV
Moisture Sensitivity (Note 7)
Flammability Rating
Transistor Count
Level 2
UL 94 V−0 @ 0.125 in
1914
Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
7. For additional information, see Application Note AND8003/D.
http://onsemi.com
6
NB7N017M
Table 8. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
3.6
Units
V
Positive Power Supply
Negative Power Supply
V
V
= 0 V
= 0 V
V
V
CC
EE
I
EE
V
V
-3.6
CC
Positive Input
Negative Input
V
V
= 0 V
= 0 V
V ≤ V
3.6
-3.6
V
V
EE
I
CC
V ≥ V
CC
I
EE
V
Differential Input Voltage
|CLK − CLK|
V
− V w 2.8 V
2.8 V
V
INPP
CC
EE
I
I
I
Input Current through R (50 W Resistor)
Continuous
Surge
25
50
mA
in
T
Output Current
Continuous
Surge
25
50
mA
mA
out
BB
V
BB
Sink/Source
$0.5
mA
°C
T
A
Operating Temperature Range
Storage Temperature Range
−40 to +85
T
stg
−65 to +150
°C
q
Thermal Resistance (Junction−to−Ambient)
(Note 8)
0 lfpm
500 lfpm
52 QFN
52 QFN
25 − 32
20 − 27
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
2S2P (Note 8)
52 QFN
4 − 15
°C/W
°C
JC
T
sol
Wave Solder
< 2 to 3 seconds
265
Maximumratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values
(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage
may occur and reliability may be affected.
8. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
http://onsemi.com
7
NB7N017M
Table 9. DC CHARACTERISTICS, POSITIVE CML OUTPUT V = 3.0 V to 3.465 V; V = 0 V (Note 11)
CC
EE
−40°C
Typ
25°C
Typ
200
85°C
Typ
200
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Positive Power Supply Current
Output HIGH Voltage (Note 12)
Unit
mA
mV
I
170
200
230
170
230
170
230
CC
V
OH
V
V
V
CC
V
V
CC
V
CC
V
V
CC
V
CC
CC
CC
CC
CC
−40
−10
−40
−10
−40
−10
V
OL
Output LOW Voltage (Note 12)
V
V
V
V
V
CC
V
mV
CC
CC
CC
CC
CC
−400 −330
−400 −330
−400 −330
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 19, 21)
V
th
Input Threshold Reference Voltage
Range (Note 9)
V
V
V
V
V
V
CC
−75
mV
EE
CC
EE
CC
EE
+1125
−75
+1125
−75
+1125
V
V
Single−Ended Input HIGH Voltage
Single−Ended Input LOW Voltage
V
+75
V
V
+75
V
V
+75
V
CC
mV
mV
IH
th
CC
th
CC
th
V
V
−75
V
V
−75
V
V
th
−75
IL
EE
th
EE
th
EE
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 20, 22)
V
V
V
Differential Input HIGH Voltage
V
V
V
V
V
V
V
V
V
mV
mV
mV
IHD
EE
CC
EE
CC
EE
CC
+1200
+1200
+1200
Differential Input LOW Voltage
V
EE
V
EE
V
EE
ILD
CC
−75
CC
−75
CC
−75
Input Common Mode Range
(Differential Cross−Point Voltage)
(Note 10)
V
V
CC
V
V
CC
V
V
CC
−50
CMR
EE
EE
EE
+1200
−50
+1200
−50
+1200
V
V
Differential Input Voltage
V
V
V
V
V
V
CC
mV
ID
EE
CC
EE
CC
EE
+100
+100
1840
45
+100
1820
45
Output Voltage Reference @ −100 mA
Internal Input Termination Resistor
Internal Output Resistor
1840
45
1970 2100
1960
50
2100
55
1970 2100
mV
W
BB
R
R
50
50
55
55
50
50
55
55
TIN
45
45
50
55
45
W
TOUT
I
IH
Input HIGH Current
CLK, CE, SEL
mA
0
0
−50
7
15
60
0
0
0
−50
7
15
60
0
0
0
−50
7
15
60
0
MR, PLa, PLb
30
30
30
Pa[0:7], Pb[0:7]
−10
−10
−10
I
IL
Input LOW Current
CLK, CE, SEL
MR, PLa, PLb
mA
−0.5
0
−50
0.5
60
0
−0.5
0
−50
0.5
60
0
−0.5
0
−50
0.5
60
0
20
−20
20
−20
20
−20
Pa[0:7], Pb[0:7]
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
9. V is applied to the complementary input when operating in single−ended mode.
th
CMR
10.V
minimum varies 1:1 with V , V
maximum varies 1:1 with V . The V range is referenced to the most positive side of the
EE
CMR
CC
CMR
differentialinput signal.
11. Input and output parameters vary 1:1 with V . V can vary +0.925 V to −0.165 V.
CC EE
12.All loading with 50 W to V
.
CC
13.V
min varies 1:1 with V , V
max varies 1:1 with V . The V range is referenced to the most positive side of the differential
IHCMR
IHCMR
input signal.
EE IHCMR
CC
http://onsemi.com
8
NB7N017M
Table 10. DC CHARACTERISTICS, NEGATIVE CML OUTPUT V = 0 V; V = −3.465 V to −3.0 V (Note 16)
CC
EE
−40°C
Typ
25°C
Typ
200
85°C
Typ
200
Min
Max
230
Min
Max
Min
Max
Symbol
Characteristic
Positive Power Supply Current
Output HIGH Voltage (Note 17)
Unit
mA
mV
I
170
200
170
230
170
230
CC
V
OH
V
V
V
CC
V
V
CC
V
CC
V
V
CC
V
CC
CC
CC
CC
CC
−40
−10
−40
−10
−40
−10
V
OL
Output LOW Voltage
(Note 17)
V
V
V
V
V
CC
−400
V
mV
CC
CC
CC
CC
CC
−400
−330
−400
−330
−330
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 19, 21)
V
th
V
IH
V
IL
Input Threshold Reference Voltage
Range (Note 14)
V
V
V
V
V
V
CC
mV
mV
mV
EE
CC
EE
CC
EE
+1125
−75
+1125
−75
+1125
−75
Single−Ended Input HIGH Voltage
V
+75
V
CC
V
+75
V
CC
V
+75
V
CC
th
th
th
Single−Ended Input LOW Voltage
V
EE
V
−75
V
EE
V
−75
V
EE
V
th
−75
th
th
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 20, 22)
V
V
V
Differential Input HIGH Voltage
V
V
V
V
V
V
V
V
V
mV
mV
mV
IHD
EE
CC
EE
CC
EE
CC
+1200
+1200
+1200
Differential Input LOW Voltage
V
EE
V
EE
V
EE
ILD
CC
−75
CC
−75
CC
−75
Input Common Mode Range
(Differential Cross−Point Voltage)
(Note 15)
V
V
CC
V
V
CC
V
V
CC
−50
CMR
EE
EE
EE
+1200
−50
+1200
−50
+1200
V
V
Differential Input Voltage
V
V
V
+100
V
V
+100
V
CC
mV
ID
EE
+100
CC
EE
CC
EE
Output Voltage
Reference @ −100 mA
−1460 −1330 −1200 −1460 −1330 −1200 −1460 −1330 −1200 mV
BB
R
R
Internal Input Termination Resistor
Internal Output Resistor
Input HIGH Current
45
45
50
50
55
55
45
45
50
50
55
55
45
45
50
50
55
55
W
W
TIN
TOUT
I
IH
mA
CLK, CE, SEL
0
0
−50
7
15
60
0
0
0
−50
7
15
60
0
0
0
−50
7
15
60
0
MR, PLa, PLb
Pa[0:7], Pb[0:7]
30
30
30
−10
−10
−10
I
IL
Input LOW Current
mA
CLK, CE, SEL
MR, PLa, PLb
Pa[0:7], Pb[0:7]
−0.5
0
−50
0.5
60
0
−0.5
0
−50
0.5
60
0
−0.5
0
−50
0.5
60
0
20
−20
20
−20
20
−20
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
14.V is applied to the complementary input when operating in single−ended mode.
th
15.V
minimum varies 1:1 with V , V
maximum varies 1:1 with V . The V
range is referenced to the most positive side of the
CMR
EE
CMR
CC
CMR
differentialinput signal.
16.Input and output parameters vary 1:1 with V
.
CC
17.All loading with 50 W to V
.
CC
18.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
http://onsemi.com
9
NB7N017M
Table 11. AC CHARACTERISTICS V = 0 V; V = −3.465 V to −3.0 V or V = 3.0 V to 3.465 V; V 0 V (Note 19)
EE =
CC
EE
CC
−40°C
Typ
25°C
Typ
400
85°C
Min
Max
Min
Max
Min
Typ
Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude @ B 2 Mode
(See Figure 5)
300
400
300
300
400
mV
OUTPP
f
in
= 3.5 GHz
t
t
,
Propagation Delay to Output Differential
ps
PLH
CLK to TC
MR to TC
435
100
555
500
455
100
575
500
475
100
595
500
PHL
t
RMS Random Clock Jitter f = 3.5 GHz
2.5
2500
65
3.0
2500
65
3.0
2500
65
ps
mV
ps
JITTER
in
(See Figure 5)
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 20)
100
25
100
25
100
25
INPP
t
r
t
f
Output Rise/Fall Times
(20% − 80%)
45
45
45
t
s
Setup Time
(Figure 23)
Pa[7:0] to PLa 3750
Pb[7:0] to PLb 4500
2500
2000
30
3750
4500
400
2500
2000
30
3750
4500
400
2500
2000
30
ps
CE to CLK
400
300
SEL to CLK
120
300
120
300
120
PLa to CLK 2500
PLb to CLK 3250
Pa[7:0] to CLK 4750
Pb[7:0] to CLK 3000
2000
2750
3500
2500
2500
3250
4750
3000
2000
2750
3500
2500
2500
3250
4750
3000
2000
2750
3500
2500
t
H
Hold Time
(Figure 23)
PLa to Pa[7:0] −1500 −2700
PLb to Pb[7:0] −1250 −1900
−1500 −2700
−1250 −1900
−1500 −2700
−1250 −1900
ps
CLK to CE
450
0
40
450
0
40
450
0
40
CLK to SEL
−110
−110
−110
CLK to PLa −1750 −1900
CLK to PLb −2250 −2700
CLK to PLb[7:0] −2250 −3200
CLK to PLb[7:0] −2000 −2500
−1750 −1900
−2250 −2700
−2250 −3200
−2000 −2500
−1750 −1900
−2250 −2700
−2250 −3200
−2000 −2500
t
t
t
Device−to−Device (Note 21)
40
85
75
40
75
40
75
ps
ps
ps
SKEW
Minimum Pulse Width
Reset Recovery
MR
250
250
85
250
85
PW
MR to TC 3000
2500
3000
2500
3000
2500
RR
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
19.Measuredusing a 400 mV source, 50% duty cycle clock source at f = 1 GHz unless stated otherwise. All loading with 50 W to V . Input edge
in
CC
rates 40 ps (20% − 80%).
20.V (MAX) cannot exceed V − V .
EE
INPP
CC
21.Device−to−Device skew for identical transitions at identical V levels.
CC
400
4
3
2
1
0
V
OUTPP
300
200
100
0
RMS Jitter
0
0.5
1
1.5
2
2.5
3
3.5
4
INPUT FREQUENCY (MHz)
Figure 5. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs. Input Frequency (fin)
@ Ambient Temperature (Typical)
http://onsemi.com
10
NB7N017M
Application Information
minimum input swing of 100 mV and the maximum input
swing of 450 mV. Within these conditions, the input
All NB7N017M inputs can accept PECL, CML, LVTTL,
LVCMOS and LVDS signal levels. The limitations for
differential input signal (LVDS, PECL, or CML) are
voltage can range from V to 1.2 V. Examples interfaces
CC
are illustrated below in a 50 W environment (Z = 50 W).
V
CC
V
CC
50 W 50 W
7N017M
Q
CLK
Z
Z
50 W
50 W
V
V
7N017M
TCLK
V
V
CC
CC
TCLK
Q
CLK
V
EE
V
EE
Figure 6. CML to CML Interface
V
CC
V
CC
50 W
CLK
Z
PECL
Driver
50 W
50 W
V
TCLK
7N017M
V
V
*
*
BIAS
BIAS
V
TCLK
50 W
RecommendedR Values
T
Z
V
CC
R
T
CLK
R
T
R
T
5.0 V 290 W
V
EE
V
V
EE
EE
3.3 V 150 W
2.5 V 80 W
Figure 7. PECL to CML Receiver Interface
*V
BIAS
is within V
Range.
CMR
V
CC
V
CC
CLK
Z
LVDS
Driver
50 W
50 W
V
V
TCLK
7N017M
TCLK
Z
CLK
V
EE
V
EE
Figure 8. LVDS to CML Receiver Interface
http://onsemi.com
11
NB7N017M
V
CC
V
CC
CLK
Z
50 W
LVTTL/
LVCMOS
Driver
No Connect
V
V
TCLK
7N017M
TCLK
No Connect
50 W
V
REF
Recommended V
Values
REF
CLK
V
REF
LVCMOS
LVTTL
V
* V
CC
EE
V
EE
V
CC
2
1.5 V
Figure 9. LVCMOS/LVTTL to CML Receiver Interface
Table 12. OPERATION TABLE
MR
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pa
PLa
Pb
PLb
X
H
H
L
SEL
X
X
X
L
CE
X
CLK
X
L
CLK_INT
TC_INT
TC
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
XXXXXXXX
00000101
x
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
XXXXXXXX
00000100
X
H
H
H
L
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
00000101
00000100
L
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
H
L
L
X
X
X
X
X
X
X
X
X
X
X
L
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
X
X
X
X
X
X
X
X
X
X
X
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
L
L
X − Don’t Care
H − HIGH
L − LOW
http://onsemi.com
12
NB7N017M
Table 12. OPERATION TABLE
MR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pa
PLa
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Pb
PLb
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
SEL
H
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
H
X
X
X
L
CE
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
CLK
H
L
CLK_INT
TC_INT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
TC
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000010
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
00000001
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
H
L
L
H
H
L
H
L
H
L
H
H
H
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
H
L
H
L
H
L
H
L
H
L
H
L
X
X
X
X
L
H
L
H
L
H
L
H
L
L
H
L
H
L
X
X
X
X
L
H
L
H
L
H
L
H
L
L
H
L
H
L
X
X
H
H
X − Don’t Care
H − HIGH
L − LOW
http://onsemi.com
13
NB7N017M
MR
Pa[7:0]
PLa
05
XX
02
XX
Pa_INT[7:0]
05
02
01
Pb[7:0]
PLb
04
XX
XX
Pb_INT[7:0]
04
01
SEL
CE
CLK
CLK_INT
TC_INT
TC
Figure 10. Device Timing Diagram for Table 12
MR
CLK
CE
CLK_INT
Figure 11. Timing Diagram for CE Input
http://onsemi.com
14
NB7N017M
MR
delay
CLK
PLa
0B
Pa[7:0]
TC[7:0]
d=12
d=12
d=12
Figure 12. Timing Diagram for PLa / PLb Inputs
(SEL is Low)
MR
delay
CLK
PLa
(hex)
0B
Pa[7:0]
TC[7:0]
d=12
d=12
d=256
d=256
Figure 13. Timing Diagram for PLa / PLb Inputs
(Before Critical Rising Edge of CLK)
(SEL is Low)
MR
delay
CLK
PLa
(hex)
0B
Pa[7:0]
TC[7:0]
d=256
d=12
d=256
d=256
Figure 14. Timing Diagram for PLa / PLb Inputs
(After Critical Rising Edge of CLK)
(SEL is Low)
http://onsemi.com
15
NB7N017M
MR
delay
CLK
SEL
Pa[7:0]
Pb[7:0]
PLa
03
02
PLb
d=4
d=4
d=4
d=3
d=3
TC[7:0]
Figure 15. Timing Diagram for SEL Input
(Before Critical Rising Edge of CLK)
MR
delay
CLK
SEL
Pa[7:0]
Pb[7:0]
PLa
03
02
PLb
d=4
d=4
d=4
d=4
d=3
TC[7:0]
Figure 16. Timing Diagram for SEL Input
(After Critical Rising Edge of CLK)
MR
CLK
Pa[7:0]
PLa
Pa_INT[7:0]
01
02
03
2
04
05
5
06
6
07
43
08
255
7
Pb/PLb have the same functionality as Pa/PLa
103
255
201
255
10
151
27
176
Pb[7:0]
PLb
Pb_INT[7:0]
201
151
27
43
MUX_OUT is the output of the internal MUX
SEL
151
MUX_INT[7:0] 255
2
5
27
43
Figure 17. Timing Diagram Relating PLa, PLb, Pa(0:7), Pb(0:7)
http://onsemi.com
16
NB7N017M
CLK
V
V
= V (CLK) − V (CLK)
IH IL
INPP
CLK
TC
= V (TC) − V (TC)
OUTPP
OH
OL
TC
t
PHL
t
PLH
Figure 18. AC Reference Measurement
D
V
th
D
D
D
V
th
Figure 19. Differential Input Driven
Figure 20. Differential Inputs Driven
Differentially
Single−Ended
V
V
CC
CC
V
V
IHDmax
V
V
V
V
thmax
CMmax
IHmax
ILDmax
ILmax
V
= V − V
IHD ILD
ID
V
IH
V
th
V
IL
V
CMR
V
IHDtyp
ILDtyp
V
th
V
V
V
IHmin
V
V
IHDmin
V
V
thmin
CMmax
ILmin
ILDmin
GND
GND
Figure 21. Vth Diagram
Figure 22. VCMR Diagram
http://onsemi.com
17
NB7N017M
CLK
+
−
Setup Time
t
s
−
+
Hold Time
t
h
Figure 23. Setup and Hold Time
V
CC
V
CC
NB7N017M
Receiver
Device
50
50
50
50
W
W
W
W
Q
D
D
Q
Figure 24. Typical Termination for 16 mA Output Drive and Device Evaluation
ORDERING INFORMATION
†
Device
NB7N017MMN
Package
Shipping
QFN−52
260 Units / Tray
260 Units / Tray
NB7N017MMNG*
QFN−52
(Pb−Free)
NB7N017MMNR2
QFN−52
2000 / Tape & Reel
2000 / Tape & Reel
NB7N017MMNR2G*
QFN−52
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Future Product − Contact factory for availability.
http://onsemi.com
18
NB7N017M
PACKAGE DIMENSIONS
QFN−52, 8 x 8 mm, 0.5 mm Pitch
Quad Flat No Lead Package
CASE 485M−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
D
A
B
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
MILLIMETERS
E
DIM MIN
MAX
1.00
0.05
0.80
A
A1
A2
A3
b
0.80
0.00
0.60
2X
0.20 REF
0.15
C
0.23
0.28
6.80
D
8.00 BSC
D2
E
6.50
6.50
2X
8.00 BSC
0.15
C
E2
e
6.80
0.50 BSC
A2
K
0.20
0.35
−−−
0.10
0.08
C
C
L
0.45
A
A3 REF
A1
SEATING PLANE
C
D2
14
26
27
13
52 X L
E2
39
1
52
40
52 X K
b
NOTE 3
52 X
e
0.10 C A
0.05
B
C
http://onsemi.com
19
NB7N017M
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NB7N017M/D
相关型号：
©2020 ICPDF网 联系我们和版权申明