NB7NPQ1204EMMUTWG [ONSEMI]
3.3 V USB 3.1 Gen-2 10 Gbps Quad Channel / Dual Port Linear Redriver;
| 型号： | NB7NPQ1204EMMUTWG |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V USB 3.1 Gen-2 10 Gbps Quad Channel / Dual Port Linear Redriver |
| 文件： | 总12页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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MARKING
DIAGRAM
3.3 V USB 3.1 Gen-2
10ꢀGbps Quad Channel /
Dual Port Linear Redriver
NB7N
204E
ALYW
UQFN34
NB7NPQ1204EM
CASE 523BR
NB7N204E = Specific Device Code
Description
A
L
= Assembly Location
= Wafer Lot
The NB7NPQ1204EM is a high performance 2−Port linear redriver
designed for USB 3.1 Gen 1 and USB 3.1 Gen 2 applications that
supports both 5 Gbps and 10 Gbps data rates. Signal integrity degrades
from PCB traces, transmission cables, and inter−symbol interference
(ISI). The NB7NPQ1204EM compensates for these losses by
engaging varying levels of equalization at the input receiver, and flat
gain amplification on the output transmitter.
The NB7NPQ1204EM offers programmable equalization and flat
gain for each independent channel to optimize performance over
various physical mediums.
The NB7NPQ1204EM contains an automatic receiver detect
function which will determine whether the output is active. The
receiver detection loop will be active if the corresponding channel’s
signal detector is idle for a period of time. The channel will then move
to Unplug Mode if a load is not detected, or it will return to Low Power
Mode (Slumber mode) due to inactivity.
Y
W
= Year
= Work Week
ORDERING INFORMATION
†
Device
NB7NPQ1204EMMUTWG UQFN34 5000 / Tape
(Pb−Free) & Reel
Package Shipping
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
The NB7NPQ1204EM comes in a 2.5 x 4.5 x 0.55 mm UQFN34
package and is specified to operate across the entire industrial
temperature range, –40°C to 85°C.
Features
• 3.3 V ± ±0.3 V Power Supply
• 5 Gbps & 10 Gbps Serial Link with Linear Amplifier
• Device Supports USB 3.1 Gen 1 and USB 3.1 Gen 2 Data Rates
• Automatic Receiver Detection
• Integrated Input and Output Termination
• Pin Adjustable Receiver Equalization and Flat Gain
Typical Applications
• 100−W Differential CML I/O’s
• USB3.1 Type−A and Type−C Signal Routing
• Mobile Phone and Tablet
• Computer, Laptop and Notebook
• External Storage Device
• Docking Station and Dongle
• Active Cable, Back Planes
• Gaming Console, Smart T.V.
• Auto Slumber Mode for Adaptive Power Management
• Hot−Plug Capable
• ESD Protection ± 4 kV HBM
• Operating Temperature Range Industrial:
−40°C to +85°C
• Package: UQFN34, 2.5 x 4.5 x 0.55 mm
• This is a Pb−Free Device
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
September, 2022 − Rev. 1
NB7NPQ1204EM/D
NB7NPQ1204EM
EQA
FGA
EN_AB
A_RX+
A_TX+
Receiver/
Equalizer
Driver
A_RX−
A_TX−
B_TX+
B_RX+
Receiver/
Driver
Equalizer
B_TX−
B_RX−
EQB
FGB
FGC
EQC
C_RX−
C_RX+
C_TX−
Receiver/
Equalizer
Driver
C_TX+
D_TX−
D_RX−
Receiver/
Equalizer
Driver
FGD
D_TX+
D_RX+
EQD
EN_CD
Figure 1. Logic Diagram of NB7NPQ1204EM
Figure 2. UQFN34 Package Pinout (Top View)
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2
NB7NPQ1204EM
Table 1. PIN DESCRIPTION
Pin Number
Pin Name
A_RX+
A_RX−
GND
Type
Description
1
INPUT Channel A Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled in
system. UFP/DFP transmitter should provide this capacitor.
2
3, 10, 10, 27
GND
Reference Ground. GND pins must be externally connected to power supply ground to guarantee
proper operation.
4
5
B_TX−
B_TX+
FGC
OUTPUT Channel B Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in system.
6
INPUT DC flat gain for channel C. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down.
INPUT EQ select for channel C. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down.
7
EQC
8
C_RX+
C_RX−
D_TX−
D_TX+
INPUT Channel C Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled in
system. UFP/DFP transmitter should provide this capacitor.
9
11
12
13, 17
14
15
16
OUTPUT Channel D Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in system.
VDD_CD POWER 3.3 V power supply for Channel C and D. VDD pins must be externally connected to power supply.
EQD
FGD
INPUT EQ select for channel D. 4−level input pin. Internal 100k−W pull−up and 200 k−W pull−down.
INPUT DC flat gain for channel D. 4−level input pin. Internal 100k−W pull−up and 200 k−W pull−down.
EN_CD
INPUT Channel CD Enable. Internal 300k−W pull−up. High−Channel is in normal operation. Low−Channel is
in power down mode.
18
19
D_ RX+
D_ RX−
C_TX−
C_TX+
FGB
INPUT Channel D Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled in
system. UFP/DFP transmitter should provide this capacitor.
21
OUTPUT Channel C Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in system.
22
23
INPUT DC flat gain for channel B. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down.
INPUT EQ select for channel B. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down.
24
EQB
25
B_ RX+
B_ RX−
A_TX−
A_TX+
INPUT Channel B Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled in
system. UFP/DFP transmitter should provide this capacitor.
26
28
OUTPUT Channel A Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in system.
29
30, 34
31
VDD_AB POWER 3.3 V power supply for Channel A and B. VDD pins must be externally connected to power supply.
EQA
FGA
INPUT EQ select for channel A. 4−level input pin. Internal 100k−W pull−up and 200k−W pull−down.
INPUT DC flat gain for channel A. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down.
32
33
EN_AB
INPUT Channel AB Enable. Internal 300 k−W pull−up. High−Channel is in normal operation. Low−Channel is
in power down mode.
EP
GND
GND
Exposed Pad (EP). EP on the package bottom is thermally connected to the die for improved heat
transfer out of the package. The exposed pad is electrically connected to the die and must be
soldered to GND on the PC board.
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NB7NPQ1204EM
Power Management
Table 3. EQUALIZATION SETTING
The NB7NPQ1204EM has an adaptive power
management feature in order to minimize power
consumption. When the receiver signal detector is idle, the
corresponding channel will change to low power slumber
mode. Accordingly, both channels will move to low power
slumber mode individually.
While in the low power slumber mode, the receiver signal
detector will continue to monitor the input channel. If a
channel is in low power slumber mode, the receiver
detection loop will be active again. If a load is not detected,
then the channel will move to Device Unplug Mode and
continuously monitor for the load. When a load is detected,
the channel will return to Low Power Slumber Mode and
receiver detection will be active again per 6 ms.
EQ A/B/C/D are the selection pins for the equalization.
EQA/B/C/D
Equalizer Setting (dB)
@2.5 GHz
@5 GHz
11.5
L (Tie 0−W to GND)
R (Tie Rext to GND)
F (Leave Open)
5.0
2.7
4.0
6.5
7.4
9.9 (Default)
13.1
H (Tie 0−W to VDD)
Table 4. FLAT GAIN SETTING
FGA/B/C/D are the selection pins for the DC gain.
FGA/B/C/D
Flat Gain Settings (dB)
L (Tie 0−W to GND)
R (Tie Rext to GND)
F (Leave Open)
−1.2
0
Table 2. OPERATING MODES
+1.0 (Default)
+2.0
Mode
R
R
OUT
IN
H (Tie 0−W to VDD)
PD
67 k−W to GND
High−Z
High−Z
Table 5. CHANNEL ENABLE SETTING
EN_AB / EN_CD are the channel enable pins for channels A&B
and C&D respectively.
Unplug Mode
40 k−W to VDD
40 k−W to VDD
Low Power
Slumber Mode
50−W to VDD
EN
0
Channel Enable Setting
Disabled
Active
50−W to VDD
50−W to VDD
1
Enabled (Default)
Table 6. ATTRIBUTES
Parameter
ESD Protection
Human Body Model
Charged Device Model
± 4 kV
> 1.5 kV
Moisture Sensitivity, Indefinite Time Out of Dry pack (Note 1)
Flammability Rating
Level 1
UL 94 V−O @ 0.125 in
81034
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test
1. For additional information, see Application Note AND8003/D.
Table 7. ABSOLUTE MAXIMUM RATINGS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
VDD
Min
−0.5
−0.5
−0.5
−25
Max
Unit
V
Supply Voltage (Note 2)
4.6
Voltage range at any input or output terminal
Differential I/O
LVCMOS inputs
V
V
+ 0.5
V
DD
DD
+ 0.5
V
Output Current
+25
mA
W
Power Dissipation, Continuous
1.2
150
125
34
Storage Temperature Range, T
−65
°C
°C
°C/W
°C
SG
Maximum Junction Temperature, T
J
Junction−to−Ambient Thermal Resistance @ 500 lfm, Ø (Note 3)
JA
Wave Solder, Pb−Free, T
265
SOL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. All voltage values are with respect to the GND terminals.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB7NPQ1204EM
Table 8. RECOMMENDED OPERATING CONDITIONS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
Min
3.0
−40
75
Typ
Max
3.6
Unit
V
V
DD
Main power supply
3.3
T
A
Operating free−air temperature
AC coupling capacitor
Industrial Temperature Range
+85
265
°C
nF
C
100
AC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 9. POWER SUPPLY CHARACTERISTICS and LATENCY
Typ
(Note 4)
Symbol
Parameter
Test Conditions
Min
Max
3.6
Unit
V
VDD
Supply Voltage
3.0
3.3
IDD
Active mode current EN_AB & EN_CD = 1, 10 Gbps, compliance test pattern
235
334
1.3
mA
mA
Active
LPSlumber
IDD
Low Power Slumber EN_AB & EN_CD = 1, no input signal longer than TLP-
0.8
mode current
Slumber
IDD
Unplug mode current EN_AB & EN_CD = 1, no output load is detected
0.5
20
0.8
mA
Unplug
IDDpd
Power−down mode EN_AB & EN_CD = 0
100
mA
current
tpd
Latency
From Input to Output
2
ns
4. TYP values use VDD = 3.3 V, TA = 25°C
Table 10. LVCMOS CONTROL PIN CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
2−Level Control Pins LVCMOS Inputs (EN_AB, EN_CD)
V
DC Input Logic High
DC Input Logic Low
0.65 x VDD
GND
VDD
GND
VDD
0.35 x VDD
25
V
V
IH
V
IL
I
IH
High−level input current
Low−level input current
mA
mA
I
IL
−25
4−Level Control Pins LVCMOS Inputs (EQA/B/C/D, FGA/B/C/D)
V
DC Input Logic High; Setting “H”
DC Input Logic 2/3 VDD; Setting “F”
DC Input Logic 1/3 VDD; Setting “R”
DC Input Logic Low; Setting “L”
High−level input current
Input pin connected to VDD
0.92 x VDD
VDD
V
V
IH
V
Input pin is left floating (Open) (Note 5) 0.59 x VDD 0.67*VDD 0.75 x VDD
68 kW must be between pin and GND 0.25 x VDD 0.33*VDD 0.41 x VDD
ext
IF
V
IR
R
V
V
Input pin connected to GND
GND
0.08 x VDD
50
V
IL
I
IH
mA
mA
kW
I
IL
Low−level input current
−50
R
External Resistor for input setting “R”
Rext connect to GND (± 5%)
64.6
68
71.4
ext
5. Floating refers to a pin left in an open state, with no external connections.
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NB7NPQ1204EM
Table 11. CML RECEIVER AC/DC CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
72
Typ
Max
120
30
Unit
W
R
Differential Input Impedance (DC)
Single−ended Input Impedance (DC)
100
RX−DIFF−DC
R
Measured with respect to GND over
a voltage of 500 mV max.
18
W
RX−SINGLE−DC
ZRX−HIZ−DC−PD Common−mode input impedance for
V>0 during reset or power−down (DC)
VCM = 0 to 500 mV
25
75
kW
Cac_coupling
AC coupling capacitance
265
150
200
nF
VRX−CM−AC−P Common mode peak voltage
VRX−CM−DC−Acti Common mode peak voltage
AC up to 5 GHz
mVpeak
mVpeak
Between U0 and U1. AC up to
5 GHz
ve−Idle−Delta−P
|AvgU0(|V
+V |)/2
RX−D−
RX−D+
–AvgU1(|V
+V |)/2|
RX−D−
RX−D+
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 12. TRANSMITTER AC/DC CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Parameter
Test Conditions
Differential Swing |V −V |
TX−D−
Min
Typ
Max
Unit
V
R
Output differential p−p voltage
swing at 100 MHz
1.2
VPPd
TX−DIFF−PP
TX−D+
Differential TX impedance (DC)
72
100
120
600
W
TX−DIFF−DC
TX−RCV−DET
V
Voltage change allowed during re-
ceiver detect
mV
Cac_coupling
AC coupling capacitance
75
265
nF
UI
UI
UI
UI
pF
W
TTX−EYE(10Gbps) Transmitter eye, Include all jitter
TTX−EYE(5Gbps) Transmitter eye, Include all jitter
TTX−DJ−DD(10Gbps) Transmitter deterministic jitter
TTX−DJ−DD(5Gbps) Transmitter deterministic jitter
At the silicon pad. 10Gbps
At the silicon pad. 5Gbps
At the silicon pad. 10Gbps
At the silicon pad. 5Gbps
0.646
0.625
0.17
0.205
1.1
Ctxparasitic
Parasitic capacitor for TX
RTX−DC−CM
Common−mode output imped−
ance (DC)
18
0
30
VTX−DC−CM
VTX−C
Instantaneous allowed DC com-
mon mode voltage at the connec-
tor side of the AC coupling capaci-
tors
|V
|V
+V
+V
|/2
|/2
2.2
V
TX−D+
TX−D+
TX−D−
Common−mode voltage
VDD –
1.5
VDD
100
200
V
TX−D−
VTX−CM−AC−PP− TX AC common−mode peak−to−
V
TX−D+
+V
TX−D−
for both time and am-
mV
PP
Active
peak voltage swing in active mode plitude
V
Active_ Common mode delta voltage
Between U0 to U1
mVpeak
mVppd
TX−CM−DC−
Idle−Delta
|AvgU0(|V
+V |)/2
TX−D−
TX−D+
–AvgU1(|V
+V
TX−D−
|)/2|
TX−D+
V
Idle mode AC common mode delta Between TX+ and TX− in idle mode.
10
10
TX−Idle−DIFF−AC−pp
voltage |V
−V
|
Use the HPF to remove DC compo-
nents. 1/LPF. No AC and DC signals
are applied to RX terminals.
TX−D+
TX−D−
V
Idle mode DC common mode
delta voltage |V −V
Between TX+ and TX− in idle mode.
Use the LPF to remove DC compo-
nents. 1/HPF. No AC and DC signals
are applied to RX terminals.
mV
TX−Idle−DIFF−DC
|
TX−D−
TX−D+
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NB7NPQ1204EM
Table 12. TRANSMITTER AC/DC CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Parameter Test Conditions
CHANNEL PERFORMANCE
Min
Typ
Max
Unit
Gp
Peaking gain (Compensation at
5 GHz, relative to 100 MHz,
100 mVp−p sine wave input)
EQx = L
EQx = R
EQx = F
EQx = H
11.5
7.4
9.9
dB
13.1
Variation around typical
−3
−3
+3
+3
dB
dB
GF
Flat Gain (<100 MHz, EQx=F)
FGx = L
FGx = R
FGx = F
FGx = H
−1.2
0
+1.0
+2.0
Variation around typical
dB
V
−1 dB compression point output
1000
750
mVppd
SW_100M
swing (100 MHz)
V
−1 dB compression point output
swing (5 GHz)
mVppd
dB
SW_5G
DDNEXT
Differential near−end crosstalk
(Note 6)
100 MHz to 5GHz, Figure 5
−40
SIGNAL AND FREQUENCY DETECTORS
Vth_dsm
Low power slumber mode detector LFPS signal threshold in Low power
100
45
600
175
mVppd
mVppd
threshold
Slumber mode
Vth_am
Active mode detector threshold
Signal threshold in Active and Slumber
mode (Note 7)
6. Measured using a vector network analyzer (VNA) with −15 dbm power level applied to the adjacent input. The VNA detects the signal at the
output of the victim channel. All other inputs and outputs are terminated with 50−W.
7. Below the minimum is no signal ≥ 25°C. Above the maximum is active.
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NB7NPQ1204EM
PARAMETER MEASUREMENT DIAGRAMS
Rx−
V
OH
80%
Rx+
t
t
diff−HL
diff−LH
20%
Tx−
V
OL
t
t
F
R
Tx+
Figure 3. Propagation Delay
Figure 4. Output Rise and Fall Times
B_RX+
B_RX−
Figure 5. Channel−Isolation Test Configuration
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NB7NPQ1204EM
APPLICATION GUIDELINES
LFPS Compliance Testing
bias the control pins to the correct voltage to achieve this if
the pin is not connected to a voltage source. The low Setting
“L” is set by pulling the control pin to ground. Likewise the
high setting “H” is set by pulling the pin high to VCC. The
Rexternal setting can be set by adding a 68−K resistor from the
control pin to ground. This will bias the Redriver internal
voltage to 33% of VCC.
As part of USB 3.1 compliance test, the host or peripheral
must transmit a LFPS signal that adheres to the spec
parameters. The NB7NPQ1204EM is tested as a part of a
USB compliant system to ensure that it maintains
compliance while increasing system performance.
LFPS Functionality
USB 3.1, Gen1 and Gen2 use Low Frequency Periodic
Signaling.
Linear Equalization
The linear equalization that the NB7NPQ1204EM
provides compensates for losses that occur naturally along
board traces and cable lines. Linear Equalization boosts high
frequencies and lower frequencies linearly so when
transmitting at varying frequencies, the voltage amplitude
will remain consistent. This compensation electrically
counters losses and allows for longer traces to be possible
when routing.
(LFPS) to implement functions like exiting low−power
modes, performing warm resets and providing link training
between host and peripheral devices. LFPS signaling
consists of bursts of frequencies ranging between 10 to
50 MHz and can have specific burst lengths or repeat rates.
Ping.LFPS for TX Compliance
During the transmitter compliance, the system under test
must transmit certain compliance patterns as defined by the
USB−IF. In order to toggle through these patterns for various
tests, the receiver must receive a ping.LFPS signal from
either the test suite or a separate pattern generator. The
standard signal comprises of a single burst period of 100 ns
at 20 MHz.
DC Flat Gain
DC flat gain equally boosts high and low frequency
signals, and is essential for countering low frequency losses.
DC flat gain can also be used to simulate a higher input
signal from a USB Controller. If a USB controller can only
provide 800 mV differential to a receiver, it can be boosted
to 1128 mV using 2 dB of flat gain.
Control Pin Settings
Control pins A1, A0, B1, and B0 control the Flat Gain and
the Equalization of channels A and B and control pins C1,
C0, D1, and D0 control the Flat Gain and the Equalization
of channels C and D of the NB7NPQ1204EM Device.
The Float (Default) Setting “F” can be set by leaving the
control pins in a floating state. The Redriver will internally
Total Gain
When using Flat Gain with Equalization in a USB
application it is important to make sure that the total voltage
does not exceed 1200 mV. Total gain can be calculated by
adding the EQ gain to the FG.
Typical Layout Practices
• RX and TX pairs should maintain as close to a 90 W
differential impedance as possible.
• Limit the number of vias used on each data line. It is
suggested that 2 or fewer are used.
• RX and TX differential pairs should always be placed and
routed on the same layer directly above a ground plane.
This will help reduce EMI and noise on the data lines.
• Routing angles should be obtuse angles and kept to 135
degrees or larger.
• Traces should be routed as straight and symmetric as
possible.
• To minimize crosstalk, TX and RX data lines should be
kept away from other high speed signals.
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NB7NPQ1204EM
NB7NPQ1204EM
Up to 3 dB Loss
Up to 11 dB Loss
A RX
A TX
220nF
220nF
220nF
USB 3.1
Receptacle
(Type-C or Type-A)
Receiver/
Equalizer
USB 3.1
Controller
Driver
220nF
ESD
Protection
220nF
220nF
330-470nF
330-470nF
Receiver/
Equalizer
220K
Driver
220K
B TX
B RX
C RX
C TX
220nF
220nF
220nF
220nF
USB 3.1
Receptacle
(Type-C or Type-A)
Receiver/
Equalizer
USB 3.1
Controller
Driver
ESD
Protection
220nF
220nF
330-470nF
330-470nF
Receiver/
Equalizer
220K
Driver
220K
D TX
D RX
Figure 6. Typical Application
Table 13. DESIGN REQUIREMENTS
Design Parameter
Value
Supply Voltage
3.3 V nominal, (3.0 V to 3.6 V)
Operation Mode (Control Pin Selection)
TX AC Coupling Capacitors
RX AC Coupling Capacitors
Floating by Default, adjust for application losses
220 nF nominal, 75 nF to 265 nF, see Figure 6
330 − 470 nF nominal, see Figure 6
68 kW, ± 5%
R
external
RX Pull Down Resistors at Receptacle
Power Supply Capacitors
200 KW to 220 KW
100 nF to GND close to each Vcc pin, and 10 mF to GND on the Vcc plane
Trace loss of FR4 before NB7NPQ1204EM (Note 8)
Trace loss of FR4 after NB7NPQ1204EM (Note 8)
Linear Range at 5 GHz
Up to 11 dB Losses
Up To 3 dB Losses. Keep as short as possible for best performance.
900 mV differential
−1.2 dB, 0 dB, +1.0 dB, +2.0 dB
7.4 to 13.1 dB
DC Flat Gain Options
Equalization Options
Differential Trace Impedance
90 W ± 10%
8. Trace loss of FR4 was estimated to have 1 dB of loss per 1 inch of FR4 length with matched impedance and no VIAS.
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UQFN34 2.5x4.5, 0.35P
CASE 523BR
ISSUE A
DATE 10 DEC 2020
GENERIC
MARKING DIAGRAM*
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXX
XXXX
ALYWG
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
(Note: Microdot may be in either location)
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98AON26127H
UQFN34 2.5x4.5, 0.35P
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