NB7NPQ1002MMTTWG [ONSEMI]
3.3 V USB 3.1 第 2 代 10Gbps 双沟道/ 单端口线性再驱动器;
| 型号： | NB7NPQ1002MMTTWG |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V USB 3.1 第 2 代 10Gbps 双沟道/ 单端口线性再驱动器 驱动 驱动器 |
| 文件： | 总11页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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3.3 V USB 3.1 Gen-2
10ꢀGbps Dual Channel /
Single Port Linear Redriver
NB7NPQ1002M
Description
www.onsemi.com
The NB7NPQ1002M is a high performance single−Port linear
redriver designed for USB 3.1 Gen 1 and USB 3.1 Gen 2 applications
that supports both 5 Gbps and 10 Gbps data rates. Signal integrity
degrades from PCB traces, transmission cables, and inter−symbol
interference (ISI). The NB7NPQ1002M compensates for these losses
by engaging varying levels of equalization at the input receiver, and
flat gain amplification on the output transmitter.
The NB7NPQ1002M offers programmable equalization and flat
gain to optimize performance over various physical mediums.
The NB7NPQ1002M contains an automatic receiver detect function
which will determine whether the output is active. The receiver
detection loop will be active if the corresponding channel’s signal
detector is idle for a period of time. The channel will then move to
Unplug Mode if a load is not detected, or it will return to Low Power
Mode (Slumber mode) due to inactivity. Both the channels are
independent with individual controls.
WQFN30
CASE 510CK
MARKING DIAGRAM
NB7N
1002
ALYW
G
The NB7NPQ1002M comes in a 2.5 x 4.5 mm WQFN30 package
and is specified to operate across the entire industrial temperature
range, –40°C to 85°C.
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Features
• 3.3 V ± 0.3 V Power Supply
• 5 Gbps & 10 Gbps Serial Link with Linear Amplifier
• Device Supports USB 3.1 Gen 1 and USB 3.1 Gen 2 Data Rates
• USB 3.1 Super Speed Gen1 & Gen2 Standard Compliant
• Automatic Receiver Detection
• Integrated Input and Output Termination
• Pin Adjustable Receiver Equalization and Flat Gain
• Pin Adjustable Output Linear Swing
• 100 W Differential CML I/O’s
• Auto Slumber Mode for Adaptive Power Management
• Hot−Plug Capable
• ESD Protection ± 2 kV HBM
ORDERING INFORMATION
†
Device
NB7NPQ1002MMTTWG WQFN30 3000 / Tape
(Pb−Free) & Reel
Package
Shipping
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Operating Temperature Range Industrial: −40°C to +85°C
• Package: WQFN30, 2.5 x 4.5 mm
• This is a Pb−Free Device
Typical Applications
• USB3.1 Type−A and Type−C Signal Routing
• Mobile Phone and Tablet
• Computer, Laptop and Notebook
• External Storage Device
• Docking Station and Dongle
• Active Cable, Back Planes
• Gaming Console, Smart T.V
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
May, 2020 − Rev. 1
NB7NPQ1002M/D
NB7NPQ1002M
EQA
SWA
FGA
Channel A Control Logic
A_RX−
A_TX−
Receiver/
Equalizer
Driver
A_RX+
A_TX+
Power Management Logic
RXDET_EN
B_RX−
EN
B_TX−
Receiver/
Driver
Equalizer
B_TX+
B_RX+
Channel B Control Logic
EQB
SWB
FGB
Figure 1. Logic Diagram of NB7NPQ1002M
30
29
28
27
26
VDD
1
2
25 VDD
A_RX+
A_TX+
24
23
22
21
A_RX−
A_TX−
3
4
GND
GND
GND
GND
5
GND
Expose Pad EP
GND
6
20 GND
GND
GND
7
19
18
17
16
B_TX−
B_TX+
B_RX−
B_RX+
VDD
8
9
10
VDD
11
12
13
14
15
Figure 2. WQFN30 Package Pinout (Top View)
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2
NB7NPQ1002M
Table 1. PIN DESCRIPTION
Pin Number Pin Name
Type
Description
1, 10, 16, 25
VDD
A_RX+
A_RX−
GND
POWER 3.3 V power supply. V pins must be externally connected to power supply.
DD
2
3
INPUT Channel A Differential CML input pair for 5 / 10 Gbps USB signals with selectable input termination
between 50 W to V or 67 kW to GND. Must be externally AC−coupled in system. UFP/DFP trans-
DD
mitter should provide this capacitor.
4 – 7, 13,
19 – 22, 28
GND Supply Ground. All GND pins must be externally connected to Ground.
8
9
B_TX−
OUTPUT Channel B Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in system.
B_TX+
11
RXDET_EN INPUT Pin for Receiver detection Enable having an internal 300 kW pull−up resistor. HIGH “1” where pin is
connected to V , LOW “0” where pin is connected to Ground. Default is “1” Pin is Enabled, Low Pin
DD
is disabled.
12
14
15
SWB
FGB
EQB
INPUT Pin for control of Channel B Swing levels having an internal 100 kW pull up and 200 kW pull−down
resistors. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is connected to
DD
Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor Rext
68 kW is connected from pin to Ground. FLOAT “F” is the default setting.
INPUT Pin for control of Channel B Flat Gain setting having internal 100 kW pull up and 200 kW pull−down
resistors. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is connected to
DD
Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor Rext
68 kW is connected from pin to Ground. FLOAT “F” is the default setting.
INPUT Pin for control of Channel B Equalization setting having internal 100 kW pull up and 200 kW pull−
down resistors. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is con-
DD
nected to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external
resistor Rext 68 kW is connected from pin to Ground. FLOAT “F” is the default setting.
17
18
23
24
26
B_RX+
B_RX−
A_TX−
A_TX+
EQA
INPUT Channel B Differential CML input pair for 5 / 10 Gbps USB signals with selectable input termination
between 50 W to V or 67 kW to GND. Must be externally AC−coupled in system. UFP/DFP trans-
DD
mitter should provide this capacitor.
OUTPUT Channel A Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in system.
INPUT Pin for control of Channel A Equalization setting having internal 100 kW pull up and 200 kW pull−
down resistors. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is con-
DD
nected to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external
resistor Rext 68 kW is connected from pin to Ground. FLOAT “F” is the default setting.
27
29
FGA
SWA
INPUT Pin for control of Channel A Flat Gain setting having internal 100 kW pull up and 200 kW pull−down
resistors. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is connected to
DD
Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor Rext
68 kW is connected from pin to Ground. FLOAT “F” is the default setting.
INPUT Pin for control of Channel A Swing levels having internal 100 kW pull up and 200 kW pull−down resis-
tors. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is connected to
DD
Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor Rext
68 kW is connected from pin to Ground. FLOAT “F” is the default setting.
30
EN
INPUT Pin for device channel Enable having an internal 300 kW pull−up resistor. HIGH “1” where pin is con-
nected to V , LOW “0” where pin is connected to Ground. Default is “1” Pin is Enabled, Low Pin is
DD
disabled.
EP
GND
GND Exposed pad (EP). EP on the package bottom is thermally connected to the die for improved heat
transfer out of the package. The exposed pad is electrically connected to the die and must be sol-
dered to GND on the PC Board.
Power Management
While in the low power slumber mode, the receiver signal
The NB7NPQ1002M has an adaptive power management
feature in order to minimize power consumption. When
there is no termination detected, the corresponding channel
will change to low power slumber mode. Accordingly, both
channels will move to low power slumber mode
individually. Both the channels are independent with
separate controls.
detector will continue to monitor the input channel. If a
channel is in low power slumber mode, the receiver
detection loop will be active again. If a load is not detected,
then the channel will move to Device Unplug Mode and
continuously monitor for the load. When a load is detected,
the channel will return to Low Power Slumber Mode and
receiver detection will be active again per 6 ms.
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3
NB7NPQ1002M
Table 2. OPERATING MODES
Modes
Table 5. SWING SETTING
RIN
ROUT
High Z
SWA/ SWB
SW (mVppd)
Power Down Mode
Unplug Mode
67 kW to Ground
Low “L”
(Pin tied to Ground)
800
High Z
40 kW to V
40 kW to V
DD
DD
DD
Rext “R” (68 kW tied from pin to Ground)
1200
Low Power Slumber Mode
Active Mode
50 W to V
50 W to V
DD
FLOAT “F”
(Pin open)
1000
(Default)
50 W to V
DD
HIGH “H”
(Pin tied to V
1100
Table 3. EQUALIZATION SETTINGS:
EQA/ EQB
)
DD
EQ (dB)
Table 6. CHANNEL ENABLE SETTING
EN
@ 2.5 GHz
5.1
@ 5 GHz
10.9
Status
Low “L” (Pin tied to Ground)
Low “0”
(Pin tied to Ground)
Disabled
Rext “R”
(68 kW tied from pin to Ground)
1.9
6.7
HIGH “1”
(Pin tied to V
Enabled (Default)
FLOAT “F” (Pin open)
3.5
6.8
8.9 (Default)
13.1
)
DD
HIGH “H” (Pin tied to V
)
DD
Table 7. RECEIVER DETECTION SETTING
Table 4. FLAT GAIN SETTING
FGA/ FGB
RXDET_EN
Status
FG (dB)
−3
Low “0”
(Pin tied to Ground)
Disabled
Low “L” (Pin tied to Ground)
Rext “R” (68 kW tied from pin to Ground)
−1.5
HIGH “1”
(Pin tied to V
Enabled (Default)
)
DD
FLOAT “F” (Pin open)
0 (Default)
+2
HIGH “H” (Pin tied to V
)
DD
Table 8. ATTRIBUTES
Parameter
ESD Protection
Human Body Model
± 2 kV
Charged Device Model
> 1.5 kV
Moisture Sensitivity, Indefinite Time Out of Dry pack (Note 1)
Flammability Rating
Level 1
UL 94 V−O @ 0.125 in
40517
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test
1. For additional information, see Application Note AND8003/D.
Table 9. ABSOLUTE MAXIMUM RATINGS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
Min
−0.5
−0.5
−0.5
−25
Max
Unit
V
Supply Voltage (Note 2)
V
DD
4.6
Voltage range at any input or output terminal
Differential I/O
V
V
+ 0.5
V
DD
DD
LVCMOS inputs
+ 0.5
V
Output Current
+25
mA
W
Power Dissipation, Continuous
1.0
150
125
TBD
265
Storage Temperature Range, T
−65
_C
_C
_C/W
_C
SG
Maximum Junction Temperature, T
J
Junction−to−Ambient Thermal Resistance @ 500 lfm, q (Note 3)
JA
Wave Solder, Pb−Free, T
SOL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. All voltage values are with respect to the GND terminals.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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4
NB7NPQ1002M
Table 10. RECOMMENDED OPERATING CONDITIONS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
Min
3.0
−40
75
Typ
Max
3.6
Unit
V
V
C
Main power supply
3.3
DD
T
A
Operating free−air temperature
AC coupling capacitor
Industrial Temperature Range
+85
265
_C
nF
kW
100
68
AC
Rext
External Resistor for input control setting “R”, ± 5%
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 11. POWER SUPPLY CHARACTERISTICS and LATENCY
Symbol
Parameter
Supply Voltage
Test Conditions
Min Typ (Note 4)
Max
Unit
V
V
DD
3.0
3.3
115
0.4
3.6
IDD
Active mode current
EN = 1, 10 Gbps, compliance test pattern
mA
mA
Active
IDD
LPSlumber
Low Power Slumber mode
current
EN = 1, no input signal longer than TLP−Slumber
0.64
IDD
Unplug mode current
Power−down mode current
Latency
EN = 1, no output load is detected
EN = 0
0.36
10
0.45
50
2
mA
mA
ns
Unplug
IDDpd
tpd
From Input to Output
4. TYP values use V = 3.3 V, T = 25°C
DD
A
Table 12. CML RECEIVER AC/DC CHARACTERISTICS
V
DD
= 3.3 V ± 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
72
Typ
Max
120
30
Unit
W
R
Differential Input Impedance (DC)
Single−ended Input Impedance (DC)
100
RX−DIFF−DC
R
Measured with respect to GND
over a voltage of 500 mV max.
18
W
RX−SINGLE−DC
Z
Common−mode input impedance for V>0 dur- VCM = 0 to 500 mV
ing reset or power−down (DC)
25
kW
RX−HIZ−DC−PD
V
Common mode peak voltage
Common mode peak voltage
AC up to 5 GHz
150
200
mVpeak
mVpeak
RX−CM−AC−P
V
-
Between U0 and U1. AC up to
5 GHz
RX−CM−DC
Active−Idle−Delta−P
|AvgU0(|V
+V |)/2 –AvgU1(|V
RX−D− RX−
RX−D+
|)/2|
+V
RX−D−
D+
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 13. LVCMOS CONTROL PIN CHARACTERISTICS
V
DD
= 3.3 V ± 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
2−LEVEL CONTROL PINS LVCMOS INPUTS (EN, RXDET_EN)
V
DC Input Logic HIGH “1”
DC Input Logic LOW “0”
High−level input current
Low−level input current
0.65 * V
GND
V
V
DD
V
V
IH
DD
DD
V
GND
0.35 * V
25
IL
DD
I
IH
mA
mA
I
IL
−25
4−LEVEL CONTROL PINS LVCMOS INPUTS (EQA/EQB, FGA/FGB, SWA/SWB)
V
DC Input Logic HIGH; Setting “H” Input pin connected to VDD
0.92 * V
0.59 * V
V
DD
V
V
IH
DD
V
DC Input Logic FLOAT; Setting “F” Input pin FLOAT (open) (Note 5), Logic 2/3 *
0.67 * V
0.33 * V
GND
0.75 * V
0.41 * V
IF
DD
DD
DD
DD
DD
V
DD
V
IR
DC Input Logic Rext; Setting “R”
Rext resistor 68 kW must be connected be-
tween pin and GND, Logic 1/3 * V
0.25 * V
V
DD
DD
DD
V
DC Input Logic LOW; Setting “L” Input pin connected to GND
High−level input current
0.08 * V
50
V
IL
I
IH
mA
mA
I
IL
Low−level input current
−50
5. Floating refers to a pin left in an open state, with no external connections.
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5
NB7NPQ1002M
Table 14. TRANSMITTER AC/DC CHARACTERISTICS
V
DD
= 3.3 V ± 0.3 V Over operating free−air temperature range (unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
V
R
Output differential p−p voltage swing at Differential Swing
1.2
V
PPd
TX−DIFF−PP
100 MHz
|VTX-D+-VTX-D-
|
Differential TX impedance (DC)
72
120
600
W
TX−DIFF−DC
TX−RCV−DET
V
Voltage change allowed during receiver
detect
mV
Cac_coupling
AC coupling capacitance
75
265
nF
UI
UI
UI
TTX−EYE (10 Gbps) Transmitter eye, Include all jitter
TTX−EYE (5 Gbps) Transmitter eye, Include all jitter
At the silicon pad. 10 Gbps
At the silicon pad. 5 Gbps
At the silicon pad. 10 Gbps
0.646
0.625
TTX−DJ−DD
(10 Gbps)
Transmitter deterministic jitter
0.17
TTX−DJ−DD (5 Gbps) Transmitter deterministic jitter
At the silicon pad. 5 Gbps
0.205
1.1
UI
pF
W
Ctxparasitic
Parasitic capacitor for TX
R
Common−mode output impedance
(DC)
18
0
30
TX−DC−CM
V
Instantaneous allowed DC common
mode voltage at the connector side of
the AC coupling capacitors
|V
|V
+V
+V
|/2
|/2
2.2
V
TX−DC−CM
TX−D+
TX−D+
TX−D−
V
TX−C
Common−mode voltage
V
– 1.5
V
DD
V
TX−D−
DD
V
TX AC common−mode peak−to−peak
voltage swing in active mode
V
+V
for both time and
100
mV
PP
TX−CM−AC−PP−Active
TX−D+
TX−D−
amplitude
V
Common mode delta voltage
Between U0 to U1
200 mV−peak
TX−CM−DC−
Active_Idle−Delta
|AvgU0(|V
+V
|)/2
TX−D+
TX−D−
–AvgU1(|V
+ V
|)/2|
TX−D+
TX−D−
V
Idle mode AC common mode delta volt- Between TX+ and TX− in idle
10
10
mVppd
mV
TX−Idle−DIFF−AC−pp
age |V
−V
|
mode. Use the HPF to remove DC
components. 1/LPF. No AC and
DC signals are applied to RX ter-
minals.
TX−D+
TX−D−
V
Idle mode DC common mode delta volt- Between TX+ and TX− in idle
TX−Idle−DIFF−DC
age |V
−V
|
mode. Use the LPF to remove DC
components. 1/HPF. No AC and
DC signals are applied to RX ter-
minals.
TX−D+
TX−D−
CHANNEL PERFORMANCE
Gp
Peaking gain (Compensation at 5 GHz, EQx = L
10.9
6.7
8.9
relative to 100 MHz, 100 mVp−p sine
EQx = R
dB
wave input)
EQx = F
EQx = H
13.1
Variation around typical
FGx = L
FGx = R
FGx = F
FGx = H
−3
+3
+3
dB
dB
Gf
Flat Gain (100 MHz, EQx=F, SWx=F)
−3
−1.5
0
+2
Variation around typical
−3
dB
V
−1 dB compression point output swing SWx = L
800
1200
1000
1100
mVppd
SW_100M
(100MHz)
SWx = R
SWx = F
SWx = H
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NB7NPQ1002M
Table 14. TRANSMITTER AC/DC CHARACTERISTICS
V
DD
= 3.3 V ± 0.3 V Over operating free−air temperature range (unless otherwise noted)
Parameter
CHANNEL PERFORMANCE
−1 dB compression point output swing SWx = L
Test Conditions
Min
Typ
Max
Unit
V
600
900
750
825
mVppd
SW_5G
(5 GHz)
SWx = R
SWx = F
SWx = H
DDNEXT
Differential near−end crosstalk (Note 6) 100MHz to 5GHz, RXDET_EN = 1
−40
dB
Figure 3
SIGNAL AND FREQUENCY DETECTORS
Vth_dsm
Low power slumber mode detector
LFPS signal threshold in Low
power Slumber mode
100
45
600
175
mVppd
mVppd
threshold
Vth_am
Active mode detector threshold
Signal threshold in Active and
Slumber mode
6. Measured using a Vector Network Analyzer (VNA) with −15 dbm power level applied to the adjacent input. The VNA detects the signal at
the output of the victim channel. All other inputs and outputs are terminated with 50−W.
Figure 3. Channel−isolation Test Configuration
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NB7NPQ1002M
Typical Application:
J1 to J6: JUMPER
SELECTION FOR EQ/FG/SW
VDD = 3.3 V
VDD
R3
68K
R4
68K
R5
68K
At Board entry
+
2
J1
4
2
J2
4
2
J3
4
C10−C13
C14
C9
100 nF
100 nF x 4
VDD
VDD
VDD
22 uF
Near VDD pins
VDD
VDD
HOST
1
2
25
24
23
22
21
20
19
18
17
16
C1
C5
VDD
VDD
A_TX+
A_TX−
GND
220 nF
220 nF
SSTX+
SSTX−
A_RX+
A_RX−
GND
3
4
C2
C6
220 nF
220 nF
5
GND
GND
GND
6
GND
GND
7
C3
220 nF
C7
330 nF
GND
GND
8
SSRX−
SSRX+
B_TX−
B_TX+
VDD
B_RX−
B_RX+
VDD
U1
9
NB7NPQ1002M
10
C4
220 nF
C8
330 nF
R1
220K
VDD
VDD
R2
220K
VDD
J4
VDD
J5
VDD
J6
2
4
2
4
2
4
R6
68K
R7
68K
R8
68K
Figure 4. USB 3.1 Host Side NB7NPQ1002M Application
Table 15. DESIGN REQUIREMENTS
Design Parameter
Value
Supply Voltage
3.3 V nominal, (3.0 V to 3.6 V)
Operation Mode (Control Pin Selection)
Default FLOAT “F”, adjust based on application losses. Refer Page 3 for different EQ, FG
and SW settings.
TX AC Coupling Capacitors
RX AC Coupling Capacitors
Rext
220 nF nominal, 75 nF to 265 nF, see Figure 4
330 − 470 nF nominal, see Figure 4
68 kW ± ±5%
RX Pull Down Resistors at Receptacle
Power Supply Capacitors
200 kW to 220 kW
100 nF to GND close to each Vcc pin, and 22 UF to GND on the Vcc plane
Trace loss of FR4 before NB7NPQ7022M Up to 13 dB losses
Trace loss of FR4 after NB7NPQ7022M
DC Flat Gain Options
Up To 3 dB losses. Keep as short as possible for best performance.
−3 dB, −1.5 dB, 0 dB, 2 dB
6.7 to 13.1 dB
Equalization Options
Swing Options
800 to 1200 mV
90 W ± ±10%
Differential Trace Impedance
Typical Layout Practices
• RX and TX pairs should maintain as close to a 90 W
Differential impedance as possible.
• Limit the number of vias used on each data line. It is
suggested that 2 or fewer are used.
• RX and TX differential pairs should always be placed and
routed on the same layer directly above a ground plane.
This will help reduce EMI and noise on the data lines.
• Routing angles should be obtuse angles and kept to 135
degrees or larger.
• Traces should be routed as straight and symmetric as
possible.
• To minimize crosstalk, TX and RX data lines should be
kept away from other high speed signals.
www.onsemi.com
8
NB7NPQ1002M
PACKAGE DIMENSIONS
WQFN30 2.50x4.50, 0.4P
CASE 510CK
ISSUE B
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9
NB7NPQ1002M
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