NB7NPQ1402E2MMUTWG [ONSEMI]
3.3 V USB 3.2 10 Gbps Dual Channel / Single Port Linear Redriver;
| 型号： | NB7NPQ1402E2MMUTWG |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V USB 3.2 10 Gbps Dual Channel / Single Port Linear Redriver |
| 文件： | 总13页 (文件大小：510K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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3.3 V USB 3.2 10ꢀGbps
Dual Channel / Single Port
Linear Redriver
MARKING
DIAGRAM
402E
ALYW
UQFN24
CASE 523AB
NB7NPQ1402E2M
402E = Specific Device Code
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
Description
The NB7NPQ1402E2M is a high performance single−Port linear
redriver designed for USB 3.2 applications that supports both 5 Gbps
and 10 Gbps data rates. Signal integrity degrades from PCB traces,
transmission cables, and inter−symbol interference (ISI).
The NB7NPQ1402E2M compensates for these losses by engaging
varying levels of equalization at the input receiver, and flat gain
amplification on the output transmitter.
The NB7NPQ1402E2M offers programmable equalization and flat
gain for each independent channel to optimize performance over
various physical mediums.
The NB7NPQ1402E2M contains an automatic receiver detect
function which will determine whether the output is active.
The receiver detection loop will be active if the corresponding
channel’s signal detector is idle for a period of time. The channel will
then move to Unplug Mode if a load is not detected, or it will return
to Low Power Mode (Slumber mode) due to inactivity.
The NB7NPQ1402E2M comes in a 2.5 x 2.5 x 0.5 mm UQFN24
package and is specified to operate across the entire industrial
temperature range, –40°C to 85°C.
= Work Week
ORDERING INFORMATION
†
Device
NB7NPQ1402E2MMUTWG UQFN24 5000 / Tape
(Pb−Free) & Reel
Package Shipping
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Features
Typical Applications
• 3.3 V ± ±0.3 V Power Supply
• USB3.2 Type−A and Type−C Signal Routing
• Mobile Phone and Tablet
• 5 Gbps & 10 Gbps Serial Link with Linear Amplifier
• Device Supports USB 3.2 Gen2 and Gen1
• Automatic Receiver Detection
• Computer, Laptop and Notebook
• External Storage Device
• Supports USB−IF VCM Requirement
• Integrated Input and Output Termination
• Pin Adjustable Receiver Equalization and Flat Gain
• 100 W Differential CML I/O’s
• Docking Station and Dongle
• Active Cable, Back Planes
• Gaming Console, Smart T.V.
• Auto Slumber Mode for Adaptive Power Management
• Hot−Plug Capable
• ESD Protection ± 4 kV HBM
• Operating Temperature Range Industrial:
−40°C to +85°C
• Package: UQFN24, 2.5 x 2.5 x 0.5 mm
• This is a Pb−Free Device
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
July, 2022 − Rev. 2
NB7NPQ1402E2M/D
NB7NPQ1402E2M
Figure 1. Logic Diagram of NB7NPQ1402E2M
Figure 2. UQFN24 Package Pinout (Top View)
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NB7NPQ1402E2M
Table 1. PIN DESCRIPTION
Pin Number Pin Name
Type
Description
1
2
3
4
EQA
FGA
SWA
EN
INPUT Pin for control of Channel A Equalization setting having internal 100 kW pull up and 200 kW pull−
down resistors. 4 state input: HIGH “H” where pin is connected to VDD, LOW “L” where pin is con-
nected to| Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external
resistor Rext 68 kW is connected from pin to Ground. FLOAT “F” is the default setting.
INPUT Pin for control of Channel A Flat Gain setting having internal 100 kW and 200 kW pull−down resis-
tors. 4 state input: HIGH “H” where pin is connected to VDD, Low “L” where pin is connected to
Ground, FLOATING “F” where the pin is left floating (open) and Rext “R” where an external resistor
Rext
INPUT Pin for control of Channel A Swing levels having internal 100 kW and 200 kW pull−down resistors. 4
state input: HIGH “H” where pin is connected to VDD, LOW “L” where pin is connected to Ground,
FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor Rext 68 kW
is connected from pin to Ground. FLOAT “F” is the default setting.
INPUT Pin for device channel Enable having an internal 300 kW pull−up resistor. HIGH “1” where pin is
connected to , LOW “0’ where pin is connected to Ground. Default is “1” pin is Enabled, Low Pin is
disabled.
5, 17
6
VDD
A_RX+
A_RX−
GND
POWER 3.3 V power supply. VDD pins must be externally connected to power supply.
INPUT Channel A Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled
in system. UFP/DFP transmitter should provide this capacitor.
7
9, 21
GND
Reference Ground. GND pins must be externally connected to power supply ground to guarantee
proper operation.
11
12
13
B_TX−
OUTPUT Channel B Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in sys-
tem
B_TX+
RXDET_EN INPUT Receiver Detection enable pin. High−receiver detection is ENABLED. Low−receiver detection is
DISABLED. Internal pull−up; default is high when open. The RXDET_EN pin must be powered
simultaneously with VDD. After device is powered up, toggle the RXDET_EN pin from High to Low
to DISABLE RX DETECT function.
14
15
16
SWB
FGB
EQB
INPUT Pin for control of Channel B Swing Levels having an internal 100 kW pull up and 200 kW pull−down
resistors. 4 state input: HIGH “H” where pin is connected to VDD, LOW “L” where pin is connected
to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor
Rext 68 kW is connected from pin to Ground. FLOAT “F” is the default setting.
INPUT Pin for control of Channel B Flat Gain setting having internal 100 kW pull−up and 200 kW pull−down
resistors. 4 state input: HIGH “H” where pin is connected to VDD, LOW “L” where pin is connected
to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor
Rext 68 kW is connected from pin to Ground. FLOAT “F” is the default setting
INPUT Pin for control of Channel B Equalization setting having terminal 100 kW pull−up and 200 kW pull−
down resistors. 4 state input: HIGH”H” where pin is connected to VDD, LOW “L” where pin is con-
nected to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external
resistor Rext 68 kW is connected from pin to Ground. FLOAT “F” is the default setting.
18
19
23
24
EP
B_RX+
B_RX−
A_TX−
A_TX+
GND
INPUT Channel B Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled
in system
OUTPUT Channel A Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in sys-
tem.
GND
Exposed Pad (EP). EP on the package bottom is thermally connected to the die for improved heat
transfer out of the package. The expose pad is electrically connected to the die and must be sol-
dered to GND on the PC board.
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NB7NPQ1402E2M
Power Management
Table 4. EQUALIZATION SETTING
The NB7NPQ1402E2M has an adaptive power
management feature in order to minimize power
consumption. When the receiver signal detector is idle, the
corresponding channel will change to low power slumber
mode. Accordingly, both channels will move to low power
slumber mode individually.
While in the low power slumber mode, the receiver signal
detector will continue to monitor the input channel. If a
channel is in low power slumber mode, the receiver
detection loop will be active again. If a load is not detected,
then the channel will move to Device Unplug Mode and
continuously monitor for the load. When a load is detected,
the channel will return to Low Power Slumber Mode and
receiver detection will be active again per 6 ms.
EQA/B are the selection pins for the equalization.
EQA/B
Equalizer Setting (dB)
@2.5 GHz
5.0
@5 GHz
9.9
L (Tie 0−W to GND)
R (Tie Rext to GND)
F (Leave Open)
2.7
6.9
4.0
8.2 (Default)
12.1
H (Tie 0−W to VDD)
6.5
Table 5. FLAT GAIN SETTING
FGA/B are the selection pins for the DC gain.
FGA/B
Flat Gain Settings (dB)
L (Tie 0 W to GND)
R (Tie Rext to GND)
F (Leave Open)
−1.2
−0.2
Table 2. OPERATING MODES
+0.8 (Default)
+1.8
Mode
R
R
OUT
IN
H (Tie 0 W to VDD)
PD
67 kW to GND
High−Z
High−Z
Unplug Mode
40 kW to VDD
40 kW to VDD
Table 6. CHANNEL ENABLE SETTING
EN is the channel enable pin for both channels A&B.
Low Power
Slumber Mode
50 W to VDD
EN
0
Channel Enable Setting
Active
50 W to VDD
50 W to VDD
Disabled
1
Enabled (Default)
Table 3. SWING SETTING
SWA/B
SW (mVppd)
800
Table 7. RECEIVER DETECTION SETTING
LOW “L” (Pin tied to Ground)
Rext “R” (68 kW tied from pin to Ground)
Float “F” (Pin open)
RXDET_EN
Status
1200
Low “0” (Pin tied to Ground)
HIGH “1” (Pin tied to VDD)
Disabled
1000 (Default)
1100
Enabled (Default)
HIGH “H” (Pin tied to VDD)
Table 8. ATTRIBUTES
Parameter
ESD Protection
Human Body Model
Charged Device Model
± 4 kV
> 1.5 kV
Moisture Sensitivity, Indefinite Time Out of Dry pack (Note 1)
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−O @ 0.125 in
Transistor Count
81034
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch- up Test
1. For additional information, see Application Note AND8003/D.
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NB7NPQ1402E2M
Table 9. ABSOLUTE MAXIMUM RATINGS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
VDD
Min
−0.5
−0.5
−0.5
−25
Max
Unit
V
Supply Voltage (Note 2)
4.6
Voltage range at any input or output terminal
Differential I/O
LVCMOS inputs
V
V
+ 0.5
V
DD
DD
+ 0.5
V
Output Current
+25
mA
W
Power Dissipation, Continuous
1.2
150
125
34
Storage Temperature Range, T
−65
°C
°C
°C/W
°C
SG
Maximum Junction Temperature, T
J
Junction−to−Ambient Thermal Resistance @ 500 lfm, q (Note 3)
JA
Wave Solder, Pb−Free, T
265
SOL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. All voltage values are with respect to the GND terminals.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
Table 10. RECOMMENDED OPERATING CONDITIONS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
Min
3.0
−40
75
Typ
Max
3.6
Unit
V
V
DD
Main power supply
3.3
T
A
Operating free−air temperature
AC coupling capacitor
Industrial Temperature Range
+85
265
°C
nF
C
100
AC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 11. POWER SUPPLY CHARACTERISTICS and LATENCY
Typ
(Note 4)
Symbol
Parameter
Test Conditions
Min
Max
3.6
Unit
V
VDD
Supply Voltage
3.0
3.3
IDD
Active mode current EN = 1, 10 Gbps, compliance test pattern
125
167
0.65
mA
mA
Active
LPSlumber
IDD
Low Power Slumber EN = 1, no input signal longer than TLPSlumber
mode current
0.4
IDD
Unplug mode current EN = 1, no output load is detected
0.25
20
0.4
50
mA
Unplug
IDDpd
Power−down mode EN = 0
mA
current
tpd
Latency
From Input to Output
2
ns
4. TYP values use VDD = 3.3 V, TA = 25°C
Table 12. LVCMOS CONTROL PIN CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
2−Level Control Pins LVCMOS Inputs (EN, RXDET_EN)
V
DC Input Logic High
DC Input Logic Low
0.65 x VDD
GND
VDD
GND
VDD
0.35 x VDD
25
V
V
IH
V
IL
I
IH
High−level input current
Low−level input current
mA
mA
I
IL
−25
4−Level Control Pins LVCMOS Inputs (EQA/B, FGA/B, SWA/B)
V
DC Input Logic High; Setting “H”
Input pin connected to VDD
0.92 x VDD
VDD
V
V
IH
V
DC Input Logic 2/3 VDD; Setting “F”
Input pin is left floating (Open) (Note 5) 0.59 x VDD 0.67*VDD 0.75 x VDD
IF
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NB7NPQ1402E2M
Table 12. LVCMOS CONTROL PIN CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol Parameter Test Conditions
4−Level Control Pins LVCMOS Inputs (EQA/B, FGA/B, SWA/B)
Min
Typ
Max
Unit
V
DC Input Logic 1/3 VDD; Setting “R”
DC Input Logic Low; Setting “L”
High−level input current
R
68 kW must be between pin and GND 0.25 x VDD 0.33*VDD 0.41 x VDD
ext
V
V
IR
V
Input pin connected to GND
GND
0.08 x VDD
50
IL
I
IH
mA
mA
kW
I
IL
Low−level input current
−50
R
External Resistor for input setting “R”
Rext connect to GND (± 5%)
64.6
68
71.4
ext
5. Floating refers to a pin left in an open state, with no external connections.
Table 13. CML RECEIVER AC/DC CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
120
30
Unit
R
Differential Input Impedance (DC)
72
18
100
W
W
RX−DIFF−DC
R
Single−ended Input Impedance (DC) Measured with respect to GND
RX−SINGLE−DC
over a voltage of 500 mV max.
ZRX−HIZ−DC−PD Common−mode input impedance for VCM = 0 to 500 mV
25
75
kW
V>0 during reset or power−down
(DC)
Cac_coupling
AC coupling capacitance
265
nF
VRX−CM−AC−P
Common mode peak voltage
AC up to 5 GHz
150
200
mVpeak
mVpeak
VRX−CM−DC−Active Rx AC common mode voltage during Measured at Rx pins into a pair of
−Idle−Delta−P
the U1 to U0 transition
50 W terminations into ground.
Includes Tx and channel
conversion, AC range up to 5 GHz
VRX−CM−DC−Conn Instantaneous DC common mode
Apply to all link states and
−0.5
−0.3
1
1
V
V
(Notes 6, 7)
voltage coupled from the far−end Tx during power−on, and power−off
when Rx termination is
equivalent of 200 kW
VRX−CM−DC−Conn Instantaneous DC common mode
Apply to all link states and
(Notes 6, 7)
voltage coupled from the far−end Tx during power−on, and power−off
when Rx termination is 50 W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Not include +/−250 mV AC ground offset.
7. The receiver supports legacy implementations with VTX−DC+AC−CONN common mode transient up to 2.2 V.
Table 14. TRANSMITTER AC/DC CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
R
Output differential p−p voltage swing Differential Swing |V
−V |
TX−D−
0.8
1.0
1.2
VPPd
TX−DIFF−PP
TX−D+
at 100 MHz (SWx = F)
Differential TX impedance (DC)
72
100
120
600
W
TX−DIFF−DC
TX−RCV−DET
V
Voltage change allowed during re-
ceiver detect
mV
Cac_coupling
AC coupling capacitance
75
265
nF
UI
UI
UI
UI
pF
TTX−EYE(10 Gbps) Transmitter eye, Include all jitter
TTX−EYE(5 Gbps) Transmitter eye, Include all jitter
TTX−DJ−DD(10 Gbps) Transmitter deterministic jitter
TTX−DJ−DD(5 Gbps) Transmitter deterministic jitter
At the silicon pad. 10 Gbps
At the silicon pad. 5 Gbps
At the silicon pad. 10 Gbps
At the silicon pad. 5 Gbps
0.646
0.625
0.17
0.205
1.1
Ctxparasitic
Parasitic capacitor for TX
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NB7NPQ1402E2M
Table 14. TRANSMITTER AC/DC CHARACTERISTICS (continued)
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
RTX−DC−CM
Common−mode output impedance
(DC)
18
30
W
VTX−DC−CM
VTX−DC−CM
VTX−C
Instantaneous allowed DC common 200 kW single ended receiver load
mode voltage at the connector side
−0.5
−0.3
1
1
V
V
V
of the AC coupling capacitors
Instantaneous allowed DC common 50 W single ended receiver load
mode voltage at the connector side
of the AC coupling capacitors
Common−mode voltage
|V
+V |/2
TX−D−
VDD –
1.5
VDD
100
200
TX−D+
VTX−CM−AC−PP− TX AC common−mode peak−to−
Active peak voltage swing in active mode
V
+V
for both time and
mV
PP
TX−D+
TX−D−
amplitude
V
Active_ Common mode delta voltage
Between U0 to U1
mVpeak
TX−CM−DC−
Idle−Delta
|AvgU0(|V
+V |)/2
TX−D−
TX−D+
–AvgU1(|V
+V |)/2|
TX−D−
TX−D+
V
Idle mode AC common mode delta
voltage |V −V
Between TX+ and TX− in idle
10
10
mVppd
mV
TX−Idle−DIFF−AC−pp
|
TX−D−
mode. Use the HPF to remove DC
components. 1/LPF. No AC and DC
signals are applied to RX terminals.
TX−D+
V
Idle mode DC common mode delta
voltage |V −V
Between TX+ and TX− in idle
TX−Idle−DIFF−DC
|
TX−D−
mode. Use the LPF to remove DC
components. 1/HPF. No AC and DC
signals are applied to RX terminals.
TX−D+
CHANNEL PERFORMANCE
Gp
GF
Peaking gain (Compensation at
5 GHz, relative to 100 MHz,
100 mVp−p sine wave input)
EQx = L
EQx = R
EQx = F
EQx = H
9.9
6.9
8.2
dB
12.1
Variation around typical
−3
−3
+3
+3
dB
dB
Flat Gain (<100 MHz, EQx=F)
FGx = L
FGx = R
FGx = F
FGx = H
−1.2
−0.2
+0.8
+1.8
Variation around typical
dB
V
−1 dB compression point output
1000
800
mVppd
SW_100M
swing (100 MHz) (SWx = F)
V
−1 dB compression point output
swing (5 GHz) (SWx = F)
mVppd
dB
SW_5G
DDNEXT
Differential near−end crosstalk
(Note 8)
100 MHz to 5 GHz, Figure 5
−40
SIGNAL AND FREQUENCY DETECTORS
Vth_dsm
Low power slumber mode detector
LFPS signal threshold in Low power
Slumber mode
100
45
600
175
mVppd
mVppd
threshold
Vth_am
Active mode detector threshold
Signal threshold in Active and
Slumber mode (Note 9)
8. Measured using a vector network analyzer (VNA) with −15 dbm power level applied to the adjacent input. The VNA detects the signal at the
output of the victim channel. All other inputs and outputs are terminated with 50 W.
9. Below the minimum is no signal ≥ 25°C. Above the maximum is active.
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NB7NPQ1402E2M
PARAMETER MEASUREMENT DIAGRAMS
Rx−
V
OH
80%
Rx+
t
t
diff−HL
diff−LH
20%
Tx−
V
OL
t
t
F
R
Tx+
Figure 3. Propagation Delay
Figure 4. Output Rise and Fall Times
B_RX+
B_RX−
Figure 5. Channel−Isolation Test Configuration
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NB7NPQ1402E2M
Figure 6. Power Up Timing
Test Conditions
Table 15. POWER UP TIMING
Symbol
Parameter
Min
Typ
Max
Unit
Td_EN
VDD to Enable Assertion timing
requirement
Figure 6.
0
ms
T_VCM
Stabilization time for VCM
Figure 6.
330
400
ms
Figure 7. Power Down Timing
Table 16. POWER DOWN TIMING
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Td_OFF
Delay time required from EN
de−assertion until VDD is powered off
Figure 7.
900
ms
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NB7NPQ1402E2M
APPLICATION GUIDELINES
LFPS Compliance Testing
Linear Equalization
As part of USB 3.2 compliance test, the host or peripheral
must transmit a LFPS signal that adheres to the spec
parameters. The NB7NPQ1402E2M is tested as a part of a
USB compliant system to ensure that it maintains
compliance while increasing system performance.
The linear equalization that the NB7NPQ1402E2M
provides compensates for losses that occur naturally along
board traces and cable lines. Linear Equalization boosts high
frequencies and lower frequencies linearly so when
transmitting at varying frequencies, the voltage amplitude
will remain consistent. This compensation electrically
counters losses and allows for longer traces to be possible
when routing.
LFPS Functionality
USB 3.2 Low Frequency Periodic Signaling.
(LFPS) to implement functions like exiting low−power
modes, performing warm resets and providing link training
between host and peripheral devices. LFPS signaling
consists of bursts of frequencies ranging between 10 to
50 MHz and can have specific burst lengths or repeat rates.
DC Flat Gain
DC flat gain equally boosts high and low frequency
signals, and is essential for countering low frequency losses.
DC flat gain can also be used to simulate a higher input
signal from a USB Controller. If a USB controller can only
provide 800 mV differential to a receiver, it can be boosted
to 1128 mV using 2 dB of flat gain.
Ping.LFPS for TX Compliance
During the transmitter compliance, the system under test
must transmit certain compliance patterns as defined by the
USB−IF. In order to toggle through these patterns for various
tests, the receiver must receive a ping.LFPS signal from
either the test suite or a separate pattern generator. The
standard signal comprises of a single burst period of 100 ns
at 20 MHz.
Total Gain
When using Flat Gain with Equalization in a USB
application it is important to make sure that the total voltage
does not exceed 1200 mV. Total gain can be calculated by
adding the EQ gain to the FG.
Control Pin Settings
Typical Layout Practices
Control pins SWA, FGA, EQA, SWB, FGB, and EQB
control the Output Swing, Flat Gain and the Equalization of
channels A and B of the NB7NPQ1402E2M Device.
The Float (Default) Setting “F” can be set by leaving the
control pins in a floating state. The Redriver will internally
bias the control pins to the correct voltage to achieve this if
the pin is not connected to a voltage source. The low Setting
“L” is set by pulling the control pin to ground. Likewise the
high setting “H” is set by pulling the pin high to VCC. The
Rexternal setting can be set by adding a 68 kW resistor from
the control pin to ground. This will bias the Redriver internal
voltage to 33% of VCC.
• RX and TX pairs should maintain as close to a 90 W
differential impedance as possible.
• Limit the number of vias used on each data line. It is
suggested that two or fewer are used.
• Traces should be routed as straight and symmetric as
possible.
• RX and TX differential pairs should always be placed and
routed on the same layer directly above a ground plane.
This will help reduce EMI and noise on the data lines.
• Routing angles should be obtuse angles and kept to
135° or larger.
• To minimize crosstalk, TX and RX data lines should be
kept away from other high speed signals.
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NB7NPQ1402E2M
Figure 8. Typical Application
Table 17. DESIGN REQUIREMENTS
Design Parameter
Value
Supply Voltage
3.3 V nominal, (3.0 V to 3.6 V)
Operation Mode (Control Pin Selection)
TX AC Coupling Capacitors
Floating by Default, adjust for application losses
220 nF nominal, 75 nF to 265 nF, see Figure 8
330 − 470 nF nominal, see Figure 8
100 nF to GND close to each VCC pin, and 10 mF to GND on the VCC plane
Up to 11 dB Losses
RX AC Coupling Capacitors
Power Supply Capacitors
Trace loss of FR4 before NB7NPQ1402E2M (Note 10)
Trace loss of FR4 after NB7NPQ1402E2M (Note 10)
Linear Range at 5 GHz
Up To 3 dB Losses. Keep as short as possible for best performance.
900 mV differential
DC Flat Gain Options
−1.2 dB, −0.2 dB, +0.8 dB, +1.8 dB
6.9 to 12.1 dB
Equalization Options
Differential Trace Impedance
90 W ± 10%
10.Trace loss of FR4 was estimated to have 1 dB of loss per 1 inch of FR4 length with matched impedance and no VIAS.
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UQFN24 2.5x2.5, 0.35P
CASE 523AB
ISSUE A
DATE 20 AUG 2021
GENERIC
MARKING DIAGRAM*
XXXX
ALYW
XXXX = Specific Device Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
A
L
= Assembly Location
= Wafer Lot
Y
W
= Year
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON31482H
UQFN24 2.5x2.5, 0.35P
PAGE 1 OF 1
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