NB7NPQ1404E2MMUTWG [ONSEMI]
3.3 V USB 3.2 10 Gbps Quad Channel / Dual Port Linear Redriver;型号: | NB7NPQ1404E2MMUTWG |
厂家: | ONSEMI |
描述: | 3.3 V USB 3.2 10 Gbps Quad Channel / Dual Port Linear Redriver |
文件: | 总13页 (文件大小:373K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
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3.3 V USB 3.2 10ꢀGbps
Quad Channel / Dual Port
Linear Redriver
MARKING
DIAGRAM
NB7N
404E
ALYW
UQFN34
CASE 523BR
NB7NPQ1404E2M
Description
NB7N404E = Specific Device Code
The NB7NPQ1404E2M is a high performance 2−Port linear
redriver designed for USB 3.2 applications that supports both 5 Gbps
and 10 Gbps data rates. Signal integrity degrades from PCB traces,
transmission cables, and inter−symbol interference (ISI).
The NB7NPQ1404E2M compensates for these losses by engaging
varying levels of equalization at the input receiver, and flat gain
amplification on the output transmitter.
The NB7NPQ1404E2M offers programmable equalization and flat
gain for each independent channel to optimize performance over
various physical mediums.
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
†
Device
NB7NPQ1404E2MMUTWG UQFN34 5000 / Tape
(Pb−Free) & Reel
Package Shipping
The NB7NPQ1404E2M contains an automatic receiver detect
function which will determine whether the output is active.
The receiver detection loop will be active if the corresponding
channel’s signal detector is idle for a period of time. The channel will
then move to Unplug Mode if a load is not detected, or it will return
to Low Power Mode (Slumber mode) due to inactivity.
The NB7NPQ1404E2M comes in a 2.5 x 4.5 x 0.55 mm UQFN34
package and is specified to operate across the entire industrial
temperature range, –40°C to 85°C.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Features
Typical Applications
• 3.3 V ± ±0.3 V Power Supply
• USB3.2 Type−A and Type−C Signal Routing
• Mobile Phone and Tablet
• 5 Gbps & 10 Gbps Serial Link with Linear Amplifier
• Device Supports USB 3.2 Gen2 and Gen1
• Automatic Receiver Detection
• Computer, Laptop and Notebook
• External Storage Device
• Supports USB−IF VCM Requirement
• Integrated Input and Output Termination
• Pin Adjustable Receiver Equalization and Flat Gain
• 100 W Differential CML I/O’s
• Docking Station and Dongle
• Active Cable, Back Planes
• Gaming Console, Smart T.V.
• Auto Slumber Mode for Adaptive Power Management
• Hot−Plug Capable
• ESD Protection ± 4 kV HBM
• Operating Temperature Range Industrial:
−40°C to +85°C
• Package: UQFN34, 2.5 x 4.5 x 0.55 mm
• This is a Pb−Free Device
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
May, 2022 − Rev. 1
NB7NPQ1404E2M/D
NB7NPQ1404E2M
EQA
FGA
EN_AB
A_RX−
A_TX−
Receiver/
Equalizer
Driver
A_RX+
A_TX+
B_TX−
B_RX−
Receiver/
Driver
Equalizer
B_TX+
B_RX+
EQB
FGB
FGC
EQC
C_RX−
C_RX+
C_TX−
Receiver/
Equalizer
Driver
C_TX+
D_TX−
D_RX−
Receiver/
Equalizer
Driver
FGD
D_TX+
D_RX+
EQD
EN_CD
Figure 1. Logic Diagram of NB7NPQ1404E2M
Figure 2. UQFN34 Package Pinout (Top View)
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NB7NPQ1404E2M
Table 1. PIN DESCRIPTION
Pin Name
A_RX+
A_RX−
GND
Type
Description
Pin Number
1
INPUT Channel A Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled in
system. UFP/DFP transmitter should provide this capacitor.
2
3, 10, 10, 27
GND
Reference Ground. GND pins must be externally connected to power supply ground to guarantee
proper operation.
4
5
B_TX−
B_TX+
FGC
OUTPUT Channel B Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in system.
6
INPUT DC flat gain for channel C. 4−level input pin. Internal 100 kW pull−up and 200 kW pull−down.
INPUT EQ select for channel C. 4−level input pin. Internal 100 kW pull−up and 200 kW pull−down.
7
EQC
8
C_RX+
C_RX−
D_TX−
D_TX+
INPUT Channel C Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled in
system. UFP/DFP transmitter should provide this capacitor.
9
11
12
13, 17
14
15
16
OUTPUT Channel D Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in system.
VDD_CD POWER 3.3 V power supply for Channel C and D. VDD pins must be externally connected to power supply.
EQD
FGD
INPUT EQ select for channel D. 4−level input pin. Internal 100 kW pull−up and 200 kW pull−down.
INPUT DC flat gain for channel D. 4−level input pin. Internal 100 kW pull−up and 200 kW pull−down.
EN_CD
INPUT Channel CD Enable. Internal 300 kW pull−up. High−Channel is in normal operation. Low−Channel is
in power down mode.
18
19
D_ RX+
D_ RX−
C_TX−
C_TX+
FGB
INPUT Channel D Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled in
system. UFP/DFP transmitter should provide this capacitor.
21
OUTPUT Channel C Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in system.
22
23
INPUT DC flat gain for channel B. 4−level input pin. Internal 100 kW pull−up and 200 kW pull−down.
INPUT EQ select for channel B. 4−level input pin. Internal 100 kW pull−up and 200 kW pull−down.
24
EQB
25
B_ RX+
B_ RX−
A_TX−
A_TX+
INPUT Channel B Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled in
system. UFP/DFP transmitter should provide this capacitor.
26
28
OUTPUT Channel A Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in system.
29
30, 34
31
VDD_AB POWER 3.3 V power supply for Channel A and B. VDD pins must be externally connected to power supply.
EQA
FGA
INPUT EQ select for channel A. 4−level input pin. Internal 100 kW pull−up and 200 kW pull−down.
INPUT DC flat gain for channel A. 4−level input pin. Internal 100 kW pull−up and 200 kW pull−down.
32
33
EN_AB
INPUT Channel AB Enable. Internal 300 kW pull−up. High−Channel is in normal operation. Low−Channel is
in power down mode.
EP
GND
GND
Exposed Pad (EP). EP on the package bottom is thermally connected to the die for improved heat
transfer out of the package. The exposed pad is electrically connected to the die and must be
soldered to GND on the PC board.
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NB7NPQ1404E2M
Power Management
Table 3. EQUALIZATION SETTING
The NB7NPQ1404E2M has an adaptive power
management feature in order to minimize power
consumption. When the receiver signal detector is idle, the
corresponding channel will change to low power slumber
mode. Accordingly, both channels will move to low power
slumber mode individually.
While in the low power slumber mode, the receiver signal
detector will continue to monitor the input channel. If a
channel is in low power slumber mode, the receiver
detection loop will be active again. If a load is not detected,
then the channel will move to Device Unplug Mode and
continuously monitor for the load. When a load is detected,
the channel will return to Low Power Slumber Mode and
receiver detection will be active again per 6 ms.
EQ A/B/C/D are the selection pins for the equalization.
EQA/B/C/D
Equalizer Setting (dB)
@2.5 GHz
@5 GHz
9.9
L (Tie 0−W to GND)
R (Tie Rext to GND)
F (Leave Open)
5.0
2.7
4.0
6.5
6.9
8.2 (Default)
12.1
H (Tie 0−W to VDD)
Table 4. FLAT GAIN SETTING
FGA/B/C/D are the selection pins for the DC gain.
FGA/B/C/D
Flat Gain Settings (dB)
L (Tie 0 W to GND)
R (Tie Rext to GND)
F (Leave Open)
−1.2
−0.2
Table 2. OPERATING MODES
+0.8 (Default)
+1.8
Mode
R
R
OUT
IN
H (Tie 0 W to VDD)
PD
67 kW to GND
High−Z
High−Z
Unplug Mode
40 kW to VDD
40 kW to VDD
Table 5. CHANNEL ENABLE SETTING
EN_AB / EN_CD are the channel enable pins for channels A&B
and C&D respectively.
Low Power
Slumber Mode
50 W to VDD
EN
0
Channel Enable Setting
Disabled
Active
50 W to VDD
50 W to VDD
1
Enabled (Default)
Table 6. ATTRIBUTES
Parameter
ESD Protection
Human Body Model
Charged Device Model
± 4 kV
> 1.5 kV
Moisture Sensitivity, Indefinite Time Out of Dry pack (Note 1)
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−O @ 0.125 in
81034
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test
1. For additional information, see Application Note AND8003/D.
Table 7. ABSOLUTE MAXIMUM RATINGS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
VDD
Min
−0.5
−0.5
−0.5
−25
Max
Unit
V
Supply Voltage (Note 2)
4.6
Voltage range at any input or output terminal
Differential I/O
LVCMOS inputs
V
V
+ 0.5
V
DD
DD
+ 0.5
V
Output Current
+25
mA
W
Power Dissipation, Continuous
1.2
150
125
34
Storage Temperature Range, T
−65
°C
°C
°C/W
°C
SG
Maximum Junction Temperature, T
J
Junction−to−Ambient Thermal Resistance @ 500 lfm, q (Note 3)
JA
Wave Solder, Pb−Free, T
265
SOL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. All voltage values are with respect to the GND terminals.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB7NPQ1404E2M
Table 8. RECOMMENDED OPERATING CONDITIONS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
Min
3.0
−40
75
Typ
Max
3.6
Unit
V
V
DD
Main power supply
3.3
T
A
Operating free−air temperature
AC coupling capacitor
Industrial Temperature Range
+85
265
°C
nF
C
100
AC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 9. POWER SUPPLY CHARACTERISTICS and LATENCY
Typ
(Note 4)
Symbol
Parameter
Test Conditions
Min
Max
3.6
Unit
V
VDD
Supply Voltage
3.0
3.3
IDD
Active mode current EN_AB & EN_CD = 1, 10 Gbps, compliance test pattern
Low Power Slumber EN_AB & EN_CD = 1, no input signal longer than TLP-
250
334
1.3
mA
mA
Active
LPSlumber
IDD
0.8
mode current
Slumber
IDD
Unplug mode current EN_AB & EN_CD = 1, no output load is detected
0.5
50
0.8
mA
Unplug
IDDpd
Power−down mode EN_AB & EN_CD = 0
100
mA
current
tpd
Latency
From Input to Output
2
ns
4. TYP values use VDD = 3.3 V, T = 25°C
A
Table 10. LVCMOS CONTROL PIN CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
2−Level Control Pins LVCMOS Inputs (EN_AB, EN_CD)
V
DC Input Logic High
DC Input Logic Low
0.65 x VDD
GND
VDD
GND
VDD
0.35 x VDD
25
V
V
IH
V
IL
I
IH
High−level input current
Low−level input current
mA
mA
I
IL
−25
4−Level Control Pins LVCMOS Inputs (EQA/B/C/D, FGA/B/C/D)
V
DC Input Logic High; Setting “H”
DC Input Logic 2/3 VDD; Setting “F”
DC Input Logic 1/3 VDD; Setting “R”
DC Input Logic Low; Setting “L”
High−level input current
Input pin connected to VDD
0.92 x VDD
VDD
V
V
IH
V
Input pin is left floating (Open) (Note 5) 0.59 x VDD 0.67*VDD 0.75 x VDD
68 kW must be between pin and GND 0.25 x VDD 0.33*VDD 0.41 x VDD
ext
IF
V
IR
R
V
V
Input pin connected to GND
GND
68
0.08 x VDD
50
V
IL
I
IH
mA
mA
kW
I
IL
Low−level input current
−50
R
External Resistor for input setting “R”
Rext connect to GND (± 5%)
64.6
71.4
ext
5. Floating refers to a pin left in an open state, with no external connections.
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NB7NPQ1404E2M
Table 11. CML RECEIVER AC/DC CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
72
Typ
Max
120
30
Unit
W
R
Differential Input Impedance (DC)
100
RX−DIFF−DC
R
Single−ended Input Impedance (DC) Measured with respect to GND
18
W
RX−SINGLE−DC
over a voltage of 500 mV max.
ZRX−HIZ−DC−PD Common−mode input impedance for VCM = 0 to 500 mV
25
75
kW
V>0 during reset or power−down
(DC)
Cac_coupling
AC coupling capacitance
265
150
200
nF
VRX−CM−AC−P
Common mode peak voltage
AC up to 5 GHz
mVpeak
mVpeak
VRX−CM−DC−Active Rx AC common mode voltage during Measured at Rx pins into a pair of
−Idle−Delta−P
the U1 to U0 transition
50 W terminations into ground.
Includes Tx and channel
conversion, AC range up to 5 GHz
VRX−CM−DC−Conn Instantaneous DC common mode
Apply to all link states and
−0.5
−0.3
1
1
V
V
(Note 6, Note 7)
voltage coupled from the far−end Tx during power−on, and power−off
when Rx termination is
equivalent of 200 kW
VRX−CM−DC−Conn Instantaneous DC common mode
Apply to all link states and
(Note 6, Note 7)
voltage coupled from the far−end Tx during power−on, and power−off
when Rx termination is 50 W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Not include +/−250 mV AC ground offset.
7. The receiver supports legacy implementations with VTX−DC+AC−CONN common mode transient up to 2.2 V.
Table 12. TRANSMITTER AC/DC CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
V
R
Output differential p−p voltage swing Differential Swing |V
−V |
TX−D−
0.8
1.0
1.2
VPPd
TX−DIFF−PP
TX−D+
at 100 MHz
Differential TX impedance (DC)
72
100
120
600
W
TX−DIFF−DC
TX−RCV−DET
V
Voltage change allowed during re-
ceiver detect
mV
Cac_coupling
AC coupling capacitance
75
265
nF
UI
UI
UI
UI
pF
W
TTX−EYE(10 Gbps) Transmitter eye, Include all jitter
TTX−EYE(5 Gbps) Transmitter eye, Include all jitter
TTX−DJ−DD(10 Gbps) Transmitter deterministic jitter
TTX−DJ−DD(5 Gbps) Transmitter deterministic jitter
At the silicon pad. 10 Gbps
At the silicon pad. 5 Gbps
At the silicon pad. 10 Gbps
At the silicon pad. 5 Gbps
0.646
0.625
0.17
0.205
1.1
Ctxparasitic
Parasitic capacitor for TX
RTX−DC−CM
Common−mode output impedance
(DC)
18
30
VTX−DC−CM
VTX−DC−CM
VTX−C
Instantaneous allowed DC common 200 kW single ended receiver load
mode voltage at the connector side
−0.5
1
1
V
V
V
of the AC coupling capacitors
Instantaneous allowed DC common 50 W single ended receiver load
mode voltage at the connector side
of the AC coupling capacitors
−0.3
Common−mode voltage
|V
+V |/2
TX−D−
VDD –
1.5
VDD
100
TX−D+
VTX−CM−AC−PP− TX AC common−mode peak−to−
Active peak voltage swing in active mode
V
+V
for both time and
mV
PP
TX−D+
TX−D−
amplitude
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NB7NPQ1404E2M
Table 12. TRANSMITTER AC/DC CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol Parameter Test Conditions
Active_ Common mode delta voltage Between U0 to U1
Min
Typ
Max
Unit
V
200
mVpeak
TX−CM−DC−
Idle−Delta
|AvgU0(|V
+V |)/2
TX−D−
TX−D+
–AvgU1(|V
+V |)/2|
TX−D−
TX−D+
V
Idle mode AC common mode delta
voltage |V −V
Between TX+ and TX− in idle
10
10
mVppd
mV
TX−Idle−DIFF−AC−pp
|
TX−D−
mode. Use the HPF to remove DC
components. 1/LPF. No AC and DC
signals are applied to RX terminals.
TX−D+
V
Idle mode DC common mode delta
voltage |V −V
Between TX+ and TX− in idle
TX−Idle−DIFF−DC
|
TX−D−
mode. Use the LPF to remove DC
components. 1/HPF. No AC and DC
signals are applied to RX terminals.
TX−D+
CHANNEL PERFORMANCE
Gp
GF
Peaking gain (Compensation at
5 GHz, relative to 100 MHz,
100 mVp−p sine wave input)
EQx = L
EQx = R
EQx = F
EQx = H
9.9
6.9
8.2
dB
12.1
Variation around typical
−3
−3
+3
+3
dB
dB
Flat Gain (<100 MHz, EQx=F)
FGx = L
FGx = R
FGx = F
FGx = H
−1.2
−0.2
+0.8
+1.8
Variation around typical
dB
V
−1 dB compression point output
1000
800
mVppd
SW_100M
swing (100 MHz)
V
−1 dB compression point output
swing (5 GHz)
mVppd
dB
SW_5G
DDNEXT
Differential near−end crosstalk
(Note 8)
100 MHz to 5 GHz, Figure 5
−40
SIGNAL AND FREQUENCY DETECTORS
Vth_dsm
Low power slumber mode detector
LFPS signal threshold in Low power
Slumber mode
100
45
600
175
mVppd
mVppd
threshold
Vth_am
Active mode detector threshold
Signal threshold in Active and
Slumber mode (Note 9)
8. Measured using a vector network analyzer (VNA) with −15 dbm power level applied to the adjacent input. The VNA detects the signal at the
output of the victim channel. All other inputs and outputs are terminated with 50 W.
9. Below the minimum is no signal ≥ 25°C. Above the maximum is active.
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NB7NPQ1404E2M
PARAMETER MEASUREMENT DIAGRAMS
Rx−
V
OH
80%
Rx+
t
t
diff−HL
diff−LH
20%
Tx−
V
OL
t
t
F
R
Tx+
Figure 3. Propagation Delay
Figure 4. Output Rise and Fall Times
B_RX+
B_RX−
Figure 5. Channel−Isolation Test Configuration
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NB7NPQ1404E2M
Figure 6. Power Up Timing
Test Conditions
Table 13. POWER UP TIMING
Symbol
Parameter
Min
Typ
Max
Unit
Td_EN
VDD to Enable Assertion timing
requirement
Figure 6.
0
ms
T_VCM
Stabilization time for VCM
Figure 6.
330
400
ms
Figure 7. Power Down Timing
Table 14. POWER DOWN TIMING
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
Td_OFF
Delay time required from EN
de−assertion until VDD is powered off
Figure 7.
900
ms
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NB7NPQ1404E2M
APPLICATION GUIDELINES
LFPS Compliance Testing
bias the control pins to the correct voltage to achieve this if
the pin is not connected to a voltage source. The low Setting
“L” is set by pulling the control pin to ground. Likewise the
high setting “H” is set by pulling the pin high to VCC. The
Rexternal setting can be set by adding a 68 kW resistor from
the control pin to ground. This will bias the Redriver internal
voltage to 33% of VCC.
As part of USB 3.2 compliance test, the host or peripheral
must transmit a LFPS signal that adheres to the spec
parameters. The NB7NPQ1404E2M is tested as a part of a
USB compliant system to ensure that it maintains
compliance while increasing system performance.
LFPS Functionality
USB 3.2 Low Frequency Periodic Signaling.
Linear Equalization
(LFPS) to implement functions like exiting low−power
modes, performing warm resets and providing link training
between host and peripheral devices. LFPS signaling
consists of bursts of frequencies ranging between 10 to
50 MHz and can have specific burst lengths or repeat rates.
The linear equalization that the NB7NPQ1404E2M
provides compensates for losses that occur naturally along
board traces and cable lines. Linear Equalization boosts high
frequencies and lower frequencies linearly so when
transmitting at varying frequencies, the voltage amplitude
will remain consistent. This compensation electrically
counters losses and allows for longer traces to be possible
when routing.
Ping.LFPS for TX Compliance
During the transmitter compliance, the system under test
must transmit certain compliance patterns as defined by the
USB−IF. In order to toggle through these patterns for various
tests, the receiver must receive a ping.LFPS signal from
either the test suite or a separate pattern generator. The
standard signal comprises of a single burst period of 100 ns
at 20 MHz.
DC Flat Gain
DC flat gain equally boosts high and low frequency
signals, and is essential for countering low frequency losses.
DC flat gain can also be used to simulate a higher input
signal from a USB Controller. If a USB controller can only
provide 800 mV differential to a receiver, it can be boosted
to 1128 mV using 2 dB of flat gain.
Control Pin Settings
Control pins A1, A0, B1, and B0 control the Flat Gain and
the Equalization of channels A and B and control pins C1,
C0, D1, and D0 control the Flat Gain and the Equalization
of channels C and D of the NB7NPQ1404E2M Device.
The Float (Default) Setting “F” can be set by leaving the
control pins in a floating state. The Redriver will internally
Total Gain
When using Flat Gain with Equalization in a USB
application it is important to make sure that the total voltage
does not exceed 1200 mV. Total gain can be calculated by
adding the EQ gain to the FG.
Typical Layout Practices
• RX and TX pairs should maintain as close to a 90 W
differential impedance as possible.
• Limit the number of vias used on each data line. It is
suggested that two or fewer are used.
• Traces should be routed as straight and symmetric as
possible.
• RX and TX differential pairs should always be placed and
routed on the same layer directly above a ground plane.
This will help reduce EMI and noise on the data lines.
• Routing angles should be obtuse angles and kept to 135
degrees or larger.
• To minimize crosstalk, TX and RX data lines should be
kept away from other high speed signals.
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NB7NPQ1404E2M
NB7NPQ1404E2M
Up to 11 dB Loss
Up to 3 dB Loss
A_RX−
A_TX−
220nF
220nF
220nF
220nF
Receiver/
Equalizer
Driver
USB 3.2
USB 3.2
Controller
Receptacle
A_TX+
B_RX−
A_RX+
B_TX−
ESD
Protection
220nF
220nF
330nF
330nF
(Type−C
or Type−A)
Receiver/
Equalizer
Driver
B_RX+
B_TX+
Enable
A_B
Enable
C_D
C_TX−
C_RX−
220nF
220nF
220nF
220nF
Receiver/
Equalizer
Driver
USB 3.2
USB 3.2
Controller
Receptacle
C_TX+
D_RX−
C_RX+
D_TX−
ESD
Protection
330nF
330nF
220nF
220nF
(Type−C
or Type−A)
Receiver/
Equalizer
Driver
D_RX+
D_TX+
Figure 8. Typical Application
Table 15. DESIGN REQUIREMENTS
Design Parameter
Value
Supply Voltage
3.3 V nominal, (3.0 V to 3.6 V)
Operation Mode (Control Pin Selection)
TX AC Coupling Capacitors
Floating by Default, adjust for application losses
220 nF nominal, 75 nF to 265 nF, see Figure 8
330 − 470 nF nominal, see Figure 8
RX AC Coupling Capacitors
Power Supply Capacitors
100 nF to GND close to each VCC pin, and 10 mF to GND on the VCC plane
Trace loss of FR4 before NB7NPQ1404E2M (Note 10)
Trace loss of FR4 after NB7NPQ1404E2M (Note 10)
Linear Range at 5 GHz
Up to 11 dB Losses
Up To 3 dB Losses. Keep as short as possible for best performance.
900 mV differential
−1.2 dB, −0.2 dB, +0.8 dB, +1.8 dB
6.9 to 12.1 dB
DC Flat Gain Options
Equalization Options
Differential Trace Impedance
90 W ± 10%
10.Trace loss of FR4 was estimated to have 1 dB of loss per 1 inch of FR4 length with matched impedance and no VIAS.
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UQFN34 2.5x4.5, 0.35P
CASE 523BR
ISSUE A
DATE 10 DEC 2020
GENERIC
MARKING DIAGRAM*
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
XXXX
XXXX
ALYWG
G
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
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DOCUMENT NUMBER:
DESCRIPTION:
98AON26127H
UQFN34 2.5x4.5, 0.35P
PAGE 1 OF 1
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