NB7NPQ1004MMTTWG [ONSEMI]
3.3V USB 3.1 Gen-2 10Gbps Quad Channel Dual Port Linear Redriver;
| 型号： | NB7NPQ1004MMTTWG |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V USB 3.1 Gen-2 10Gbps Quad Channel Dual Port Linear Redriver 驱动 接口集成电路 驱动器 |
| 文件： | 总11页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB7NPQ1004M
3.3 V USB 3.1 Gen-2
10ꢀGbps Quad Channel /
Dual Port Linear Redriver
Description
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The NB7NPQ1004M is a high performance 2−Port linear redriver
designed for USB 3.1 Gen 1 and USB 3.1 Gen 2 applications that
supports both 5 Gbps and 10 Gbps data rates. Signal integrity degrades
from PCB traces, transmission cables, and inter−symbol interference
(ISI). The NB7NPQ1004M compensates for these losses by engaging
varying levels of equalization at the input receiver, and flat gain
amplification on the output transmitter.
The NB7NPQ1004M offers programmable equalization and flat
gain for each independent channel to optimize performance over
various physical mediums.
MARKING
DIAGRAM
NB7N
1004
ALYWG
1
WQFN42
CASE 510AP
The NB7NPQ1004M contains an automatic receiver detect function
which will determine whether the output is active. The receiver
detection loop will be active if the corresponding channel’s signal
detector is idle for a period of time. The channel will then move to
Unplug Mode if a load is not detected, or it will return to Low Power
Mode (Slumber mode) due to inactivity.
NB7N1004 = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
The NB7NPQ1004M comes in a 3.5 x 9 mm WQFN42 package and
is specified to operate across the entire industrial temperature range,
–40°C to 85°C.
ORDERING INFORMATION
†
Device
NB7NPQ1004MMTTWG WQFN42 5000 / Tape
(Pb−Free) & Reel
Package Shipping
Features
• 3.3 V ± ±0.3 V Power Supply
• 5 Gbps & 10 Gbps Serial Link with Linear Amplifier
• Device Supports USB 3.1 Gen 1 and USB 3.1 Gen 2 Data Rates
• Automatic Receiver Detection
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
• Integrated Input and Output Termination
• Pin Adjustable Receiver Equalization and Flat Gain
• 100−W Differential CML I/O’s
Typical Applications
• Auto Slumber Mode for Adaptive Power Management
• Hot−Plug Capable
• USB3.1 Type−A and Type−C Signal Routing
• Mobile Phone and Tablet
• Computer, Laptop and Notebook
• External Storage Device
• Docking Station and Dongle
• Active Cable, Back Planes
• Gaming Console, Smart T.V.
• ESD Protection ± 2 kV HBM
• Operating Temperature Range Industrial:
−40°C to +85°C
• Package: WQFN42, 3.5 x 9 mm
• This is a Pb−Free Device
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
June, 2018 − Rev. 0
NB7NPQ1004M/D
NB7NPQ1004M
EQA
NC
NC
NC
39
42
40
41
FGA
NC
1
2
38
37
36
35
34
33
32
EN_AB
NC
EQA
FGA
EN_AB
VDD
A_RX+
A_RX-
TEST1#
VDD
VDD
A_TX+
3
4
A_RX+
A_TX+
Receiver/
Equalizer
Driver
5
A_TX-
NC
A_RX−
A_TX−
6
VDD
7
B_TX+
B_RX+
Exposed
Pad
Receiver/
Equalizer
Driver
B_TX+
B_TX-
B_RX+
B_RX-
EQB
8
31
30
B_TX−
B_RX−
GND
9
EQB
FGB
10
11
12
13
14
15
16
17
29
28
27
26
25
24
23
22
FGC
EQC
FGB
FGC
EQC
C_RX-
C_RX+
VDD
C_TX-
C_TX+
VDD
C_RX−
C_RX+
C_TX−
Receiver/
Equalizer
Driver
NC
TEST2#
D_RX-
D_RX+
C_TX+
D_TX-
D_TX+
D_TX−
D_RX−
Receiver/
Equalizer
Driver
FGD
D_TX+
D_RX+
18
19
20
21
EQD
EN_CD
Figure 1. Logic Diagram of NB7NPQ1004M
Figure 2. WQFN−42 Package Pinout
(Top View)
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2
NB7NPQ1004M
Table 1. PIN DESCRIPTION
Pin Number
Pin Name
Type
INPUT
INPUT
Description
1
2
FGA
DC flat gain for channel A. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down.
EN_AB
Channel AB Enable. Internal 300 k−W pull−up. High−Channel is in normal operation. Low−
Channel is in power down mode.
3
4
VDD
A_RX+
A_RX−
Test1#
VDD
POWER
INPUT
3.3 V power supply. VDD pins must be externally connected to power supply.
Channel A Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC−
coupled in system. UFP/DFP transmitter should provide this capacitor.
5
6
INPUT
POWER
OUTPUT
Connect to VDD is recommended.
7
3.3 V power supply. VDD pins must be externally connected to power supply.
8
B_TX+
B_TX−
FGC
Channel B Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in
system.
9
10
11
12
13
14
15
16
17
18
19
20
INPUT
INPUT
INPUT
DC flat gain for channel C. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down.
EQ select for channel C. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down.
EQC
C_RX−
C_RX+
VDD
Channel C Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC−
coupled in system. UFP/DFP transmitter should provide this capacitor.
POWER
NC
3.3 V power supply. VDD pins must be externally connected to power supply.
NC
No Connect pin: connect to VDD is recommended
D_TX−
D_TX+
EQD
OUTPUT
Channel D Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in
system.
INPUT
INPUT
INPUT
EQ select for channel D. 4−level input pin. Internal 100k−W pull−up and 200 k−W pull−down.
DC flat gain for channel D. 4−level input pin. Internal 100k−W pull−up and 200 k−W pull−down.
FGD
EN_CD
Channel CD Enable. Internal 300k−W pull−up. High−Channel is in normal operation. Low−
Channel is in power down mode.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VDD
D_ RX+
D_ RX−
Test2#
VDD
POWER
INPUT
3.3 V power supply. VDD pins must be externally connected to power supply.
Channel D Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC−
coupled in system. UFP/DFP transmitter should provide this capacitor.
INPUT
POWER
OUTPUT
Connect to VDD is recommended.
3.3 V power supply. VDD pins must be externally connected to power supply.
C_TX+
C_TX−
FGB
Channel C Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in
system.
INPUT
INPUT
INPUT
DC flat gain for channel B. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down.
EQ select for channel B. 4−level input pin. Internal 100 k−W pull−up and 200 k−W pull−down.
EQB
B_ RX−
B_ RX+
VDD
Channel B Differential CML input pair for 5 / 10 Gbps USB signals. Must be externally AC−
coupled in system. UFP/DFP transmitter should provide this capacitor.
POWER
NC
3.3 V power supply. VDD pins must be externally connected to power supply.
NC
No Connect pin: connect to VDD is recommended
A_TX−
A_TX+
VDD
OUTPUT
Channel A Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled in
system.
POWER
NC
3.3 V power supply. VDD pins must be externally connected to power supply.
37, 38, 39,
40, 41
NC
No Connect
42
EQA
GND
INPUT
GND
EQ select for channel A. 4−level input pin. Internal 100k−W pull−up and 200k−W pull−down.
EP
Exposed pad (EP). EP on the package bottom is thermally connected to the die for improved
heat transfer out of the package. The exposed pad is electrically connected to the die and
must be soldered to GND on the PC Board.
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3
NB7NPQ1004M
Power Management
Table 3. EQUALIZATION SETTING
The NB7NPQ1004M has an adaptive power management
feature in order to minimize power consumption. When the
receiver signal detector is idle, the corresponding channel
will change to low power slumber mode. Accordingly, both
channels will move to low power slumber mode
individually.
While in the low power slumber mode, the receiver signal
detector will continue to monitor the input channel. If a
channel is in low power slumber mode, the receiver
detection loop will be active again. If a load is not detected,
then the channel will move to Device Unplug Mode and
continuously monitor for the load. When a load is detected,
the channel will return to Low Power Slumber Mode and
receiver detection will be active again per 6 ms.
EQ A/B/C/D are the selection pins for the equalization.
EQA/B/C/D
Equalizer Setting (dB)
@2.5 GHz
@5 GHz
10.9
L (Tie 0−W to GND)
R (Tie Rext to GND)
F (Leave Open)
5.1
1.9
3.5
6.8
6.7
8.9 (Default)
13.1
H (Tie 0−W to VDD)
Table 4. FLAT GAIN SETTING
FGA/B/C/D are the selection pins for the DC gain.
FGA/B/C/D
Flat Gain Settings (dB)
L (Tie 0−W to GND)
R (Tie Rext to GND)
F (Leave Open)
−3
−1.5
Table 2. OPERATING MODES
0 (Default)
+2
Mode
R
R
OUT
IN
H (Tie 0−W to VDD)
PD
67 k−W to GND
High−Z
High−Z
Table 5. CHANNEL ENABLE SETTING
EN_AB / EN_CD are the channel enable pins for channels A&B
and C&D respectively.
Unplug Mode
40 k−W to VDD
40 k−W to VDD
Low Power
Slumber Mode
50−W to VDD
EN
0
Channel Enable Setting
Disabled
Active
50−W to VDD
50−W to VDD
1
Enabled (Default)
Table 6. ATTRIBUTES
Parameter
ESD Protection
Human Body Model
Charged Device Model
± 2 kV
> 1.5 kV
Moisture Sensitivity, Indefinite Time Out of Dry pack (Note 1)
Flammability Rating
Level 1
UL 94 V−O @ 0.125 in
81034
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test
1. For additional information, see Application Note AND8003/D.
Table 7. ABSOLUTE MAXIMUM RATINGS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
VDD
Min
−0.5
−0.5
−0.5
−25
Max
Unit
V
Supply Voltage (Note 2)
4.6
Voltage range at any input or output terminal
Differential I/O
LVCMOS inputs
V
V
+ 0.5
V
DD
DD
+ 0.5
V
Output Current
+25
mA
W
Power Dissipation, Continuous
1.2
150
125
34
Storage Temperature Range, T
−65
°C
°C
°C/W
°C
SG
Maximum Junction Temperature, T
J
Junction−to−Ambient Thermal Resistance @ 500 lfm, Ø (Note 3)
JA
Wave Solder, Pb−Free, T
265
SOL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. All voltage values are with respect to the GND terminals.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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4
NB7NPQ1004M
Table 8. RECOMMENDED OPERATING CONDITIONS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
Min
3.0
−40
75
Typ
Max
3.6
Unit
V
V
DD
Main power supply
3.3
T
A
Operating free−air temperature
AC coupling capacitor
Industrial Temperature Range
+85
265
°C
nF
C
100
AC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 9. POWER SUPPLY CHARACTERISTICS and LATENCY
Typ
(Note )
Symbol
Parameter
Test Conditions
Min
Max
3.6
Unit
V
VDD
Supply Voltage
3.0
3.3
IDD
Active mode current EN_AB & EN_CD = 1, 10 Gbps, compliance test pattern
225
334
1.2
mA
mA
Active
LPSlumber
IDD
Low Power Slumber EN_AB & EN_CD = 1, no input signal longer than TLP-
0.8
mode current
Slumber
IDD
Unplug mode current EN_AB & EN_CD = 1, no output load is detected
0.5
20
0.75
100
mA
Unplug
IDDpd
Power−down mode EN_AB & EN_CD = 0
mA
current
tpd
Latency
From Input to Output
2
ns
4. TYP values use VDD = 3.3 V, TA = 25°C
Table 10. LVCMOS CONTROL PIN CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
2−Level Control Pins LVCMOS Inputs (EN_AB, EN_CD)
V
DC Input Logic High
DC Input Logic Low
0.65 x VDD
GND
VDD
GND
VDD
0.35 x VDD
25
V
V
IH
V
IL
I
IH
High−level input current
Low−level input current
mA
mA
I
IL
−25
4−Level Control Pins LVCMOS Inputs (EQA/B/C/D, FGA/B/C/D)
V
DC Input Logic High; Setting “H”
DC Input Logic 2/3 VDD; Setting “F”
DC Input Logic 1/3 VDD; Setting “R”
DC Input Logic Low; Setting “L”
High−level input current
Input pin connected to VDD
0.92 x VDD
VDD
V
V
IH
V
Input pin is left floating (Open) (Note 5) 0.59 x VDD 0.67*VDD 0.75 x VDD
68 kW must be between pin and GND 0.25 x VDD 0.33*VDD 0.41 x VDD
ext
IF
V
IR
R
V
V
Input pin connected to GND
GND
0.08 x VDD
50
V
IL
I
IH
mA
mA
kW
I
IL
Low−level input current
−50
R
External Resistor for input setting “R”
Rext connect to GND (± 5%)
64.6
68
71.4
ext
5. Floating refers to a pin left in an open state, with no external connections.
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NB7NPQ1004M
Table 11. CML RECEIVER AC/DC CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
72
Typ
Max
120
30
Unit
W
R
Differential Input Impedance (DC)
Single−ended Input Impedance (DC)
100
RX−DIFF−DC
R
Measured with respect to GND over
a voltage of 500 mV max.
18
W
RX−SINGLE−DC
ZRX−HIZ−DC−PD Common−mode input impedance for
V>0 during reset or power−down (DC)
VCM = 0 to 500 mV
25
75
kW
Cac_coupling
AC coupling capacitance
265
150
200
nF
VRX−CM−AC−P Common mode peak voltage
VRX−CM−DC−Acti Common mode peak voltage
AC up to 5 GHz
mVpeak
mVpeak
Between U0 and U1. AC up to
5 GHz
ve−Idle−Delta−P
|AvgU0(|V
+V |)/2
RX−D−
RX−D+
–AvgU1(|V
+V |)/2|
RX−D−
RX−D+
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 12. TRANSMITTER AC/DC CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Parameter
Test Conditions
Differential Swing |V −V |
TX−D−
Min
Typ
Max
Unit
V
R
Output differential p−p voltage
swing at 100 MHz
1.2
VPPd
TX−DIFF−PP
TX−D+
Differential TX impedance (DC)
72
100
120
600
W
TX−DIFF−DC
TX−RCV−DET
V
Voltage change allowed during re-
ceiver detect
mV
Cac_coupling
AC coupling capacitance
75
265
nF
UI
UI
UI
UI
pF
W
TTX−EYE(10Gbps) Transmitter eye, Include all jitter
TTX−EYE(5Gbps) Transmitter eye, Include all jitter
TTX−DJ−DD(10Gbps) Transmitter deterministic jitter
TTX−DJ−DD(5Gbps) Transmitter deterministic jitter
At the silicon pad. 10Gbps
At the silicon pad. 5Gbps
At the silicon pad. 10Gbps
At the silicon pad. 5Gbps
0.646
0.625
0.17
0.205
1.1
Ctxparasitic
Parasitic capacitor for TX
RTX−DC−CM
Common−mode output imped−
ance (DC)
18
0
30
VTX−DC−CM
VTX−C
Instantaneous allowed DC com-
mon mode voltage at the connec-
tor side of the AC coupling capaci-
tors
|V
|V
+V
+V
|/2
|/2
2.2
V
TX−D+
TX−D+
TX−D−
Common−mode voltage
VDD –
1.5
VDD
100
200
V
TX−D−
VTX−CM−AC−PP− TX AC common−mode peak−to−
V
TX−D+
+V
TX−D−
for both time and am-
mV
PP
Active
peak voltage swing in active mode plitude
V
Active_ Common mode delta voltage
Between U0 to U1
mVpeak
mVppd
TX−CM−DC−
Idle−Delta
|AvgU0(|V
+V |)/2
TX−D−
TX−D+
–AvgU1(|V
+V
TX−D−
|)/2|
TX−D+
V
Idle mode AC common mode delta Between TX+ and TX− in idle mode.
10
10
TX−Idle−DIFF−AC−pp
voltage |V
−V
|
Use the HPF to remove DC compo-
nents. 1/LPF. No AC and DC signals
are applied to RX terminals.
TX−D+
TX−D−
V
Idle mode DC common mode
delta voltage |V −V
Between TX+ and TX− in idle mode.
Use the LPF to remove DC compo-
nents. 1/HPF. No AC and DC signals
are applied to RX terminals.
mV
TX−Idle−DIFF−DC
|
TX−D−
TX−D+
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NB7NPQ1004M
Table 12. TRANSMITTER AC/DC CHARACTERISTICS
VDD = 3.3 V +/− 0.3 V Over operating free−air temperature range (unless otherwise noted)
Parameter Test Conditions
CHANNEL PERFORMANCE
Min
Typ
Max
Unit
Gp
Peaking gain (Compensation at
5 GHz, relative to 100 MHz,
100 mVp−p sine wave input)
EQx = L
EQx = R
EQx = F
EQx = H
10.9
6.7
8.9
dB
13.1
Variation around typical
−3
−3
+3
+3
dB
dB
GF
Flat Gain (100 MHz, EQx=F)
FGx = L
FGx = R
FGx = F
FGx = H
−3
−1.5
0
+2
Variation around typical
dB
V
−1 dB compression point output
1000
750
−40
0.6
0.5
0.8
1
mVppd
SW_100M
swing (100 MHz)
V
−1 dB compression point output
swing (5 GHz)
mVppd
dB
SW_5G
DDNEXT
Differential near−end crosstalk
(Note 6)
100 MHz to 5GHz, Figure 6
Vnoise−input
Input−referred noise (Note 7)
Output−referred noise (Note 7)
100 MHz to 5 GHz, FGx = 1, EQx = R
Figure 7
mVRMS
100 MHz to 5 GHz, FGx = 1, EQx = 1
Figure 7
Vnoise−output
100 MHz to 5 GHz, FGx = 1, EQx = R
Figure 7
mVRMS
100 MHz to 5 GHz, FGx = 1, EQx = 1
Figure 7
SIGNAL AND FREQUENCY DETECTORS
Vth_dsm
Low power slumber mode detector LFPS signal threshold in Low power
100
45
600
175
mVppd
mVppd
threshold
Slumber mode
Vth_am
Active mode detector threshold
Signal threshold in Active and Slumber
mode
6. Measured using a vector network analyzer (VNA) with −15 dbm power level applied to the adjacent input. The VNA detects the signal at the
output of the victim channel. All other inputs and outputs are terminated with 50−W.
7. Guaranteed by design and characterization.
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NB7NPQ1004M
PARAMETER MEASUREMENT DIAGRAMS
Rx−
V
OH
80%
Rx+
t
t
diff−HL
diff−LH
20%
Tx−
V
OL
t
t
F
R
Tx+
Figure 3. Propagation Delay
Figure 4. Output Rise and Fall Times
APPLICATION GUIDELINES
LFPS Compliance Testing
bias the control pins to the correct voltage to achieve this if
the pin is not connected to a voltage source. The low Setting
“L” is set by pulling the control pin to ground. Likewise the
high setting “H” is set by pulling the pin high to VCC. The
Rexternal setting can be set by adding a 68−K resistor from the
control pin to ground. This will bias the Redriver internal
voltage to 33% of VCC.
As part of USB 3.1 compliance test, the host or peripheral
must transmit a LFPS signal that adheres to the spec
parameters. The NB7NPQ1004M is tested as a part of a USB
compliant system to ensure that it maintains compliance
while increasing system performance.
LFPS Functionality
USB 3.1, Gen1 and Gen2 use Low Frequency Periodic
Signaling.
Linear Equalization
The linear equalization that the NB7NPQ1004M provides
compensates for losses that occur naturally along board
traces and cable lines. Linear Equalization boosts high
frequencies and lower frequencies linearly so when
transmitting at varying frequencies, the voltage amplitude
will remain consistent. This compensation electrically
counters losses and allows for longer traces to be possible
when routing.
(LFPS) to implement functions like exiting low−power
modes, performing warm resets and providing link training
between host and peripheral devices. LFPS signaling
consists of bursts of frequencies ranging between 10 to
50 MHz and can have specific burst lengths or repeat rates.
Ping.LFPS for TX Compliance
During the transmitter compliance, the system under test
must transmit certain compliance patterns as defined by the
USB−IF. In order to toggle through these patterns for various
tests, the receiver must receive a ping.LFPS signal from
either the test suite or a separate pattern generator. The
standard signal comprises of a single burst period of 100 ns
at 20 MHz.
DC Flat Gain
DC flat gain equally boosts high and low frequency
signals, and is essential for countering low frequency losses.
DC flat gain can also be used to simulate a higher input
signal from a USB Controller. If a USB controller can only
provide 800 mV differential to a receiver, it can be boosted
to 1128 mV using 2 dB of flat gain.
Control Pin Settings
Control pins A1, A0, B1, and B0 control the Flat Gain and
the Equalization of channels A and B and control pins C1,
C0, D1, and D0 control the Flat Gain and the Equalization
of channels C and D of the NB7NPQ7041M Device.
The Float (Default) Setting “F” can be set by leaving the
control pins in a floating state. The Redriver will internally
Total Gain
When using Flat Gain with Equalization in a USB
application it is important to make sure that the total voltage
does not exceed 1200 mV. Total gain can be calculated by
adding the EQ gain to the FG.
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NB7NPQ1004M
NB7NPQ1004M
Up to 3 dB Loss
Up to 11 dB Loss
A RX
A TX
100nF
100nF
100nF
USB 3.1
Receptacle
(Type-C or Type-A)
Receiver/
Equalizer
USB 3.1
Controller
Driver
100nF
ESD
Protection
100nF
100nF
330-470nF
330-470nF
Receiver/
Equalizer
220K
Driver
220K
B TX
B RX
C RX
C TX
100nF
100nF
100nF
100nF
USB 3.1
Receptacle
(Type-C or Type-A)
Receiver/
Equalizer
USB 3.1
Controller
Driver
ESD
Protection
100nF
100nF
330-470nF
330-470nF
Receiver/
Equalizer
220K
Driver
220K
D TX
D RX
Figure 5. Typical Application
Table 13. DESIGN REQUIREMENTS
Design Parameter
Value
Supply Voltage
3.3 V nominal, (3.135 V to 3.465 V)
Operation Mode (Control Pin Selection)
TX AC Coupling Capacitors
RX AC Coupling Capacitors
Floating by Default, adjust for application losses
100 nF nominal, 75 nF to 265 nF, see Figure 5
330 − 470 nF nominal, see Figure 5
68 kW, ± 5%
R
external
RX Pull Down Resistors at Receptacle
Power Supply Capacitors
200 KW to 220 KW
100 nF to GND close to each Vcc pin, and 10 mF to GND on the Vcc plane
Trace loss of FR4 before NB7NPQ7021M
Trace loss of FR4 after NB7NPQ7021M
Linear Range at 5 GHz
Up to 11 dB Losses
Up To 3 dB Losses. Keep as short as possible for best performance.
900 mV differential
−3 dB, −1.5 dB, 0 dB, 2 dB
6.7 to 13.1 dB
DC Flat Gain Options
Equalization Options
Differential Trace Impedance
90 W ± 10%
8. Trace loss of FR4 was estimated to have 1 dB of loss per 1 inch of FR4 length with matched impedance and no VIAS.
Typical Layout Practices
• RX and TX pairs should maintain as close to a 90 W
differential impedance as possible.
• Limit the number of vias used on each data line. It is
suggested that 2 or fewer are used.
• RX and TX differential pairs should always be placed and
routed on the same layer directly above a ground plane.
This will help reduce EMI and noise on the data lines.
• Routing angles should be obtuse angles and kept to 135
degrees or larger.
• Traces should be routed as straight and symmetric as
possible.
• To minimize crosstalk, TX and RX data lines should be
kept away from other high speed signals.
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9
NB7NPQ1004M
B_RX+
B_RX−
Figure 6. Channel−Isolation Test Configuration
Figure 7. Noise Test Configuration
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10
NB7NPQ1004M
PACKAGE DIMENSIONS
WQFN42 3.5x9, 0.5P
CASE 510AP−01
ISSUE O
NOTES:
A B
D
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
L
L
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30 MM
FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
L1
DETAIL A
MILLIMETERS
ALTERNATE TERMINAL
CONSTRUCTIONS
E
DIM MIN
MAX
0.80
0.05
A
A1
A3
b
0.70
0.00
0.20 REF
EXPOSED Cu
MOLD CMPD
0.20
0.30
D
D2
E
3.50 BSC
0.15
C
1.95
2.15
9.00 BSC
E2
e
K
L
L1
7.45
0.50 BSC
0.20
0.30
0.00
7.65
0.15
C
DETAIL B
TOP VIEW
ALTERNATE
−−−
0.50
0.15
CONSTRUCTION
A
0.10
0.08
C
C
A3
RECOMMENDED
MOUNTING FOOTPRINT*
DETAIL B
NOTE 4
A1
K
SEATING
PLANE
9.30
C
04.62X3
2.16
SIDE VIEW
0.50
0.10
C
A
B
PITCH
3.80
D2
DETAIL A
22
1
42X
17
PACKAGE
OUTLINE
42X
L
0.35
DIMENSIONS: MILLIMETERS
42X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
b
E2
0.10
0.05
C
C
A
B
NOTE 3
1
38
0.10
C A
B
e
e/2
BOTTOM VIEW
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