PI6C49003A [PERICOM]
PCIe Gen 2 Networking Clock Generator;
| 型号： | PI6C49003A |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | PCIe Gen 2 Networking Clock Generator PC |
| 文件： | 总12页 (文件大小：843K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C49003A
PCIe®ꢀGen 2 Networking Clock Generator
Description
Features
TheꢀPI6C49003AꢀisꢀaꢀclockꢀgeneratorꢀdeviceꢀintendedꢀforꢀPCIe®ꢀ
Gen2ꢀnetworkingꢀapplications.ꢀTheꢀdeviceꢀincludesꢀfiveꢀ100MHzꢀ
differentialꢀHostꢀClockꢀSignalꢀLevelꢀ(HCSL)ꢀoutputsꢀforꢀPCIeꢀGenꢀ
2,ꢀtwoꢀsingle-endedꢀ50MHzꢀoutputs,ꢀoneꢀsingle-endedꢀ32.256MHzꢀ
output,ꢀandꢀoneꢀselectableꢀsingle-endedꢀ33/66/133MHzꢀoutput.
•ꢀ 3.3Vꢀ+/-10%ꢀSupplyꢀVoltage
•ꢀ Usesꢀ25MHzꢀxtalꢀ
•ꢀ FiveꢀPCIe®ꢀGen.ꢀ2ꢀ100MHzꢀHCSLꢀoutputsꢀwithꢀoptionalꢀ
-0.5%ꢀspreadꢀspectrumꢀsupportꢀ
•ꢀ TwoꢀLVCMOSꢀ50MHzꢀoutputsꢀthatꢀsupportꢀ+/-ꢀ10%ꢀ
frequencyꢀmargining
UsingꢀaꢀseriallyꢀprogrammableꢀSMBUSꢀinterface,ꢀtheꢀPI6C49003Aꢀ
incorporatesꢀspreadꢀspectrumꢀmodulationꢀonꢀtheꢀtwelveꢀ100MHzꢀ
HCSLꢀPCIeꢀGenꢀ2ꢀoutputs,ꢀandꢀindependentꢀfrequencyꢀmarginingꢀ
onꢀ theꢀ 50MHzꢀ output,ꢀ 33.3333MHzꢀ andꢀ 66.6666MHzꢀ clockꢀ
outputs.
•ꢀ Oneꢀfrequencyꢀselectableꢀ33/66/133MHzꢀLVCMOSꢀoutput
•ꢀ Oneꢀ32.256MHzꢀLVCMOSꢀoutput
•ꢀ Industrialꢀtemperatureꢀ-40°Cꢀtoꢀ85°C
•ꢀ Package:ꢀ48-pinꢀTSSOPꢀpackage
Pin Configuration
Block Diagram
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
VDD
14
VDD
IREF
GND
VDD
NC
NC
100M_Q0-
100M_Q0+
100M_Q1+
100M_Q1-
VDD
25 MHz
Clock Buffer/
crystal or
VDD
VDD
GND
GND
Crystal
5
clock input
Oscillator
100M_OUT(0-4)
GND
50M_OUT(1-2)
PLL, Dividers,
Buffers, and
Logic
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
9
VDD
GND
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
100M_Q2+
100M_Q2-
100M_Q3+
100M_Q3-
VDD
33/66/133M_OUT1
VDD
SCLK
SCLK
32.256M_OUT1
SDATA
SDATA
GND
PD_RESET
50M_Out1
50M_Out2
VDD
GND
VDD
10
100M_Q4+
100M_Q4-
33/66/133M_Out1
VDD
ISET
475 Ohms
1%
GND
GND
VDD
32.256M_Out1
GND
GND
NC
VDD
NC
X2
PD_RESET
X1
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Pin Description
Pin # Pin Name
Pin Type
Pin Description
1
V
Power
Output
3.3VꢀSupplyꢀPin
DD
2
IREF
NC
Connectꢀtoꢀ475-OhmꢀresistorꢀtoꢀsetꢀHCSLꢀoutputꢀdriveꢀcurrent
3
Noꢀconnect.ꢀLeaveꢀopen
4
NC
Noꢀconnect.ꢀLeaveꢀopen
5
V
V
Power
Power
Power
Power
Power
Power
Power
Input
3.3VꢀSupplyꢀPin
DD
DD
6
3.3VꢀSupplyꢀPin
7
GND
GND
Ground
8
Ground
9
V
3.3VꢀSupplyꢀPin
DD
10
11
12
13
14
GND
Ground
V
3.3VꢀSupplyꢀPin
DD
SCLK
SDATA
GND
SMBusꢀcompatibleꢀinputꢀclock.ꢀSupportsꢀfastꢀmodeꢀ400kHzꢀinputꢀclock.
I/O
SMBusꢀcompatibleꢀdataꢀline
Ground
Power
50MHzꢀLVCMOSꢀoutput.ꢀWhenꢀdisabled,ꢀoutputꢀisꢀtrisatedꢀandꢀhasꢀaꢀnominalꢀ110k-
Ohmꢀpull-down.ꢀ
15
16
50M_Out1
50M_Out2
Output
Output
50MHzꢀLVCMOSꢀoutput.ꢀWhenꢀdisabled,ꢀoutputꢀisꢀtrisatedꢀandꢀhasꢀaꢀnominalꢀ110k-
Ohmꢀpull-down.ꢀ
17
18
19
V
Power
Power
Power
3.3VꢀSupplyꢀPin
Ground
DD
GND
V
3.3VꢀSupplyꢀPin
DD
32.256MHzꢀLVCMOSꢀoutput.ꢀWhenꢀdisabled,ꢀoutputꢀisꢀtrisatedꢀandꢀhasꢀaꢀnominalꢀ
110k-Ohmꢀpull-down.ꢀ
20
32.256M_Out1
Output
Power
21
22
23
GND
NC
Ground
NC
Powerꢀdownꢀresetꢀ-ꢀwhenꢀlowꢀallꢀPLL'sꢀareꢀpoweredꢀdownꢀandꢀoutputsꢀtristated.ꢀ
SMBusꢀregistersꢀareꢀresetꢀtoꢀdefaultꢀvalues.ꢀ
24
25
26
Input
PD_RESET
X1
Input
Crystalꢀinput.ꢀIntegratedꢀ6pFꢀcapacitance
X2
Output
Crystalꢀoutput.ꢀIntegratedꢀ6pFꢀcapacitance
27
28
29
V
Power
Power
Power
3.3VꢀSupplyꢀPin
Ground
DD
GND
V
3.3VꢀSupplyꢀPin
DD
33/66/133MHzꢀselectableꢀLVCMOSꢀoutput.ꢀWhenꢀdisabled,ꢀoutputꢀisꢀtrisatedꢀandꢀhasꢀ
aꢀnominalꢀ110k-Ohmꢀpull-down.ꢀ
30
33/66/133M_Out1 Output
31
100M_Q4-
100M_Q4+
Output
Output
100MHzꢀHCSLꢀoutput
100MHzꢀHCSLꢀoutput
32
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Pin Description (Cont..)
Pin # Pin Name
Pin Type Pin Description
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
V
Power
Power
Power
Output
Output
Output
Output
Power
Power
Power
Output
Output
Output
Output
Power
Power
3.3VꢀSupplyꢀPin
Ground
DD
GND
V
3.3VꢀSupplyꢀPin
100MHzꢀHCSLꢀoutput
100MHzꢀHCSLꢀoutput
100MHzꢀHCSLꢀoutput
100MHzꢀHCSLꢀoutput
3.3VꢀSupplyꢀPin
Ground
DD
100M_Q3-
100M_Q3+
100M_Q2-
100M_Q2+
V
DD
GND
V
3.3VꢀSupplyꢀPin
100MHzꢀHCSLꢀoutput
100MHzꢀHCSLꢀoutput
100MHzꢀHCSLꢀoutput
100MHzꢀHCSLꢀoutput
3.3VꢀSupplyꢀPin
Ground
DD
100M_Q1-
100M_Q1+
100M_Q0+
100M_Q0-
V
DD
GND
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
50MHz Frequency Margining Table
33/66/133MHz Frequency Margining
Table
FS3 FS2
FS1
FS0 50M_OUT1,ꢀ50M_OUT2
FS6
FS5
FS4
33M/66M/133M_OUT1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
nominal
nominalꢀ+ꢀ1%
nominalꢀ+ꢀ2%
nominalꢀ+ꢀ3%
nominalꢀ+ꢀ4%
nominalꢀ+ꢀ5%
nominalꢀ+ꢀ6%
nominalꢀ+ꢀ8%
nominalꢀ+ꢀ10%
nominalꢀ-ꢀ1%
nominalꢀ-ꢀ2%
nominalꢀ-ꢀ3%
nominalꢀ-ꢀ4%
nominalꢀ-ꢀ6%
nominalꢀ-ꢀ8%
nominalꢀ-ꢀ10%
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
33.3333MHz
66.6666MHz +2%
66.6666MHz +1%
66.6666MHz +0%
66.6666MHz -2%
66.6666MHz -4%
66.6666MHz -6%
133.3333MHz
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Serial Data Interface (SMBus)
PI6C49003AꢀisꢀaꢀslaveꢀonlyꢀSMBusꢀdeviceꢀthatꢀsupportsꢀindexedꢀblockꢀreadꢀandꢀindexedꢀblockꢀwriteꢀprotocolꢀusingꢀaꢀsingleꢀ7-bitꢀad-
dressꢀandꢀread/writeꢀbitꢀasꢀshownꢀbelow.
Address Assignment
A6
A5
A4
A3
A2
A1
A0
W/R
1
1
0
1
0
0
1
0/1
How to Write
1 bit 8 bits
1
8 bits
1
8 bits
1
8 bits
1
8 bits
1
1 bit
Start
D2H
bit
Register
offset
Byte Count
= N
Data Byte
0
Data Byte
N - 1
Ack
Ack
Ack
Ack
…
Ack Stop bit
Note:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
How to Read (M:ꢀabbreviationꢀforꢀMasterꢀorꢀController;ꢀS:ꢀabbreviationꢀforꢀslave/clock)
1 bit 8 bits
1 bit
8 bits
1 bit
1 bit 8 bits 1 bit
8 bits
1 bit
8 bits
1 bit
…
8 bits
1 bit
1 bit
S:
S:
M: send
starting
databyte
location:
N
sends #
of data
bytes
that
will be
sent: X
sends
start-
sends ing
S:
M: Not
Ac-
knowl-
edge
M:
Start
bit
S:
sends
Ack
S:
M:
M:
S:
sends
Ack
M:
M:
sends
Ack
sends
data
byte
N+X-1
M:
Stop
bit
M: Send
"D2h"
sends Start Send
Ack bit "D3h"
…
Ack
data
byte
N
Byte 0: Spread Spectrum Control Register
Output(s)
Condition Affected
Power Up
Bit
Description
Type
Notes
0=spread off
Spread Spectrum Selection for 100MHz HCSL PCI-
Express clocks
All 100MHz HCSL
PCI Express outputs
7
RW
0
1 = -0.5% down spread
0 = hardware cntl
1 = soꢀware ctrl
Enables hardware or soꢀware control of OE bits (see
Byte 0–Bit 6 and Bit 5 Functionality table)
6
5
RW
RW
0
PD_RESET pin, bit 5
Soꢀware PD_RESET bit. Enables or disables all out-
puts
0 = disabled
1 = enabled
1
All outputs
(see Byte 0–Bit 6 and Bit 5 Functionality table)
Frequency margining select bit FS3
Frequency margining select bit FS2
Frequency margining select bit FS1
4
3
2
RW
RW
RW
1
0
1
See 50MHz Frequency
Margining Table on
Page 3
50M_Out1 and 50M_
Out2
1
0
Frequency margining select bit FS0
RW
RW
0
1
0 = disabled
1 = enabled
Single-ended 50MHz
output 50M_Out2
OE for single-ended 50MHz output 50M_Out2
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Byte 0 - Bit 6 and Bit 5 Functionality
Bit 6
Bit 5
Description
0
1
X
0
(PD_RESET = "H" will enable all outputs; SMBus cannot control each output.)
Disables all outputs and tri-states the outputs, PD_RESET HW pin/signal = DO NOT CARE
Enable outputs according to the SMBus default values; SMBus can control each output.
PD_RESET HW pin/signal = DON'T CARE
1
1
Byte 1: Control Register
Power Up Con-
dition
Bit
Description
Type
Output(s) Affected
Notes
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
7
OE for 32.256M_Out1
RW
1
1
1
1
0
0
0
0
32.256M_Out1
6
5
4
3
2
1
0
OE for 50M_Out1
RW
RW
RW
RW
RW
RW
RW
50M_Out1
33/66/133M_Out1
100M_Q11
100M_Q10
100M_Q9
OE for 33/66/133M_Out1
OE for 100M_Q11 HCSL output
OE for 100M_Q10 HCSL output
OE for 100M_Q09 HCSL output
OE for 100M_Q08 HCSL output
OE for 100M_Q07 HCSL output
100M_Q8
100M_Q7
Byte 2: Control Register
Power Up Con-
dition
Bit
Description
Type
Output(s) Affected
Notes
7
Frequency margining select bit FS6 RW
Frequency margining select bit FS5 RW
Frequency margining select bit FS4 RW
1
See 33/66/133MHz
Frequency Margin-
ing Table on Page 3
6
0
33/66/133M_Out1
Not Applicable
5
0
4 to 0
Reserved
R
Undefined
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Byte 3: Control Register
Power Up
Condition
Bit
Description
Type
Output(s) Affected
Notes
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
7
OE for 100M_Q6 HCSL Output
RW
0
0
0
0
0
1
100M_Q6
6
5
4
3
2
OE for 100M_Q5 HCSL Output
OE for 100M_Q4 HCSL Output
OE for 100M_Q3 HCSL Output
OE for 100M_Q2 HCSL Output
OE for 100M_Q1 HCSL Output
RW
RW
RW
RW
RW
100M_Q5
100M_Q4
100M_Q3
100M_Q2
100M_Q1
1
0
OE for 100M_Q0 HCSL Output
Reserved
RW
R
1
100M_Q0
Undefined
Not Applicable
Byte 4 & 5: Control Register
Power Up Con-
dition
Bit
Description
Type
Output(s) Affected
Notes
Notes
7 to 0
Reserved
R
Undefined
Not Applicable
Byte 6: Control Register
Power Up Con-
dition
Bit
Description
Type
Output(s) Affected
7
6
5
4
3
2
1
0
Revivsion ID bit 3
Revivsion ID bit 2
Revivsion ID bit 1
Revivsion ID bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
1
1
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
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StorageꢀTemperature........................................................ –65°Cꢀtoꢀ+150°C
AmbientꢀOperatingꢀTemperature
....................................... –40°Cꢀtoꢀ+85°Cꢀ
PI6C49003A
PCIe® Gen 2 Networking Clock Generator
1
Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol
Parameters
Min.
Max.
Units
V
V
V
3.3V I/O Supply Voltage
Input High Voltage
Input Low Voltage
Storage Temperature
ESD Protection
-0.5
4.6
4.6
DD
IH
IL
V
-0.5
-65
Ts
150
°C
V
V
2000
ESD
Note:
1.ꢀStressꢀbeyondꢀthoseꢀlistedꢀunderꢀ“AbsoluteꢀMaximumꢀRatings”ꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.
Maximum Ratings
(Aboveꢀwhichꢀusefulꢀlifeꢀmayꢀbeꢀimpaired.ꢀꢀForꢀuserꢀguidelines,ꢀnotꢀtested.)
Note:
MaximumꢀSupplyꢀVoltage,ꢀV ꢀ............................................................ 7V
DD
StressesꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀMAXIMUMꢀRAT-
INGSꢀmayꢀcauseꢀpermanentꢀdamageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀ
aꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀ
atꢀtheseꢀorꢀanyꢀotherꢀconditionsꢀaboveꢀthoseꢀindicatedꢀinꢀ
theꢀoperationalꢀsectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀ
Exposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀex-
tendedꢀperiodsꢀmayꢀaffectꢀreliability.
AllꢀInputsꢀandꢀOutputsꢀ...............................................–0.5VꢀtoꢀV +0.5V
DDꢀ
JunctionꢀTemperatureꢀ........................................................................125°C
PeakꢀSolderingꢀTemperature..............................................................260°C
DC Electrical Characteristics
Unless otherwise specified, V =3.3V±10%, Ambient Temperature –40°C to +85°C
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
V
V
V
V
Operating Supply Voltage
Input High Voltage
3.0
2
3.6
DD
IH
IL
V
DD
Input Low Voltage
–0.3
0.8
V
Input High Voltage
SDATA, SCLK
SDATA, SCLK
0.7V
V
DD
IH
IL
DD
Input Low Voltage
0.3V
DD
I
Operating Supply Current
IDD at Output Disable Condition
320
3.0
DD
mA
PD_RESET = 0
PD_RESET
216
R
C
/R
Internal Pull-Up/Pull-Down Resistor
Input Capacitance
k–Ohm
pF
PU PD
All single-ended outputs
All input pins
75
6
IN
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Electrical Characteristics - Single-Ended
Unless otherwise specified, V =3.3V±10%, Ambient Temperature –40°C to +85°Cꢀ
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Units
F
Input Clock Frequency
SCLK Frequency
25
MHz
kHz
IN
100
400
Minimum Pulse Width of PD_RESET
Input
100
ns
Output Frequency Error
Output Frequency Error
Output Rise/Fall Time
FS0, FS6 = 0
32.256MHz
0
ppm
7
t t
V
=3.3V, 0.8V to 2.4V
DD
0.5
50
1
ns
%
r, f
Output Clock Duty Cycle
High-Level Output Voltage
High-Level Output Voltage
Low-Level Output Voltage
Measured at V /2
45
55
DD
V
OH
I
= -4mA
= -8mA
= 8mA
V
-0.4
OH
DD
V
OH
I
OH
2.4
V
V
OL
I
OL
0.4
50MHz clock output
140
125
200
Peak-to-Peak Jitter
33/66/133MHz clock output
175
ps
32.256MHz clock output
50MHz clock output
115
120
120
150
175
160
10
Cycle-to-Cycle Jitter
33/66/133 MHz clock output
Clock Stabilization Time from Power Up
3
ms
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Electrical Characteristics - 100MHz Differential HCSL Outputs
Unless otherwise specified, V =3.3V±10%, Ambient Temperature –40°C to +85°Cꢀ
DD
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Output Frequency
100
150
MHz
T
Cycle-to-Cycle Jitter
CC/Jitter
ps
Using PCIe jitter measure-
ment method
Peak-to-Peak Phase Jitter
86
PCIe 2.0 Test Method @
100MHz Output
J
PCIe 2.0 RMS Phase Jitter
3.1
0
ps
%
RMS2.0
Spread Modulation Percentage
-0.5
32
Spread Modulation Frequency
kHz
T
Duty Cycle
45
50
55
%
DC
Rising/Falling Edge Rate
Note 3, 4
0.6
4.5
V/ns
V = 50%(measurement
T
T
Z
Output Skew
200
ps
OSKEW
threshold)
Clock Source DC Impedance, single ended
High-Level Output Voltage
50
Ohm
C-DC
Note 2, (R =33-Ohm,
S
V
0.65
0.71
0.95
0.05
OH
R =50-Ohm)
T
V
V
Low-Level Output Voltage
–0.20
0
OL
I
I
@ 6*I
REF
–13
–14.2
-18.5
0.55
mA
V
OH
OH
V
Absolute Crossing Point Voltage
Note 2, 5, 6
Note 2, 5, 8
Note 3, 9, 10
Note 3, 7
0.25
CROSS
Variation of VCROSS over all rising clock
edges
V
140
mV
CROSS Delta
T
T
Average Clock Period Accuracy
–300
9.847
2800
ppm
PERIOD AVG
PERIOD ABS
Absolute Period (including jitter and spread
spectrum)
10.203 ns
Notes:
1.ꢀ Measuredꢀatꢀtheꢀendꢀofꢀanꢀ8-inchꢀtraceꢀwithꢀaꢀ5pFꢀload.
2.ꢀMeasurementꢀtakenꢀfromꢀaꢀsingle-endedꢀwaveform.
3.ꢀ Measurementꢀtakenꢀfromꢀaꢀdifferentialꢀwaveform.
4.ꢀMeasuredꢀfromꢀ-150ꢀmVꢀtoꢀ+150ꢀmVꢀonꢀtheꢀdifferentialꢀwaveform.ꢀTheꢀsignalꢀisꢀmonotonicꢀthroughꢀtheꢀmeasurementꢀregionꢀforꢀriseꢀandꢀfallꢀtime.ꢀꢀ
Theꢀ300ꢀmVꢀmeasurementꢀwindowꢀisꢀcenteredꢀonꢀtheꢀdifferentialꢀzeroꢀcrossing.
5.ꢀ Measuredꢀatꢀcrossingꢀpointꢀwhereꢀtheꢀinstantaneousꢀvoltageꢀvalueꢀofꢀtheꢀrisingꢀedgeꢀofꢀ100M+ꢀequalsꢀtheꢀfallingꢀedgeꢀ100M–.
6.ꢀRefersꢀtoꢀtheꢀtotalꢀvariationꢀfromꢀtheꢀlowestꢀcrossingꢀpointꢀtoꢀtheꢀhighest,ꢀregardlessꢀofꢀwhichꢀedgeꢀisꢀcrossing.ꢀꢀ
Refersꢀtoꢀallꢀcrossingꢀpointsꢀforꢀthisꢀmeasurement.
7.ꢀ Definesꢀasꢀtheꢀabsoluteꢀminimumꢀorꢀmaximumꢀinstantaneousꢀperiod.ꢀThisꢀincludesꢀcycle-to-cycleꢀjitter,ꢀrelativeꢀPPMꢀtolerance,ꢀꢀ
andꢀspreadꢀspectrumꢀmodulation.
8.ꢀDefinedꢀasꢀtheꢀtotalꢀvariationꢀofꢀallꢀcrossingꢀvoltagesꢀofꢀrisingꢀ100M+ꢀandꢀfallingꢀ100M–.
9.ꢀ Referꢀtoꢀsectionꢀ4.3.2.1ꢀofꢀtheꢀPCIꢀExpressꢀBaseꢀSpecification,ꢀRevisionꢀ1.1ꢀforꢀinformationꢀregardingꢀPPMꢀconsiderations.
10.ꢀ PPMꢀrefersꢀtoꢀpartsꢀperꢀmillionꢀandꢀisꢀaꢀDCꢀabsoluteꢀperiodꢀaccuracyꢀspecification.ꢀ1ꢀPPMꢀisꢀ1/1,000,000thꢀofꢀ100ꢀMHzꢀexactlyꢀorꢀ100ꢀHz.ꢀForꢀ300ꢀPPMꢀthereꢀ
isꢀanꢀerrorꢀbudgetꢀofꢀ100Hz/PPMꢀ*ꢀ300ꢀPPMꢀ=ꢀ30ꢀkHz.ꢀTheꢀperiodꢀisꢀmeasuredꢀwithꢀaꢀfrequencyꢀcounterꢀwithꢀmeasurementꢀwindowꢀsetꢀatꢀ100ꢀmsꢀorꢀgreater.ꢀ
Withꢀspreadꢀspectrumꢀturnedꢀoffꢀtheꢀerrorꢀisꢀlessꢀthanꢀ±300ꢀppm.ꢀWithꢀspreadꢀspectrumꢀturnedꢀonꢀthereꢀisꢀanꢀadditionalꢀ+2500ꢀPPMꢀnominalꢀshiftꢀinꢀmaximumꢀ
periodꢀresultingꢀfromꢀtheꢀ-0.5%ꢀdownꢀspread.
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Crystal Load Capacitors
If an input crystal is used, crystal should be connected from pins X1 to ground and X2 to ground to optimize the accuracy of the
output frequency.
C = Crystal's load capacitance in pF
L
Crystal Capacitors (pF) = (C - 8) *2
L
For example, for a crystal with a 18pF load cap, each external crystal cap would be 18pF. (18 - 8) *2 =18.
Application Notes
Crystal circuit connection
e following diagram shows PI6LC4830-01 crystal circuit connection with a parallel crystal. For the CL=18pF crystal, it is suggest-
ed to use C1= 27pF, C2= 33pF. C1 and C2 can be adjusted to fine tune to the target ppm of crystal oscillator according to different
board layouts.
Crystal Oscillator Circuit
XTAL_IN
C1
27pF
SaRonix-eCera
Crystal�(CL�=�18pF)
CG2500003
XTAL_OUT
C2
33pF
Recommended Crystal Specification
Pericom recommends:
a)ꢀꢀꢀGC2500003ꢀXTALꢀ49S/SMD(4.0ꢀmm),ꢀ25M,ꢀCL=18pF,ꢀ+/-30ppm,ꢀhttp://www.pericom.com/pdf/datasheets/se/GC_GF.pdfꢀ
b)ꢀꢀꢀFY2500081,ꢀSMDꢀ5x3.2(4P),ꢀ25M,ꢀCL=18pF,ꢀ+/-30ppm,ꢀhttp://www.pericom.com/pdf/datasheets/se/FY_F9.pdfꢀ
c)ꢀꢀꢀFL2500047,ꢀSMDꢀ3.2x2.5(4P),ꢀ25M,ꢀCL=18pF,ꢀ+/-20ppm,ꢀhttp://www.pericom.com/pdf/datasheets/se/FL.pdfꢀ
Configuration test load board termination for HCSL Outputs
Rs
Clock
33Ω
5%
TLA
PI6C49003A
Rs
Clock#
33Ω
5%
TLB
2pF
5%
2pF
5%
Rp
49.9Ω
1%
Rp
49.9Ω
475Ω
1%
1%
Figure 4. Configuration Test Load Board Termination
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11/11/14
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PI6C49003A
PCIe® Gen 2 Networking Clock Generator
Packaging Mechanical: 48-Contact TSSOP(A)
DOCUMENT CONTROL NO.
PD - 1501
48
REVISION: G
DATE: 03/09/05
.236
.244
6.0
6.2
See Note 4
1
.488 12.4
See Note 3
.496 12.6
.047
1.20 Max
SEATING PLANE
0.09
0.20
.004
.008
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.007
.010
.0197
BSC
.319
BSC
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
0.50
0.17
0.27
8.1
Note:
1. Controlling dimensions in millimeters.
2. Ref: JEDEC MO-153F/ED
3. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protru-
sions and gate burrs shall not exceed 0.15mm per side.
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
4. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion
shall not exceed 0.25mm per side.
DESCRIPTION: 48-Pin 240-Mil Wide TSSOP
PACKAGE CODE: A
Note: For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
(1-3)
Ordering Information
Ordering Code
Package Code
Package Description
PI6C49003AAE
A
48-pin, 240-Mil Wide (TSSOP)
Notes:
1.ꢀThermalꢀcharacteristicsꢀcanꢀbeꢀfoundꢀonꢀtheꢀcompanyꢀwebꢀsiteꢀatꢀwww.pericom.com/packaging/
2.ꢀEꢀ=ꢀPb-freeꢀandꢀGreen
3.ꢀAddingꢀanꢀXꢀsuffixꢀ=ꢀTape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
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