RTQ2503S [RICHTEK]
暂无描述;
| 型号： | RTQ2503S |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | 暂无描述 |
| 文件： | 总20页 (文件大小：743K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
RTQ2503S
3A, 6.5V, Ultra Low Noise, Ultra Low Dropout Linear Regulator
General Description
Features
Input Voltage Range : 1.1V to 6.5V
The RTQ2503S is a high-current (3A), low-noise
(4.4μVRMS), high accuracy (1% over line, load, and
temperature), low-dropout linear regulator (LDO) capable
of sourcing 3A with extremely low dropout (max. 180mV).
The device output voltage is pin-selectable (up to 3.95V)
using a PCB layout without the need of external resistors,
thus reducing overall component count. Designers can
achieve higher output voltage with the use of external
resistor divider. The device supports single input supply
voltage as low to 1.1V that makes it easy to use.
Two Output Voltage Modes
0.8 V to 5.5V (Set by a Resistive Divider)
0.8 V to 3.95V (Set via PCB Layout, No External
Resistor Required)
Accurate Output Voltage Accuracy (1%) Over Line,
Load and Temperature
Ultra High PSRR : 40dB at 500kHz
Excellent Noise Immunity
4.4μVRMS at 0.8V Output
7.7μVRMS at 5.0V Output
Ultra Low Dropout Voltage : 180mV at 3A
Enable Control
The low noise, high PSRR and high output current capability
makes the RTQ2503S ideal to power noise-sensitive
devices such as analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), and RF components.
With very high accuracy, remote sensing, and soft-start
capabilities to reduce inrush current, the RTQ2503S is
ideal for powering digital loads such as FPGAs, DSPs,
andASICs.
Programmable Soft-Start Output
Stable with a 47μF or Larger Ceramic Output
Capacitor
Support Power-Good Indicator Function
RoHS Compliant and Halogen Free
The external enable control and power good indicator
function makes the sequence control easier. The output
noise immunity is enhanced by adding external bypass
capacitor onNR/SS pin. The device is fully specified over
the temperature range of TJ = −40°C to 125°C and is offered
in a WQFN-20L 3.5x3.5 package.
Applications
Portable ElectronicDevice
Wireless Infrastructure : SerDes, FPGA, DSP
RF, IF Components : VCO, ADC, DAC, LVDS
Pin Configuration
(TOP VIEW)
Ordering Information
RTQ2503S
20 19 18 17 16
Package Type
QW: WQFN-20L 3.5x3.5 (W-Type)
1
2
3
4
5
15
14
13
12
11
VOUT
SNS
FB
PGOOD
50mV
VIN
EN
NR/SS
NC
Lead Plating System
G : Green (Halogen Free and Pb Free)
GND
21
10
1.6V
Note :
6
7
8
9
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
WQFN-20L 3.5x3.5
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DSQ2503S-01 June 2019
www.richtek.com
1
RTQ2503S
Marking Information
AA= : Product Code
YMDNN : Date Code
AA=YM
DNN
Functional Pin Description
Pin No.
Pin Name
Pin Function
LDO output pins. A 47F or larger ceramic capacitor (22F or greater of
capacitance) is required for stability. Place the output capacitor as close to
the device as possible and minimize the impedance between VOUT pin to
load.
1, 19, 20
VOUT
Output voltage sense input pin. Connect this pin only if using PCB layout set
the VOUT voltage (No External Resistor Required). Keep SNS pin floating if
the VOUT voltage is set by external resistor.
2
3
SNS
FB
Feedback voltage input. This pin is used to set the desired output voltage
via an external resistive divider. The feedback reference voltage is 0.8V
typically.
Power good indicator output. An open-drain output and active high when the
output voltage reaches 88% of the target. The pin is pulled to ground when
the output voltage is lower than its specified threshold, EN shutdown, OCP
and OTP.
4
PGOOD
Output voltage setting pins. Connect these pins to ground or leave floating.
50mV, 100mV, Connecting these pins to ground increases the output voltage by the value
5, 6, 7, 9, 10, 11 200mV, 400mV, of the pin name; multiple pins can be simultaneously connected to GND to
800mV, 1.6V
select the desired output voltage. Leave these pins floating (open) if the
VOUT voltage is set by external resistor.
8, 18,
21 (Exposed Pad)
Ground. The exposed pad must be soldered to a large PCB and connected
to GND for maximum the power dissipation.
GND
No internal connection. Leave these pins floating doesn’t affect the chip
functionality. By connecting these pins to GND, design engineers could
extend the GND copper coverage on the PCB top layer to enhance the
thermal convection.
12
13
NC
Noise-reduction and soft-start pin. Decouple this pin to GND with an external
capacitor CNR/SS can not only reduce output noise to very low levels but also
slow down the VOUT rise like a soft-start behavior. For low noise
applications, a 10nF to 1F CNR/SS is suggested.
NR/SS
Enable control input. Connecting this pin to logic high enables the regulator
or driving this pin low puts it into shutdown mode. The device can operate
with VIN and VEN sequenced in any order. Mostly, enabling the device after
14
EN
VIN is present can achieve precise timing control.
Supply input. A minimum of 47F ceramic capacitor should be placed as
close as possible to this pin for better noise rejection.
15, 16, 17
VIN
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
2
DSQ2503S-01 June 2019
RTQ2503S
Functional Block Diagram
VOUT
VIN
Charge
Pump
Active
Discharge
Current
Limit
Gate
Driver
Thermal
Protection
PGOOD
0.72V
UVLO
+
-
Enable
Control
Logic
UVLO
-
EN
SNS
FB
Bandgap
Reference
2R
32R 16R
8R
4R
2R
1R
INR/SS
NR/SS GND
50mV 100mV 200mV 400mV 800mV 1.6V
Operation
The RTQ2503S operates with single supply input ranging
from 1.1V to 6.5V and capable to deliver 3Acurrent to the
output. The device features high PSRR and low noise
provides a clean supply to the application.
If not used, connect EN to the largest capacitance on the
input as close as possible to prevent voltage droops on
the VIN line from triggering the enable circuit.
VOUT Programming Pins
A low-noise reference and error amplifier are included to
reduce device noise. TheNR/SS capacitor filters the noise
from the reference and feed-forward capacitor filters the
noise from the error amplifier. The high power-supply
rejection ratio (PSRR) of the RTQ2503S minimize the
coupling of input supply noise to the output.
The RTQ2503S built-in matched feedback resistor network
to set output voltage. The output voltage can be
programmed from 0.8V to 3.95V in 50mV steps when tying
these programming pins (Pins 5 to 11) to ground. Tying
any of the VOUT programming pins to SNS can lower the
value of the upper resistor divider. Hence the VOUT
programming resolution is increased.
Enable and Shutdown
The RTQ2503S provides an EN pin, as an external chip
enable control, to enable or disable the device. VEN below
0.5 V turns the regulator off and enters the shutdown mode,
while VEN above 1.1V turns the regulator on. When the
regulator is shutdown, the ground current is reduced to a
maximum of 25μA. The enable circuitry has hysteresis
(typically 50mV) for use with relatively slowly ramping
analog signals.
Programmable Soft-Start
The noise-reduction capacitor (CNR/SS) accomplishes dual
purpose of both noise-reduction and programming the soft-
start ramp time during turn-on. When EN and UVLO
exceeds the respective threshold voltage, the RTQ2503S
active a quick-start circuit to charge the noise reduction
capacitor (CNR/SS) and then the output voltage ramps up.
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DSQ2503S-01 June 2019
www.richtek.com
3
RTQ2503S
Power Good
Over-Temperature Protection (OTP)
The power-good circuit monitors the feedback pin voltage
to indicate the status of the output voltage. The open-
drain PGOOD pin requires an external pull-up resistor to
an external supply, any downstream device can receive
power-good as a logic signal that can be used for
sequencing. Pull-up resistor from 10kΩ to 100kΩ is
recommended. Make sure that the external pull-up supply
voltage results in a valid logic signal for the receiving device
or devices.
The RTQ2503S implements thermal shutdown protection.
The device is disable when the junction temperature (TJ)
exceeds 160°C (typical). The LDO automatically turn-on
again when the temperature falls to 140°C (typical).
For reliable operation, limit the junction temperature to a
maximum of 125°C. Continuously running the RTQ2503S
into thermal shutdown or above a junction temperature of
125°C reduces long-term reliability.
Output Active Discharge
After start-up, the PGOODpin becomes high impedance
when the feedback voltage exceeds VPGOOD_HYS (Typically
90% of 0.8V reference voltage level). The PGOOD is pulled
to GND when the feedback pin voltage falls below the
VIT_PGOOD, EN low, Current limit, and OTP.
When the device is disabled, the RTQ2503S discharges
the LDO output (via VOUT pins) through an internal several
hundred ohms to ground. Do not rely on the active
discharge circuit for discharging a large amount of output
capacitance after the input supply has collapsed because
reverse current can possibly flow from the output to the
input. External current protection should be added if the
device may work at reverse voltage state.
Under-Voltage Lockout (UVLO)
The UVLO circuit monitors the input voltage to prevent
the device from turning on before VIN rises above the VUVLO
threshold. The UVLO circuit also disables the output of
the device when VIN fall below the lockout voltage
(VUVLO − ΔVUVLO). The UVLO circuit responds quickly to
glitches on VIN and attempts to disable the output of the
device if VINcollapse.
Internal Current Limit (ILIM
)
The RTQ2503S continuously monitors the output current
to protect the pass transistor against abnormal operations.
When an overload or short circuit is encountered, the
current limit circuitry controls the pass transistor's gate
voltage to limit the output within the predefined range.
Thermal shutdown can activate during a current limit event
because of the high power dissipation typically found in
these conditions. To ensure proper operation of the current
limit, minimize the inductances to the input and load.
Continuous operation in current limit is not recommended.
By reason of the build-in body diode, the pass transistor
conducts current when the output voltage exceeds input
voltage. Since the current is not limited, external current
protection should be added if the device may work at
reverse voltage state.
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DSQ2503S-01 June 2019
RTQ2503S
Absolute Maximum Ratings (Note 1)
VIN, PGOOD, EN -------------------------------------------------------------------------------------------------- −0.3V to 7V
VOUT ------------------------------------------------------------------------------------------------------------------ −0.3V to (VIN + 0.3V)
NR/SS, FB ----------------------------------------------------------------------------------------------------------- −0.3V to 3.6V
Power Dissipation, PD @ TA = 25°C
WQFN-20L 3.5x3.5 ------------------------------------------------------------------------------------------------ 3.5W
Package Thermal Resistance (Note 2)
WQFN-20L 3.5x3.5, θJA ------------------------------------------------------------------------------------------- 28.5°C/W
WQFN-20L 3.5x3.5, θJC ------------------------------------------------------------------------------------------ 7.2°C/W
Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------ 260°C
Junction Temperature ---------------------------------------------------------------------------------------------- 150°C
Storage Temperature Range ------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model)--------------------------------------------------------------------------------------- 2kV
CDM (ChargedDevice Model) ----------------------------------------------------------------------------------- 1kV
Recommended Operating Conditions (Note 4)
Supply Input Voltage, VIN ---------------------------------------------------------------------------------------- 1.1V to 6.5V
Junction Temperature Range------------------------------------------------------------------------------------- −40°C to 125°C
Electrical Characteristics
Over operating temperature range (TJ = −40°C to 125°C), (1.1V ≤ VIN < 6.5V and VIN ≥ VOUT(TARGET) + 0.3 V, VOUT(TARGET) = 0.8V,
VOUT connected to 50Ω to GND, VEN = 1.1 V, CIN = 10μF, COUT = 47μF, CNR/SS = 0nF, CFF = 0nF, and PGOOD pin pulled up to
VIN with 100 kΩ, unless otherwise noted. (Note 5)
Parameter
Symbol
VIN
Test Conditions
Min
Typ
Max Unit
Operating Input
Voltage Range
1.1
--
6.5
V
V
Feedback Reference
Voltage
VREF
--
0.8
0.8
--
NR/SS Pin Voltage
VNR/SS
VUVLO
--
--
--
---
V
V
VIN increasing
Hysteresis
1.02 1.085
Under-Voltage
Lock-Out
VUVLO
150
--
mV
Using voltage setting pins (50mV, 100mV, 0.8V
3.95V
+ 1%
--
V
V
200mV, 400mV, 800mV, and 1.6V)
1%
Output Voltage Range
Output Voltage
0.8V
1%
5V +
1%
Using external resistors
--
--
V
IN = VOUT + 0.3V, 0.8V VOUT 5V,
VOUT
1
1
%
Accuracy
(Note 6)
5mA IOUT 3A
Line Regulation
Load Regulation
VOUT/VIN IOUT = 5mA, 1.4V VIN 6.5 V
VOUT/IOUT 5mA IOUT 3A
--
--
0.05
0.08
--
--
%/V
%/A
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DSQ2503S-01 June 2019
www.richtek.com
5
RTQ2503S
Parameter
Symbol
VDROP
Test Conditions
Min
Typ
Max
Unit
VIN = 1.1V to 6.5V, IOUT = 3A,
FB = 0.8V 3%
Dropout Voltage
--
110
180
mV
V
VOUT = 90% VOUT(TARGET),
VIN = VOUT(TARGET) + 400mV
Output Current Limit
ILIM
3.7
--
4.2
2.8
4.2
--
4.7
4
A
Minimum load, VIN = 6.5V,
I
OUT = 5mA
Maximum load, VIN = 1.4V,
OUT = 3A
Shutdown, PGOOD = Open,
IN = 6.5V, VEN = 0.5V
mA
Ground Pin Current
EN Pin Current
IGND
--
5.5
I
--
25
0.1
6.5
A
A
V
--
--
IEN
VIN = 6.5V, VEN = 0V and 6.5V
0.1
1.1
EN Pin High-Level
Input Voltage
VEN_H
Enable device
V
EN Pin Low-Level
Input Voltage
--
VEN_L
Disable device
0
0.5
PGOOD Pin
Threshold
For the direction PGOOD signal
falling with decreasing VOUT
0.82 x 0.883 x 0.93 x
VIT_PGOOD
V
V
VOUT
VOUT
VOUT
PGOOD Pin
Hysteresis
0.01 x
VOUT
VPGOOD_HYS For PGOOD signal rising
--
--
PGOOD Pin Low-
Level Output Voltage
VOUT < VIT_PGOOD
IPGOOD = 1mA (current into device)
,
VPGOOD_L
--
--
0.4
V
PGOOD Pin Leakage
Current
VOUT > VIT_PGOOD
PGOOD = 6.5V
,
IPGOOD_LK
INR/SS
IFB
--
4
--
6.2
--
1
9
A
A
nA
V
NR/SS Pin Charging
Current
VNR/SS = GND, VIN = 6.5V
VIN = 6.5V
FB Pin Leakage
Current
100
--
100
--
f = 10kHz,
OUT = 0.8V
42
39
40
25
V
VIN VOUT = 0.4V,
OUT = 3A,
f = 500kHz,
OUT = 0.8V
I
--
--
V
Power Supply
Rejection Ratio
C
C
C
NR/SS = 100nF,
FF = 10nF,
OUT = 47F || 10F
PSRR
dB
f = 10kHz,
OUT = 5V
--
--
V
|| 10F
f = 500kHz,
--
--
VOUT = 5V
BW = 10Hz to 100kHz,
V
IN = 1.1V,
--
4.4
7.7
--
I
OUT = 3A,
VOUT = 0.8V
C
C
C
NR/SS = 100nF,
FF = 10nF,
OUT = 47μF || 10μF
Output Noise Voltage eNO
VRMS
VOUT = 5 V
|| 10μF
Temperature increasing
Temperature decreasing
--
--
160
140
--
--
Thermal Shutdown
TSD
°C
Threshold
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
6
DSQ2503S-01 June 2019
RTQ2503S
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the
exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. VOUT(TARGET) is the expected VOUT value set by the external feedback resistors. The 50Ω load is disconnected when the
test conditions specify an IOUT value.
Note 6. External resistor tolerance is not taken into account.
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DSQ2503S-01 June 2019
www.richtek.com
7
RTQ2503S
Typical Application Circuit
RTQ2503S
15, 16, 17
1, 19, 20
3
V
OUT
V
VIN
IN
VOUT
C
47µF
1.2V/3A
IN
C
47µF
C
10nF
OUT
FF
R1
5.9k
Power Good
FB
R3 100k
4
V
R2
11.8k
OUT
PGOOD
14
13
Enable
EN
NR/SS
C
10nF
NR/SS
GND
8, 18, 21 (Exposed Pad)
R1
R2
5.9k
11.8k
VOUT = VREF 1 +
= 0.8V 1 +
= 1.2V
Figure 1. Configuration Circuit for VOUT Adjusted by a ResistiveDivider
Table 1. Recommended Feedback-Resistor Values
External Restive Divider Combinations
Output Voltage (V)
R1 (k)
12.4
12.4
12.4
12.4
12.4
12.4
11.8
11.8
12.4
R2 (k)
100
0.9
1
49.9
24.9
14.3
10
1.2
1.5
1.8
2.5
3.3
4.5
5
5.9
3.74
2.55
2.37
RTQ2503S
15, 16, 17
1, 19, 20
V
OUT
V
VIN
IN
VOUT
C
47µF
1.25V/3A
IN
2
3
C
47µF
C
10nF
OUT
FF
SNS
FB
Power Good
R3 100k
11
10
9
4
V
1.6V
800mV
400mV
OUT
PGOOD
14
13
Enable
EN
7
NR/SS
200mV
100mV
C
10nF
NR/SS
6
5
50mV
GND
8, 18, 21 (Exposed Pad)
VOUT = VREF + 50mV + 400mV = 0.8V + 50mV + 400mV = 1.25V
(Table 2. provides a full list for different VOUT target and the corresponding pin settings.)
Figure 2. Configuration Circuit for VOUT Adjusted via PCB Layout
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
8
DSQ2503S-01 June 2019
RTQ2503S
Table 2. VOUT Select Pin Settings for Different Target
VOUT (V) 50mV 100mV 200mV 400mV 800mV 1.6V VOUT (V) 50mV 100mV 200mV 400mV 800mV 1.6V
0.8
0.85
0.9
Open Open Open
GND Open Open
Open GND Open
GND GND Open
Open Open
Open Open
Open Open
Open Open
Open Open
Open Open
Open Open
Open Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
2.4
2.45
2.5
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open
Open
Open
Open
GND
GND
GND
GND
Open Open
Open Open
Open Open
Open Open
Open Open
Open Open
Open Open
Open Open
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
0.95
1
2.55
2.6
Open Open
GND Open
Open GND
GND GND
GND
GND
GND
GND
1.05
1.1
2.65
2.7
1.15
1.2
2.75
2.8
Open Open Open
GND Open Open
Open GND Open
GND GND Open
GND
GND
GND
GND
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
Open
Open
Open
Open
Open
Open
Open
Open
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1.25
1.3
2.85
2.9
1.35
1.4
2.95
3
Open Open
GND Open
Open GND
GND GND
GND
GND
GND
GND
1.45
1.5
3.05
3.1
1.55
1.6
3.15
3.2
Open Open Open
GND Open Open
Open GND Open
GND GND Open
1.65
1.7
3.25
3.3
1.75
1.8
3.35
3.4
Open Open
GND Open
Open GND
GND GND
GND
GND
GND
GND
1.85
1.9
3.45
3.5
1.95
2
3.55
3.6
Open Open Open
GND Open Open
Open GND Open
GND GND Open
2.05
2.1
3.65
3.7
2.15
2.2
3.75
3.8
Open Open
GND Open
Open GND
GND GND
GND
GND
GND
GND
2.25
2.3
3.85
3.9
2.35
3.95
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DSQ2503S-01 June 2019
www.richtek.com
9
RTQ2503S
Typical Operating Characteristics
PSRR vs. Frequency and VIN
PSRR vs. Frequency and IOUT
100
80
60
40
20
0
100
VOUT = 0.8V, IOUT = 3A, COUT = 47μF//10μF//10μF,
VIN = 1.1V, VOUT = 0.8V, COUT = 47μF//10μF//10μF,
CNR/SS = 10nF, CFF = 10nF
CNR/SS = 10nF, CFF = 10nF
80
60
IOUT = 0.1A
VIN = 1.1V
VIN = 1.15V
VIN = 1.2V
VIN = 1.25V
VIN = 1.3V
VIN = 1.35V
VIN = 1.4V
IOUT = 0.5A
IOUT = 1A
IOUT = 2A
40
20
0
IOUT = 2.5A
IOUT = 3A
10
100
1K
10K
100K
1M
10M
10
100
1K
10K
100K
1M
10M
Frequency (Hz)
Frequency (Hz)
PSRR vs. Frequency and VOUT
PPSRR vs. Frequency and VIN
100
80
60
40
20
0
100
80
60
40
20
0
VIN = VOUT + 0.3V, IOUT = 3A,
COUT = 47μF//10μF//10μF,
CNR/SS = 10nF, CFF = 10nF
VOUT = VIN - 0.4V, IOUT = 1A
COUT = 47μF//10μF//10μF,
CNR/SS = 10nF, CFF =10nF
VIN = 1.1V
VIN = 1.2V
VIN = 1.4V
VIN = 2.5V
VIN = 5V
VOUT = 0.8V
VOUT = 0.9V
VOUT = 1.1V
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.8V
VOUT = 2.5V
10
100
1K
10K
100K
1M
10M
10
100
1K
10K
100K
1M
10M
Frequency (Hz)
Frequency (Hz)
PSRR vs. Frequency and VIN for VOUT = 3.3 V
PSRR vs. Frequency and COUT
100
100
80
60
40
20
0
IOUT = 3A, COUT = 47μF//10μF//10μF,
VIN = VOUT + 0.3V, VOUT = 1V, IOUT = 3A,
CNR/SS = 10nF, CFF =10nF
CNR/SS = 10nF, CFF = 10nF
80
60
VIN = 3.6V
VIN = 3.65V
VIN = 3.7V
40
COUT = 47//10//10μF
COUT = 47μF
COUT = 100μF
VIN = 3.75V
VIN = 3.8V
VIN = 3.85V
20
COUT = 200μF
VIN = 3.9V
COUT = 500μF
0
10
100
1K
10K
100K
1M
10M
10
100
1K
10K
100K
1M
10M
Frequency (Hz)
Frequency (Hz)
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
10
DSQ2503S-01 June 2019
RTQ2503S
Output Noise vs. Frequency and Output Voltage
Output Noise vs. Frequency and Input Voltage
10.000
10.000
IOUT = 3A, VOUT = VIN − 0.4V,
COUT = 47μF//10μF//10μF,
CNR/SS = 10nF, CFF = 10nF
VIN = VOUT + 0.3V, IOUT = 3A,
COUT = 47μF//10μF//10μF,
CNR/SS = 10nF, CFF = 10nF
1.000
0.100
0.010
0.001
1.000
0.100
0.010
0.001
VOUT = 5V
VOUT = 1.5V
VOUT = 0.8V
VIN = 1.4V
VIN = 1.5V
VIN = 1.8V
10
100
1K
10K
100K
1M
10
100
1K
10K
100K
1M
Frequency (Hz)
Frequency (Hz)
Output Noise vs. Frequency and CNR/SS
Output Noise vs. Frequency and CFF
10.000
1.000
0.100
0.010
0.001
10.000
1.000
0.100
0.010
0.001
VIN = 1.1V, VOUT = 0.8V, IOUT = 3A,
COUT = 47μF//10μF//10μF, CNR/SS = 10nF
VIN =1.1V, VOUT = 0.8V, IOUT = 3A,
COUT = 47μF//10μF//10μF, CFF = 10nF
CFF = 0nF
CNR/SS = 0nF
C
C
FF = 0.1nF
FF = 1nF
CNR/SS = 1nF
CNR/SS = 10nF
CFF = 10nF
FF = 100nF
CNR/SS = 100nF
C
10
100
1K
10K
100K
1M
10
100
1K
10K
100K
1M
Frequency (Hz)
Frequency (Hz)
Power Up Response
Output Noise at 5V Output
10.000
1.000
0.100
0.010
0.001
VIN = 5.4V, VOUT = 5V, IOUT = 3A,
COUT = 47μF//10μF//10μF, CFF = 10nF
VEN
VEN
(2V/Div)
CNR/SS = 10nF
CNR/SS = 100nF
CNR/SS = CFF = 100nF
VOUT, CNR/SS = 1nF
VOUT, CNR/SS = 10nF
VOUT, CNR/SS = 47nF
VOUT, CNR/SS = 100nF
VOUT
(0.5V/Div)
VIN = VOUT + 0.3V, VOUT = 1.8V,
IOUT = 3A, COUT = 47μF, CFF = 10nF
10
100
1K
10K
100K
1M
Time (4ms/Div)
Frequency (Hz)
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DSQ2503S-01 June 2019
www.richtek.com
11
RTQ2503S
Load Transient Response vs. Load Slew Rate
Load Transient Response
VIN = VOUT + 0.3V, VOUT = 1.8V,
CNR/SS = CFF = 10nF, COUT = 47μF,
IOUT = 1A to 3A (slew rate = 1A/μs)
VOUT, Load S. R. = 0.5A/μs
VOUT, Load S. R. = 1A/μs
VOUT, Load S. R. = 2A/μs
VOUT
(20mV/Div)
offset 1.8V
VOUT
(20mV/Div)
offset 1.8V
VOUT
(20mV/Div)
offset 1.8V
VOUT
(20mV/Div)
offset 1.8V
IOUT
(1A/Div)
VIN = VOUT + 0.3V, VOUT = 1.8V,
CNR/SS = CFF =10nF,
COUT = 47μF, IOUT = 1A to 3A
Time (40μs/Div)
Time (100μs/Div)
Enable Voltage vs. Temperature
Input UVLO vs. Temperature
1.50
1.25
1.00
0.75
0.50
0.25
0.00
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VOUT = 0.8V, IOUT = 10mA
VIN = 1.8V, VOUT = 0.8V, IOUT = 10mA
Logic-High
Logic-Low
Logic-High
Logic-Low
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Dropout Voltage vs. Input Voltage
Dropout Voltage vs. Output Current
160
140
120
100
80
120
100
80
60
40
20
0
IOUT = 3A
VIN = 1.1V
125°C
85°C
25°C
−40°C
125°C
85°C
25°C
60
−40°C
40
1
2
3
4
5
6
0
500
1000
1500
2000
2500
3000
Output Current (mA)
Input Voltage (V)
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
12
DSQ2503S-01 June 2019
RTQ2503S
Dropout Voltage vs. Output Current
120
100
80
60
40
20
0
VIN = 5.4V
125°C
85°C
25°C
−40°C
0
500
1000
1500
2000
2500
3000
Output Current (mA)
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DSQ2503S-01 June 2019
www.richtek.com
13
RTQ2503S
Application Information
The RTQ2503S is a high current, low-noise, high accuracy,
low-dropout linear regulator which capable of sourcing 3A
with only maximum 180mV dropout. The input voltage
operating range from 1.1V to 6.5V and adjustable output
voltage from 0.8V to (VIN − VDROP ) via external resistor
setting or 0.8V to 3.95V via PCB Layout to short specific
pins and get required output target.
RTQ2503S
V
OUT
OUT
VIN
V
IN
VOUT
C
C
SNS
IN
C
EN
FF
FB
1.6V
800mV
400mV
200mV
100mV
Output Voltage Setting
50mV
The output voltage of the RTQ2503S can be set by external
resistors or by output voltage setting pins (50mV, 100mV,
200mV, 400mV, 800mV and 1.6V) to achieve different
output target.
GND
EX :
V
= 0.8V + ( Output setting pins to Ground)
= 0.8V + (0.8V + 0.2V + 0.05V) = 1.85V
OUT
Figure 4. Output Setting without External Resistors
Using external resistors, the output voltage is determined
by the values of R1 and R2 as Figure 3. The values of R1
and R2 can be calculated with any voltage value via use
the formula given in Equation :
Table 2. summarizes these voltage values associated with
each active pin setting for reference. By leaving all program
pins open, or floating, the output is thereby programmed
to the minimum possible output voltage equal to VREF
(0.8V). The maximum output target can be supported up
to 3.95V after all pins 5, 6, 7, 9, 10 are shorted with ground
at the same time.
R1 + R2
VOUT = 0.8
R2
RTQ2503S
V
V
IN
OUT
VIN
VOUT
SNS
C
OUT
C
IN
R1
R2
EN
C
FF
Dropout Voltage
FB
The dropout voltage refers to the voltage difference between
the VINand VOUT pins while operating at specific output
current. The dropout voltage VDROP also can be expressed
as the voltage drop on the pass-FET at specific output
current (IRATED) while the pass-FET is fully operating at
ohmic region and the pass-FET can be characterized as
an resistance RDS(ON). Thus the dropout voltage can be
defined as (VDROP = VIN − VOUT = RDS(ON) x IRATED). For
normal operation, the suggested LDO operating range is
(VIN > VOUT + VDROP) for good transient response and
PSRR ability. Vice versa, while operating at the ohmic
region will degrade the performance severely.
GND
Figure 3. Output Voltage Set by External Resistors
The RTQ2503S also can short the pins 5, 6, 7, 9, 10, and
11 to ground and program the regulated output voltage
level without external resistors after SNS pin is connected
with VOUT pin .The pins 5, 6, 7, 9, 10, and 11 is connected
with internal resistor pairs, each pin is either connected
to ground (active) or left open (floating).
The voltage programming is set as the sum of the internal
reference voltage (VREF = 0.8V) plus the accumulated sum
of the respective voltages assigned to each active pin as
illustrated in figure 4.
CIN and COUT Selection
The RTQ2503S is designed to support the low equivalent
series resistance (ESR) ceramic capacitors for application.
The X7R, X5R, and COG-rated ceramic capacitors is
recommended due to its good capacitive stability across
temperature, whereas the use of Y5V-rated capacitors is
discouraged because of large variations in capacitance.
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
14
DSQ2503S-01 June 2019
RTQ2503S
However, ceramic capacitance varies with operating voltage
and temperature and the design engineer must be aware
of these characteristics. Ceramic capacitors are usually
recommended to be derated by 50%. A 47μF or greater
ceramic capacitor (or 22μF effective capacitance) for output
is suggested to ensure the stability. Input capacitance is
selected to minimize transient input droop during load
current steps. For general applications, an input capacitor
of at least 47μF is highly recommended for minimal input
impedance. If the trace inductance between the RTQ2503S
input supply is high, a fast load transient any cause VIN
voltage level ringing and above the absolute maximum
voltage rating that also damage the device. Adding more
input capacitors is available to restrict the ringing and to
keep it not above the device absolute maximum ratings.
capacitance (CNR/SS), and the internal reference 0.8V
(VREF).
V
C
REF
NR/SS
t
=
a1
SS
I
NR/SS
For noise-reduction consideration, the CNR/SS also
conjunction with an internal noise-reduction resistor that
forms a low-pass filter (LPF) and filters out the noise from
the internal bandgap reference before it being gained up
via the error amplifier, thus reducing the total device noise
floor.
Input Inrush Current
During start-up process, the input Inrush current into VIN
pin is consists of the sum of load current and the charging
current of the output capacitor. The inrush current is difficult
to measure that the input capacitor must be removed and
which is not recommended.Generally, the soft-start inrush
current can be estimated by Equation b1, which VOUT(t)
is the instantaneous output voltage of the power-up ramp,
dVOUT(t) / dt is the slope of the VOUT ramp and RLOAD is
the resistive load impedance.
Generally, a 47μF 0805-sized ceramic capacitor in parallel
with two 10μF 0805-sized ceramic capacitor ensures that
met the minimum effective capacitance at high input
voltage and high output voltage configurations' requirement.
Place these capacitors as close to the pins as possible
for optimum performance and to help ensure stability.
COUT dVOUT
t
VOUT
t
+
IOUT t =
b1
Feed-Forward Capacitor (CFF)
dt
RLOAD
The RTQ2503S is designed to be stable without the
external feed-forward capacitor (CFF). However, a 10nF
external feed-forward capacitor optimizes the transient,
noise, and PSRR performance. Ahigher capacitance CFF
can be also used, but the start-up time is longer and the
power-good signal can incorrectly indicate that the output
voltage is settled.
Under-Voltage Lockout (UVLO)
The under-voltage lockout (UVLO) threshold is the
minimum input operational voltage range that ensure the
device stays disabled. Figure 5 explain the UVLO circuits
being triggered between three different input voltage
events(duration a, b and c), assuming VEN ≥ VEN_H for all
time duration. For duration “a”, input power starts rising
and VIN over the UVLO rising threshold, the VOUT starts
power on then reached the target level and under regulated.
Duration “b” is assume VIN occurs instant power line
unstable and have droop severely, the VIN droop level not
lower than UVLO falling threshold, the device maintain
normal work status, VOUT still under regulated. The
duration “c” is happens VIN droop level lower than UVLO
falling threshold, the control loop of device is disabled
and don't have the regulation ability either, the VOUT droop
in the mean time. For general application, instant power
line transient with long power trace between VINpin may
have VIN level unstable force the device trap into duration
c and makes output voltage collapse. In this case, adding
Soft-Start and Noise Reduction (CNR/SS
)
The RTQ2503S is designed for a programmable, monotonic
soft-start time of output rising, it can be achieved via an
external capacitor (CNR/SS) onNR/SS pin. Using an external
CNR/SS is recommended for general application, not only
for the in-rush current minimization but also helps reduce
the noise component from internal reference.
During the monotonic start-up procedure, the error amplifier
of the RTQ2503S tracks the voltage ramp of the external
soft-start capacitor(CNR/SS) until the voltage approaches
the internal reference 0.8V. The soft-start ramp time can
be calculated with Equation a1 and which is depends on
the soft-start charging current (INR/SS), the soft-start
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DSQ2503S-01 June 2019
www.richtek.com
15
RTQ2503S
more input capacitance or improving input trace layout on PCB are effectively to make sure input power stabilization.
c
a
b
UVLO Rising Threshold
UVLO Hystersis Falling
V
IN
V
OUT
Figure 5. Under-Voltage Lockout Trigging Conditions and Output Variation
Power-Good (PGOOD) Function
the VIN, ENand protection status. Duration “a” is present
the device is under the operation while VEN is higher than
VEN_H threshold, the output voltage VOUT start rising(the
The Power-Good function is monitors the voltage level at
the feedback pin to indicate the output voltage status is
works normal or not, this function enables others devices
receive the RTQ2503S's Power-Good signal as a logic
signal that can be used for the sequence design of the
system application. The PGOOD pin is an open-drain
structure and an external pull-up resistor connecting to
an external supply is necessary. The pulled-up resistor
value between 10kΩ to 100kΩ is recommended for proper
operation. The lower limit of 10kΩ results from the
maximum pulled-down strength of the power-good
transistor, and the upper limit of 100kΩ results from the
maximum leakage current at the power-good node.
rising time has related with soft-start capacitor CNR/SS)
,
after VOUT over PGOOD hysteresis threshold, the reflected
feedback voltage VFB exceeds VPGOOD_HYS threshold, the
PGOODpin is high impedance. The duration “b” indicates
some unpredictable operation happens (ex: OTP, OCP or
output voltage droop severely caused by very fast load
variation). Where the VFB lower than VIT_PGOOD threshold
and the VPGOOD is pulled to GND for the indication that
output voltage status is not ready. While duration “c” is
assume VOUT have small droop that not lower than
PGOOD falling threshold, the PGOOD pin remain high
impedance. After VEN goes logic low level, VPGOOD pulled
to GND as duration “d” presented.
Figure 6 demonstrates some PGOOD scenarios versus
V
EN
a
c
d
b
PGOOD Hysteresis Rising
PGOOD Falling Threshold
V
OUT
V
PGOOD
Figure 6. PGOODTrigger Scenario withDifferent Operating Status
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
16
DSQ2503S-01 June 2019
RTQ2503S
Reverse Current Protection
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction-to-ambient
thermal resistance.
If the maximum VOUT exceeds VIN + 0.3V, that may induce
reverse current from VOUT to VIN that flows through the
body diode of pass element instead of the normal
conducting channel. In this case, the pass element may
be damaged. For example, the output is biased above
input supply voltage level or input supply has instant
collapse at light load operation that makes VIN < VOUT. As
shown in Figure 7, an external Schottky diode could be
added to prevent the pass element be damaged from the
reverse current.
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA, is highly package dependent. For a
WQFN-20L 3.5x3.5 package, the thermal resistance, θJA,
is 28.5°C/W on a standard JEDEC 51-7 high effective-
thermal-conductivity four-layer test board. The maximum
power dissipation at TA = 25°C can be calculated as below :
PD(MAX) = (125°C − 25°C) / (28.5°C/W) = 3.5W for a
WQFN-20L 3.5x3.5 package.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
resistance, θJA. The derating curves in Figure 9 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
VIN
RTQ2503S
GND
VOUT
C
OUT
C
IN
Figure 7. Application Circuit for Reverse Current
Protection
V
OUT
Short to GND
Thermal Considerations
Thermal protection limits power dissipation in the
RTQ2503S.When power dissipation on pass element
(PDIS = (VIN − VOUT) x IOUT ) is too much that raise the
operation junction temperature exceeds 160°C, the OTP
circuit starts the thermal shutdown function and turns the
pass element off. The pass element turns on again after
the junction temperature cools down by 20°C. The
RTQ2503S output voltage will be closed to zero when
output short circuit occurs as shown in Figure 8. It can
reduce the chip temperature and provides maximum safety
to end users when output short circuit occurs.
V
OUT
ILIM’
I
OUT
IC Temperature
Figure 8. Short-Circuit Protection when Output Short-
Circuit Occurs
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DSQ2503S-01 June 2019
www.richtek.com
17
RTQ2503S
Layout Consideration
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
For best performance of the RTQ2503S, the PCB layout
suggestions below are highly recommend. All circuit
components placed on the same side and as near to the
respective LDO pin as possible, place the ground return
path connection to the input and output capacitor, the
ground plane connected by a wide copper surface for good
thermal dissipation. Using vias and long power traces for
the input and output capacitors connection is discouraged
and have negatively affects on performance. Figure 10
shows an example for the layout reference that reduce
conduction trace loop, helping inductive parasitic minimize,
load transient reduction and good circuit stability.
Four-Layer PCB
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 9. Derating Curve of Maximum PowerDissipation
Ground Power Plane for Thermal dissipation / Signal Ground
PGOOD reference
supply
10
21
9
8
7
6
To Signal
Ground
11
12
5
4
1.6V
NC
NR/SS
EN
50mV
PGOOD
FB
SNS
VOUT
PG Output
GND
R2
R1
To Signal Ground
13
14
15
3
2
1
Remote Sense
To Load
VIN
16 17 18 19 20
Output Power Plane
Input Power Plane
Place capacitors as close as
possible to the connecting pins for
minimize power loop area and low
impedance connection to GND
plate.
Thermal vias can help to reduce power trace and
improve thermal dissipation.
Ground Power Plane
Figure 10. PCB Layout Guide
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
18
DSQ2503S-01 June 2019
RTQ2503S
Outline Dimension
1
2
1
2
DETAILA
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
0.700
0.000
0.175
0.200
3.400
2.000
3.400
2.000
Max
0.800
0.050
0.250
0.300
3.600
2.100
3.600
2.100
Min
0.028
0.000
0.007
0.008
0.134
0.079
0.134
0.079
Max
0.031
0.002
0.010
0.012
0.142
0.083
0.142
0.083
A
A1
A3
b
D
D2
E
E2
e
0.500
0.020
L
0.350
0.450
0.014
0.018
W-Type 20L QFN 3.5x3.5 Package
Copyright 2019 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DSQ2503S-01 June 2019
www.richtek.com
19
RTQ2503S
Footprint Information
Footprint Dimension (mm)
Bx By
0.50 4.30 4.30 2.60 2.60 0.85 0.35 2.15 2.15
Number of
Package
Tolerance
±0.05
Pin
P
Ax
Ay
C
D
Sx
Sy
V/W/U/XQFN3.5*3.5-20
20
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify
that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek
product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;
nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent
or patent rights of Richtek or its subsidiaries.
www.richtek.com
20
DSQ2503S-01 June 2019
相关型号：
©2020 ICPDF网 联系我们和版权申明