FAGD1636048BA [ROCHESTER]
ATM/SONET/SDH SUPPORT CIRCUIT, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, HEAT SINK, PLASTIC, TQFP-48;
| 型号： | FAGD1636048BA |
| 厂家： | 
Rochester Electronics |
| 描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, HEAT SINK, PLASTIC, TQFP-48 ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总10页 (文件大小：861K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
140/155 Mbit/s
CMI Shaper and
Equaliser for
E4/STM-1/OC-3
GD16360
an Intel company
Preliminary
General Description
Features
l
The GD16360 is a dual transceiver for
transmitting and receiving CMI–signals,
according to the ITU-T G.703 standard.
Basically the chip is used as an interface
between the internal system signals and
the outside world.
This signal is fed into an equalizer circuit,
which compensates for the frequency de-
pendant attenuation and reshapes the
signal levels into digital, differential
LVPECL levels.
Fully dual transmit/receive IC for
E4/STM-1/OC-3 operations.
l
Meet G.703 for 140 and 155 Mbit/s
CMI interface:
–
–
–
Return loss
Receive sensitivity
Transmit power
The transmit path receives a distorted
signal usually improperly terminated and
with high reflections. This signal is origi-
nally a differential LVPECL signal from
the system ASIC.
The internal system signals are CMI
coded, though distorted and attenuated.
The outside world signals should fully
meet ITU-T G.703.
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Meet G.775 for LOS detection.
3.3 V LVPECL High speed I/O’s.
CMOS configuration signals.
On the receive side the GD16360 re-
ceives an attenuated signal after passing
through a 75 W coax cable with a 12.7 dB
attenuation at 78 MHz.
Power consumption: 500 mW
<target>.
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Supply voltage: 3.3 V
(5 V for external cabledriver
connection.)
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Package: 48 pin TQFP
(7×7×1.4 mm).
Designed for low cost and volume
production.
Applications
l
STM-1 or E4 CMI electrical line inter-
faces
Data Sheet Rev.: 6
Block Diagram
TXIN1P
TXIN1N
TXOM1P
TXOM1N
Shaper
TD
MCIP1
TXO1P
TXO1N
LOS
BITA
TD
Line
G.703
CIP1
LOS
BITC
LOS
BITB
RXO1P
RXO1N
RXIN1P
RXIN1N
PECL
Equaliser
RXOEN1
LOOP1
LOS1
LOS
G.775
BIT1P
BIT1N
Logic
TXIN2P
TXIN2N
TXOM2P
TXOM2N
Shaper
TD
MCIP2
TXO2P
TXO2N
LOS
BITA
TD
Line
G.703
CIP2
LOS
BITC
LOS
BITB
RXO2P
RXO2N
RXIN2P
RXIN2N
PECL
Equaliser
RXOEN2
LOOP2
LOS2
LOS
G.775
BIT2P
BIT2N
Logic
Data Sheet Rev.: 6
GD16360
Page 2 of 9
Functional Details
Functionally the GD16360 consists of
two identical blocks, each containing:
For the remaining three I/O signals
(BITA/B/C), the criteria for signal detec-
tion is set by the presence of transitions.
If there are no transitions for more than
100 bit periods this signal will go high in-
ternally. Otherwise it will stay low.
u
A transmit channel
A receive channel
u
Transmit Channel
The determination of the output open col-
lector signal BITxP/N, will be generated
according to the logic table below.
Each transmit channel comprises:
u
One differential LVPECL signal input
(shaper)
u
Two cable drivers, providing G.703
interface signals.
BITA/B/C/G.775
Receive Channel
The cable drivers can be adjusted indi-
vidually, allowing optimum performance,
with minimum power consumption.
CMI Digital Output
Signal ON
CMI Analog Input
Signal ON
OK
FAIL
FAIL
OK
Signal ON
NO Signal
The shaper takes the distorted LVPECL
CMI signals and restores them to a near
square waveform internally. This signal is
sent out through the cable drivers. Both
of which are differential open collector
outputs. Both cable drivers are adjust-
able by use of a current control pin (cur-
rent mirroring).
NO Signal
Signal ON
NO Signal
NO Signal
Transmit Channel
CMI Analog Output
Signal ON
CMI Digital Input
Signal ON
OK
FAIL
FAIL
OK
Signal ON
NO Signal
Receive Channel
NO Signal
Signal ON
Each receive channel comprises:
u
NO Signal
NO Signal
A cable equaliser and a LOS (ITU-T
G.775 compliant Loss Of Signal de-
tector)
A selector and an LVPECL output
Hence if there is one or more FAIL condi-
tions, then the overall (-external BITxP/N
monitoring signals) will be low (voltage).
u
buffer.
The Equaliser takes the differential ana-
logue input signals, which have been
Öf-attenuated through the coax,
The internal signals BITA, BITB, BITC,
G.775 are OR’ed together.
equalises the signal, and send it to a se-
lector. From the selector the signal goes
to the output LVPECL buffer. This buffer
drives the signal outputs from circuit in-
tended for interconnection to the system
ASIC.
The LOS function monitors the input sig-
nal amplitude and generates a signal ac-
cording to ITU-T G.775.
Loopback Mode
The selector can be used to take the sig-
nal from the transmit channel and send it
out through RXOxx to the system ASIC
by setting the LOOPx high.
Build in Test
The build in test is a monitoring circuit,
which looks at the two input signals as
well as both output signals.
For the input signals for the receiver the
detection is determined by the use of the
ITU-T G.775 LOS function.
Data Sheet Rev.: 6
GD16360
Page 3 of 9
Pin List
Mnemonic:
Pin Number:
13, 14
24, 23
2, 3
Pin Type:
LVPECL-IN
LVPECL-IN
ANL-OUT
ANL-OUT
ANL-OUT
Description:
TXIN1P, TXIN1N
TXIN2P, TXIN2N
TXO1P, TXO1N
TXO2P, TXO2N
TXOM1P, TXOM1N
Distorted, LVPECL signal input, 100 - 1000 mVPP
Distorted, LVPECL signal input, 100 – 1000 mVPP
ITU-T G.703 interface, open collector output 26.7 mA nominally
ITU-T G.703 interface, open collector output 26.7 mA nominally
35, 34
6, 7
ITU-T G.703 interface, open collector output 26.7 mA nominally.
Monitor cable driver.
TXOM2P, TXOM2N
CIP1, CIP2
31, 30
1, 36
5, 32
ANL-OUT
ANL
ITU-T G.703 interface, open collector output 26.7 mA nominally.
Monitor cable driver.
CML open collector current control input. Connect resistor TBD W
to VDD + 1.7 V.
MCIP1, MCIP2
ANL
CML open collector current control input for Monitor cabledrivers.
Connect resistor TBD W to VDD + 1.7 V
RXIN1P, RXIN1N
RXIN2P, RXIN2N
RXO1P, RXO1N
RXO2P, RXO2N
RXOEN1
44, 45
42, 41
17, 16
20, 21
8
ANL-IN
ANL-IN
ITU-T G.703 input. f - Attenuated from coax.
ITU-T G.703 input. f - Attenuated from coax.
LVPECL output to system ASIC.
LVPECL-OUT
LVPECL-OUT
CMOS-IN
LVPECL output to system ASIC.
When LOW, RXO1P is forced LOW.
When LOW, RXO2P is forced LOW.
RXOEN2
29
CMOS-IN
LOS1
18
CMOS-OUT
ITU-T G.775 LOS detected from RXIN1P/N input. When LOS
flagged, output is LOW.
LOS2
19
9
CMOS-OUT
CMOS-IN
CMOS-IN
ITU-T G.775 LOS detected from RXIN2P/N input. When LOS
flagged, output is LOW.
LOOP1
Loop-back selector. When HIGH loop-back in transceiver 1 is
enabled.
LOOP2
28
Loop-back selector. When HIGH loop-back in transceiver 2 is
enabled.
BIT1P, BIT1N
10, 11
OPEN-
COLLECTOR
Build in test for transceiver 1. Determines status of GD16360 and
I/O signals determined from logic table above. If one or more fails
the positive output is low (voltage).
BIT2P, BIT2N
27, 26
OPEN-
COLLECTOR
Build in test for transceiver 2. Determines status of GD16360 and
I/O signals determined from logic table above. If one or more fails
the positive output is low (voltage).
VDD
VDD
4, 12, 15, 22,
33
PWR
PWR
Positive power supply 3.3 V for transceiver 1.
39, 40, 43, 46,
47
Positive power supply 3.3 V for transceiver 2.
VEE
25, 37
38, 48
PWR
PWR
0 V power, GND.
0 V power, GND.
Connected to VEE.
VEE
Heat sink
Data Sheet Rev.: 6
GD16360
Page 4 of 9
Package Pinout
1
36
35
34
33
32
31
30
29
28
27
26
25
CIP1
CIP2
2
TXO1P
TXO2P
TXO2N
VDD
3
TXO1N
4
VDD
5
MCIP1
MCIP2
TXOM2P
TXOM2N
RXOEN2
LOOP2
BIT2P
6
TXOM1P
7
TXOM1N
8
RXOEN1
9
LOOP1
10
BIT1P
11
BIT1N
BIT2N
VEE
12
VDD
Figure 1. Package 48 pin, Top View
Data Sheet Rev.: 6
GD16360
Page 5 of 9
Maximum Ratings
These are the limits beyond which the component may be damaged.
All voltages are referenced to VEE unless otherwise noted.
Symbol:
VDD
Characteristic:
Supply Voltage
Output Voltage
Output Current
Output Current
Input Voltage
Conditions:
MIN.:
0
TYP.:
MAX.:
5
UNIT:
V
VO max
IO,PECL max
IO,CMOS max
VI max
II max
LVPECL/CMOS
LVPECL
-0.5
VDD + 0.5
40
V
mA
mA
V
CMOS
-10
-0.5
-1.0
-55
10
LVPECL/CMOS
LVPECL/CMOS
Junction
VDD + 0.5
1.0
Input Current
mA
EC
EC
V
TO
Operating Temperature
Storage Temperature
ESD Voltage
+150
+175
Ts
Junction
-65
VESD
Note 1
500
FIT
TBD
Note 1: Human body model (100 pF, 1500 W) MIL 883 std.
Thermal Characteristics
TAMBIENT = -5 °C to 85 °C.
Thermal resistance qJ-C = TBD
Thermal resistance qJ-A = TBD
Note:
Heat sink will be used, see package outline.
Data Sheet Rev.: 6
GD16360
Page 6 of 9
DC Characteristics
All voltages in table are referred to VEE unless otherwise noted.
All input signal and power currents in the table are defined positive into the pin.
All output signal currents are defined positive out of the pin.
Symbol:
VDD
Characteristic:
Conditions:
MIN.:
TYP.:
MAX.:
3.45
UNIT:
V
Supply Voltage
3.15
3.30
IDD
Supply Current
Note 3
TBD
mA
V
VIC,LVPECL
VIDIFF,LVPECL
LVPECL Input Common Mode Voltage
LVPECL Differential Input Voltage
Shaper Input
VDD -1.5
VDD -1.1
1.000
Shaper Input,
Note 2
0.100
V
IIH,LVPECL
IIL,LVPECL
VOH,LVPECL
VOL,LVPECL
VODIFF,LVPECL
VIH,CMOS
LVPECL Input HI Current
LVPECL Input LO Current
LVPECL Output HI Voltage
LVPECL Output LO Voltage
LVPECL Output Differential Voltage
CMOS Input HI Voltage
V
IH LVPECL, max
IL LVPECL, min
100
mA
mA
V
V
-100
VDD -1.1
VDD -2.00
600
Note 1
Note 1
Note 1
VDD -0.70
VDD -1.62
1300
V
mV
V
VDD x0.8
0
VDD
VIL,CMOS
CMOS Input LO Voltage
CMOS Input HI Current
VDD x0.2
100
V
IIH ,CMOS
V
IH CMOS, max
IL CMOS, min
mA
mA
V
IIL ,CMOS
CMOS Input LO Current
CMOS Output HI Voltage
CMOS Output LO Voltage
V
-100
VDD - 0.1
0
VOH ,CMOS
VOL ,CMOS
IOH = 1mA
IOL = -1mA
VDD
0.1
V
Note 1: 50 W termination to VDD -2.0 V.
Note 2: Although VIDIFF,PECL may vary within VIH,MAX and VIL,MIN, it must not exceed VIDIFF,MAX.
Analog Characteristics
All specifications according to the CMI ITU-T interface are to be kept according to this standard.
The ‘shaper’ block is to be considered as a LVPECL input, with an external biasing according to note 1 above.
Symbol:
OVLDIN
SENSIN
RLIN
Characteristic:
Conditions:
G.703 interface
G.703 interface
Note 1
MIN.:
TYP.:
MAX.:
UNIT:
mVPP
dB
Input Overload
1000
Input Sensitivity
-15
-17
Input Return Loss
Output Return Loss
G.703 Output Voltage HI
G.703 Output Voltage LO
dB
RLOUT
Note 1
-17
dB
V
OH G.703
OL G.703
Note 2
0.45
0.55
-0.45
V
V
Note 2
-0.55
V
Note 1: G.703 interface open collector type. Actual value depends on discrete external circuitry.
Note 2: Measured in 75 W load via AC- or pulse transformer coupling
Data Sheet Rev.: 6
GD16360
Page 7 of 9
AC Characteristics
All voltages in table are referred to VEE unless otherwise noted.
All input signal and power currents in the table are defined positive into the pin.
All output signal currents are defined positive out of the pin.
Symbol:
TR-PECL
Characteristic:
PECL Rise Time
PECL Fall Time
CMOS Rise Time
CMOS Fall Time
Conditions:
Note 1
MIN.:
TYP.:
MAX.:
800
800
4
UNIT:
ps
TF-PECL
Note 1
ps
TR-CMOS
TF-CMOS
Note 2
ns
Note 2
4
ns
Note 1: 20 - 80 %, 50 W to VDD - 2.0 V.
Note 2: 20 - 80 %, 10 pF and 100 mA load.
Package Outline
Figure 2. Package 48 pin TQFP, EDQUAD
Data Sheet Rev.: 6
GD16360
Page 8 of 9
Device Marking
GD16360
<Wafer ID>
<YY WW>
Figure 3. Device Marking, Top View
External References
ITU-T G.703 (04/91):
ITU-T G.775 (11/94):
General Aspects of Digital transmissionsystems, terminal equipments.
LOS and AIS defect detection criteria.
Ordering Information
To order, please specify as shown below:
Product Name:
Intel Order number:
Package Type:
Ambient Temperature Range:
GD16360-48BA
FAGD1636048BA
MM#: 836046
48 Lead TQFP, EDQUAD
-5..85 EC
GD16360, Data Sheet Rev.: 6 - Date: 24 July 2001
an Intel company
Mileparken 22, DK-2740 Skovlunde
Denmark
Phone : +45 7010 1062
Distributor:
The information herein is assumed to be
reliable. GIGA assumes no responsibility
for the use of this information, and all such
information shall be at the users own risk.
Prices and specifications are subject to
change without notice. No patent rights or
licenses to any of the circuits described
herein are implied or granted to any third
party. GIGA does not authorise or warrant
any GIGA Product for use in life support
devices and/or systems.
Fax : +45 7010 1063
E-mail : sales@giga.dk
Web site : http://www.intel.com/ixa
Copyright © 2001 GIGA ApS
An Intel company
All rights reserved
Please check our Internet web site
for latest version of this data sheet.
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