BD9161FVM_12 [ROHM]

2.5V to 4.5V, 0.6A 1ch Synchronous Buck Converter Integrated FET; 2.5V至4.5V ， 0.6A 1路同步降压转换器集成FET


型号：	BD9161FVM_12
厂家：	ROHM
描述：	2.5V to 4.5V, 0.6A 1ch Synchronous Buck Converter Integrated FET 2.5V至4.5V ， 0.6A 1路同步降压转换器集成FET 转换器
文件：	总19页 (文件大小：922K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Datasheet

2.5V to 4.5V, 0.6A 1ch

Synchronous Buck Converter Integrated FET

BD9161FVM

●General Description

●Key Specifications

ROHM’s high efficiency step-down switching regulator

BD9161FVM is a power supply designed to produce

1.2volts (low voltage) from 3.3volts power supply line.

Offers high efficiency with our original pulse skip

control technology and synchronous rectifier.

Employs a current mode control system to provide

faster transient response to sudden change

in load.

 Input voltage range:

 Output voltage range:

 Output current:

 Switching frequency:

 Pch FET ON resistance:

 Nch FET ON resistance:

 Standby current:

2.5V to 4.5V

1.0V to 3.3V

0.6A(Max.)

1MHz(Typ.)

0.35Ω(Typ.)

0.37Ω(Typ.)

0μA (Typ.)

 Operating temperature range:

-25℃ to +85℃

●Features

●Package

 Offers fast transient response with current mode

PWM control system.

MSOP8:

2.90 mm x 4.00 mm x 0.83 mm

 Offers highly efficiency for all load range with

synchronous rectifier (Nch/Pch FET)

 Incorporates 100% Duty function.

 Incorporates soft-start function.

 Incorporates thermal protection and ULVO

functions.

●Applications

Power supply for HDD, DVD and for LSI of CPU, ASIC

 Incorporates short-current protection circuit with

time delay function.

 Incorporates shutdown function Icc=0μA (Typ.)

●Typical Application Circuit

VCC

Cin

VCC,PVCC

VOUT

ITH

ESR

GND,PGND

RITH

CITH

Fig.1 Typical application circuit

○Product structure：Silicon monolithic integrated circuit ○This product is not designed protection against radioactive rays.

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BD9161FVM

●Pin Configuration

(TOP VIEW)

Fig.2 Pin Configuration

●Pin Description

Pin No.

Pin name

ADJ

PIN function

Output voltage Feedback pin (Adjustable)

GmAmp output pin/Connected phase compensation capacitor

Enable pin (Active High)

ITH

GND

PGND

Ground

Nch FET source pin

Pch/Nch FET drain output pin

Pch FET source pin

PVCC

VCC

VCC power supply input pin

●Block Diagram

VCC

VREF

3.3V

Input

PVCC

Current

Comp.

Current

Sense/

Protect

Gm Amp.

Output

SLOPE

CLK

OSC

VCC

Driver

Logic

UVLO

PGND

Soft

Start

TSD

SCP

GND

ADJ

ITH

Fig.3 Block Diagram

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BD9161FVM

●Absolute Maximum Ratings(Ta=25℃)

Parameter

Symbol

VCC

Rating

-0.3 to +7 *1

-0.3 to +7

387.5*2

Unit

VCC voltage

PVCC voltage

PVCC

EN Voltage

SW, ITH Voltage

SW,ITH

Pd1

Power Dissipation 1

Power Dissipation 2

Operating temperature range

Storage temperature range

℃

Pd2

587.4*3

Topr

-25 to +85

-55 to +150

+150

Tstg

EN voltage

Tjmax

*1 Pd should not be exceeded.

*2 Derating in done 3.1mW/℃ for temperatures above Ta=25℃.

*3 Derating in done 4.7mW/℃ for temperatures above Ta=25℃,Mounted on 70mm×70mm×1.6mm Glass Epoxy PCB.

●Operating Ratings(Ta=25℃)

Limits

Parameter

Symbol

Unit

Min.

2.5

Typ.

Max.

4.5

VCC voltage

VCC^*4

PVCC^*4

3.3

PVCC voltage

3.3

4.5

EN voltage

VCC

3.3

Output Voltage Setting Range

SW,ITH

Isw^*4

1.0

SW, ITH average output current

0.6

*4 Pd should not be exceeded.

●Electrical Characteristics

◎(Ta=25℃, VCC=PVCC=3.3V, EN=VCC, unless otherwise specified.)

Limits

Parameter

Symbol

Unit

Conditions

EN=GND

Min.

Typ.

Max.

Standby current

ISTB

ICC

μA

Bias current

200

GND

VCC

400

0.8

EN Low voltage

VENL

VENH

IEN

Standby mode

Active mode

VEN=3.3V

EN High voltage

2.0

EN input current

μA

MHz

Ω

Oscillation frequency

Pch FET ON resistance

Nch FET ON resistance

Output voltage

FOSC

RONP

RONN

VOUT

ITHSI

0.8

1.2

0.6

0.68

0.816

0.35

0.37

0.8

PVCC=3.3V

Ω

0.784

2.2

2.22

0.5

ITH SInk current

μA

VOUT =H

VOUT =L

ITH Source Current

UVLO threshold voltage

UVLO hysteresis voltage

Soft start time

ITHSO

VUVLO1

VUVLO2

TSS

2.3

2.35

2.4

2.5

VCC=H→L

VCC=L→H

Timer latch time

TLATCH

SCP/TSD operated

Output Short circuit

Threshold Voltage

VSCP

0.4

0.56

VOUT =H→L

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BD9161FVM

●Typical Performance Curves

Fig.5 Ven-Vout

Fig.4 Vcc-Vout

Fig.7 Ta-VOUT

Fig.6 Iout-Vout

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BD9161FVM

Fig.8 Efficiency

Fig.9 Ta - Fosc

Fig.11 Ta-ICC

Fig.10 Ta-VEN

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BD9161FVM

Fig.13 Soft start waveform

Fig.12 Vcc-Fosc

Fig.14 SW waveform Io=10mA

Fig.15 SW waveform Io=500mA

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BD9161FVM

Fig. 16 SW waveform Io=600mA

Fig. 17 Transient response

Io=250→500mA(10μs)

Fig.18 Transient response

Io=500→250mA(10μs)

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BD9161FVM

●Application Information

Operation

BD9161FVM is a synchronous rectifying step-down switching regulator that achieves faster transient response by

employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for

heavier load, while it utilizes SLLM^TM(Simple Light Load Mode) operation for lighter load to improve efficiency.

○Current mode PWM control

Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.

・PWM (Pulse Width Modulation) control

The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a P-channel MOS FET (while a

N-channel MOS FET is turned OFF), and an inductor current I_Lincreases. The current comparator (Current Comp)

receives two signals, a current feedback control signal (SENSE: Voltage converted from I_L) and a voltage feedback

control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the

P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control

repeats this operation.

・SLLM^TM(Simple Light Load Mode) control

When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching

pulse is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation

without voltage drop or deterioration in transient response during the mode switching from light load to heavy load or

vise versa.

Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current

Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching

is tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces

the switching dissipation and improves the efficiency.

・100% Duty control

Max duty is 100%. (@ Pch MOS FET always ON) In usual PWM control, in case output voltage cannot keep (ex, drop

of input voltage), oscillation frequency becomes lower and finally it becomes 100% duty. The output voltage is a value

that depends only by on a voltage hang from the input voltage to Pch MOS FET, and can keep the output voltage even

with the low input voltage.

SENSE

Current

Comp

VOUT

RESET

Level

Shift

SET

Driver

Logic

VOUT

Gm Amp.

Load

OSC

ITH

Fig.19 Diagram of current mode PWM control

PVCC

SENSE

PVCC

Current

Comp

Current

SENSE

Comp

SET

GND

RESET

GND

IL(AVE)

VOUT

VOUT(AVE)

Not switching

Fig.21 SLLM^TMswitching timing chart

Fig.20 PWM switching timing chart

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BD9161FVM

Description of Operations

・Soft-start function

EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited

during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.

・Shutdown function

With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference

voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0μF (Typ.).

・UVLO function

Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width

of 50 mV (Typ.) is provided to prevent output chattering.

Hysteresis 50mV

VCC

VOUT

Tss

Soft start

Standby

mode

Standby

mode

Standby mode

Operating mode

Standby mode

UVLO

Fig.22 Soft start, Shutdown, UVLO timing chart

・Short-current protection circuit with time delay function

Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for

the fixed time (TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking

UVLO.

Output OFF

latch

VOUT

Limit

1msec

Standby

mode

Standby

mode

Operating mode

Timer latch

Fig.23 Short-current protection circuit with time delay timing chart

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BD9161FVM

Information on Advantages

Advantage 1：Offers fast transient response with current mode control system.

Conventional product (VOUT of which is 2.5 volts)

BD9161FVM (Load response IO=250mA→500mA)

VOUT

40mV

98mV

IOUT

Voltage drop due to sudden change in load was reduced by about 50%.

Fig.24 Comparison of transient response

Advantage 2： Offers high efficiency for all load range.

・For lighter load:

Utilizes the current mode control mode called SLLM^TMfor lighter load, which reduces various dissipation such as

switching dissipation (P_SW), gate charge/discharge dissipation, ESR dissipation of output capacitor (P_ESR) and

on-resistance dissipation (P_RON) that may otherwise cause degradation in efficiency for lighter load.

Achieves efficiency improvement for lighter load.

100

SLLM^TM

・For heavier load:

②

Utilizes the synchronous rectifying mode and the low on-resistance

MOS FETs incorporated as power transistor.

①

①inprovement by SLLM^TMsystem

PWM

②improvement by synchronous rectifier

ON resistance of P-channel MOS FET: 0.35 Ω (Typ.)

ON resistance of N-channel MOS FET: 0.37 Ω (Typ.)

0.001

0.01

0.1

Output current Io[A]

Fig.25 Efficiency

Achieves efficiency improvement for heavier load.

Offers high efficiency for all load range with the improvements mentioned above.

Advantage 3：・Supplied in smaller package due to small-sized power MOS FET incorporated.

・Allows reduction in size of application products

・Output capacitor Co required for current mode control: 10 μF ceramic capacitor

・Inductance L required for the operating frequency of 1 MHz: 4.7 μH inductor

Reduces a mounting area required.

VCC

15mm

CIN

Cin

RITH

CITH

DC/DC

Convertor

Controller

VOUT

10mm

RITH

CITH

Fig.26 Example application

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BD9161FVM

Switching Regulator Efficiency

Efficiency ŋ may be expressed by the equation shown below:

VOUT×IOUT

POUT

η=

×100[%]=

×100[%]

Vin×Iin

POUT+PDα

Efficiency may be improved by reducing the switching regulator power dissipation factors P_Dα as follows:

Dissipation factors:

1) ON resistance dissipation of inductor and FET：PD(I²R)

2) Gate charge/discharge dissipation：PD(Gate)

3) Switching dissipation：PD(SW)

4) ESR dissipation of capacitor：PD(ESR)

5) Operating current dissipation of IC：PD(IC)

1)PD(I²R)=IOUT ×(RCOIL+RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET

IOUT[A]：Output current.)

2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET, f[H]：Switching frequency, V[V]：Gate driving voltage of FET)

Vin²×CRSS×IOUT×f

3)PD(SW)=

(CRSS[F]：Reverse transfer capacitance of FET, IDRIVE[A]：Peak current of gate.)

IDRIVE

4)PD(ESR)=IRMS ×ESR (IRMS[A]：Ripple current of capacitor, ESR[Ω]：Equivalent series resistance.)

5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.)

Consideration on Permissible Dissipation and Heat Generation

As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is

needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input

voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation

must be carefully considered.

For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.

Because the conduction losses are considered to play the leading role among other dissipation mentioned above including

gate charge/discharge dissipation and switching dissipation.

1000

800

①Using an IC alone

θj-a=322.6℃/W

②mounted on glass epoxy PCB

θj-a=212.8℃/W

P=IOUT ×(RON)

RON=D×RONP+(1-D)×RONN

D：ON duty (=VOUT/VCC)

RONP：ON resistance of P-channel MOS FET

RONN：ON resistance of N-channel MOS FET

IOUT：Output current

②587.4mW

①387.5mW

600

400

200

75 85 100

125

150

Ambient temperature:Ta [℃]

Fig.27 Thermal derating curve

(MSOP8)

If VCC=3.3V, VOUT=2.5V RONP=0.35Ω, RONN=0.37Ω

IOUT=0.6A, for example,

D=VOUT/VCC=2.5/3.3=0.758

RON=0.758×0.35+(1-0.758)×0.37

=0.2653+0.08954

=0.35484[Ω]

P=0.6²×0.35484

≒127.7[mV]

As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. With the consideration

on the dissipation as above, thermal design must be carried out with sufficient margin allowed.

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BD9161FVM

Selection of Components Externally Connected

1. Selection of inductor (L)

The inductance significantly depends on output ripple current.

As seen in the equation (1), the ripple current decreases as the

inductor and/or switching frequency increases.

ΔIL

VCC

(VCC-VOUT)×VOUT

[A]・・・(1)

ΔIL=

L×VCC×f

Appropriate ripple current at output should be 20 to 30% more or less

of the maximum output current.

VOUT

ΔIL=0.25×IOUTmax. [A]・・・(2)

(VCC-VOUT)×VOUT

[H]・・・(3)

ΔIL×VCC×f

(ΔIL: Output ripple current, and f: Switching frequency)

Fig.28 Output ripple current

* Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases

efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its

current rating.

If VCC=3.3V, VOUT=2.5V, f=1MHz, ΔIL=0.25×0.6A=0.15A

(3.3-2.5)×2.5

0.15×3.3×1M

L≧

≧4.04μ

* Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for

better efficiency.

2. Selection of output capacitor (CO)

VCC

Output capacitor should be selected with the consideration on the stability

region and the equivalent series resistance required to smooth ripple voltage.

Output ripple voltage is determined by the equation (4)：

VOUT

ΔVOUT=ΔIL×ESR [V]・・・(4)

ESR

(ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor)

*Rating of the capacitor should be determined allowing sufficient margin against

output voltage. Less ESR allows reduction in output ripple voltage.

Fig.29 Output capacitor

Inappropriate capacitance may cause problem in startup. A 10μF to 100μF ceramic capacitor is recommended.

3. Selection of input capacitor (Cin)

Input capacitor to select must be a low ESR capacitor of the capacitance

sufficient to cope with high ripple current to prevent high transient voltage. The

ripple current IRMS is given by the equation (5):

VCC

Cin

√

VOUT

VOUT(VCC-VOUT)

IRMS=IOUT×

[A]・・・(5)

VCC

< Worst case > IRMS(max.)

IOUT

When VCC is twice the Vout,

Fig.30 Input capacitor

If VCC=3.3V, VOUT=2.5V, and IOUTmax.=0.6A

√

2.5(3.3-2.5)

IRMS=0.6×

=0.284[ARMS]

A low ESR 10μF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.

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BD9161FVM

4. Determination of RITH, CITH that works as a phase compensator

As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area

due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high

frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the

power amplifier output with C and R as described below to cancel a pole at the power amplifier.

fp(Min.)

fp=

fp(Max.)

2π×RO×CO

Gain

[dB]

fz(ESR)=

fz(ESR)

2π×ESR×CO

IOUTMin.

IOUTMax.

Pole at power amplifier

When the output current decreases, the load resistance Ro

increases and the pole frequency lowers.

Phase

[deg]

-90

fp(Min.)=

fp(Max.)=

[Hz]←with lighter load

2π×ROMax.×CO

Fig.31 Open loop gain characteristics

[Hz]←with heavier load

2π×ROMin.×CO

fz(Amp.)

Zero at power amplifier

Gain

[dB]

Increasing capacitance of the output capacitor lowers the

pole frequency while the zero frequency does not change.

(This is because when the capacitance is doubled, the

capacitor ESR reduces to half.)

Phase

[deg]

fz(Amp.)=

-90

2π×RITH.×CITH

Fig.32 Error amp phase compensation characteristics

Cin

VCC

VCC,PVCC

VOUT

ITH

ESR

GND,PGND

RITH

CITH

Fig.33 Typical application

Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load

resistance with CR zero correction by the error amplifier.

fz(Amp.)= fp(Min.)

2π×RITH×CITH

2π×ROMax.×CO

5. Determination of output voltage

The output voltage VOUT is determined by the equation (6):

Output

VOUT=(R2/R1+1)×VADJ・・・(6) VADJ: Voltage at ADJ terminal (0.8V Typ.)

With R1 and R2 adjusted, the output voltage may be determined as required.

(Adjustable output voltage range： 1.0V to 3.3V )

ADJ

Use 1 kΩ to 100 kΩ resistor for R1. If a resistor of the resistance higher than

100 kΩ is used, check the assembled set carefully for ripple voltage etc.

Fig.34 Determination of output voltage

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BD9161FVM

BD9161FVM Cautions on PC Board Layout

Fig.35 Board layout

For the sections drawn with heavy line, use thick conductor pattern as short as possible.

①

②

Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the

pin PGND.

③

Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring.

Recommended Component Lists With Above Applications

Symbol Part

Value

Manufacturer

TDK

Series

VLF5014AT-4R7M1R1

CMD6D11B

Coil

4.7μH

Sumida

ROHM

Kyocera

murata

ROHM

RIN

CIN

Resistance

10Ω

10μF

MCR03 Series

CM316X5R106K10A

GRM18 Series

MCR03 Series

Ceramic capacitor

V_OUT=1.0V

820pF

560pF

470pF

330pF

6.8kΩ

8.2Ω

12kΩ

15kΩ

V_OUT=1.2V

V_OUT=1.5V

V_OUT=1.8V

V_OUT=2.5V

V_OUT=1.0V

V_OUT=1.2V

V_OUT=1.5V

V_OUT=1.8V

V_OUT=2.5V

CITH

RITH

Resistance

* The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your

application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the

depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When

switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier

diode established between the SW and PGND pins.

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Datasheet

BD9161FVM

●I/O Equivalence Circuit

・EN pin

PVCC

・SW pin

10kΩ

・ITH pin

・ADJ pin

VCC

10kΩ

ADJ

ITH

Fig.36 I/O equivalence circuit

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Datasheet

BD9161FVM

●Operational Notes

1. Absolute Maximum Ratings

While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum

ratings including the voltage applied and the operating temperature range may result in breakage. If broken, short-mode or

open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the absolute

maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.

2. Electrical potential at GND

GND must be designed to have the lowest electrical potential In any operating conditions.

3. Short-circuiting between terminals, and mismounting

When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may

result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and

power supply or GND may also cause breakdown.

4.Operation in Strong electromagnetic field

Be noted that using the IC in the strong electromagnetic radiation can cause operation failures.

5. Thermal shutdown protection circuit

Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to

protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not

be used thereafter for any operation originally intended.

6. Inspection with the IC set to a pc board

If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the

capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper

grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the

inspection process, be sure to turn OFF the power supply before it is connected and removed.

7. Input to IC terminals

This is a monolithic IC with P⁺isolation between P-substrate and each element as illustrated below. This P-layer and

the N-layer of each element form a P-N junction, and various parasitic element are formed.

If a resistor is joined to a transistor terminal as shown in Fig 37:

○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or

GND>Terminal B (at transistor side); and

○if GND>Terminal B (at NPN transistor side),

a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.

The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,

and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such

manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in

activation of parasitic elements.

Fig.37 Simplified structure of monorisic IC

8. Ground wiring pattern

If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND

pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that

resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the

small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.

Status of this document

The Japanese version of this document is formal specification. A customer may use this translation version only for a reference

to help reading the formal version.

If there are any differences in translation version of this document formal version takes priority

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TSZ22111･15･001

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02.MAR.2012 Rev.001

Datasheet

BD9161FVM

●Ordering Information

B D 9

V M -

T R

Package

Packaging and forming specification

TR: Embossed tape and reel

FVM: MSOP8

●Physical Dimension, Tape and Reel information

●Marking Diagram

MSOP8(TOP VIEW)

Part Number Marking

LOT Number

1PIN MARK

www.rohm.com

TSZ22111･15･001

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Daattaasshheeeett

Notice

●Precaution for circuit design

1) The products are designed and produced for application in ordinary electronic equipment (AV equipment, OA

equipment, telecommunication equipment, home appliances, amusement equipment, etc.). If the products are to be

used in devices requiring extremely high reliability (medical equipment, transport equipment, aircraft/spacecraft,

nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose

malfunction or operational error may endanger human life and sufficient fail-safe measures, please consult with the

ROHM sales staff in advance. If product malfunctions may result in serious damage, including that to human life,

sufficient fail-safe measures must be taken, including the following:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits in the case of single-circuit failure

2) The products are designed for use in a standard environment and not in any special environments. Application of the

products in a special environment can deteriorate product performance. Accordingly, verification and confirmation of

product performance, prior to use, is recommended if used under the following conditions:

[a] Use in various types of liquid, including water, oils, chemicals, and organic solvents

[b] Use outdoors where the products are exposed to direct sunlight, or in dusty places

[c] Use in places where the products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2,

and NO2

[d] Use in places where the products are exposed to static electricity or electromagnetic waves

[e] Use in proximity to heat-producing components, plastic cords, or other flammable items

[f] Use involving sealing or coating the products with resin or other coating materials

[g] Use involving unclean solder or use of water or water-soluble cleaning agents for cleaning after soldering

[h] Use of the products in places subject to dew condensation

3) The products are not radiation resistant.

4) Verification and confirmation of performance characteristics of products, after on-board mounting, is advised.

5) In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse) is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

6) De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta).

When used in sealed area, confirm the actual ambient temperature.

7) Confirm that operation temperature is within the specified range described in product specification.

8) Failure induced under deviant condition from what defined in the product specification cannot be guaranteed.

●Precaution for Mounting / Circuit board design

1) When a highly active halogenous (chlorine, bromine, etc.) flux is used, the remainder of flux may negatively affect

product performance and reliability.

2) In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the

Company in advance.

Regarding Precaution for Mounting / Circuit board design, please specially refer to ROHM Mounting specification

●Precautions Regarding Application Examples and External Circuits

1) If change is made to the constant of an external circuit, allow a sufficient margin due to variations of the characteristics

of the products and external components, including transient characteristics, as well as static characteristics.

2) The application examples, their constants, and other types of information contained herein are applicable only when

the products are used in accordance with standard methods. Therefore, if mass production is intended, sufficient

consideration to external conditions must be made.

Notice - Rev.001

Daattaasshheeeett

●Precaution for Electrostatic

This product is Electrostatic sensitive product, which may be damaged due to Electrostatic discharge. Please take proper

caution during manufacturing and storing so that voltage exceeding Product maximum rating won't be applied to products.

Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from

charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

●Precaution for Storage / Transportation

1) Product performance and soldered connections may deteriorate if the products are stored in the following places:

[a] Where the products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2

[b] Where the temperature or humidity exceeds those recommended by the Company

[c] Storage in direct sunshine or condensation

[d] Storage in high Electrostatic

2) Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using products of which storage time is

exceeding recommended storage time period .

3) Store / transport cartons in the correct direction, which is indicated on a carton as a symbol. Otherwise bent leads may

occur due to excessive stress applied when dropping of a carton.

4) Use products within the specified time after opening a dry bag.

●Precaution for product label

QR code printed on ROHM product label is only for internal use, and please do not use at customer site. It might contain a

internal part number that is inconsistent with an product part number.

●Precaution for disposition

When disposing products please dispose them properly with a industry waste company.

●Precaution for Foreign exchange and Foreign trade act

Since concerned goods might be fallen under controlled goods prescribed by Foreign exchange and Foreign trade act,

please consult with ROHM in case of export.

●Prohibitions Regarding Industrial Property

1) Information and data on products, including application examples, contained in these specifications are simply for

reference; the Company does not guarantee any industrial property rights, intellectual property rights, or any other

rights of a third party regarding this information or data. Accordingly, the Company does not bear any responsibility for:

[a] infringement of the intellectual property rights of a third party

[b] any problems incurred by the use of the products listed herein.

2) The Company prohibits the purchaser of its products to exercise or use the intellectual property rights, industrial

property rights, or any other rights that either belong to or are controlled by the Company, other than the right to use,

sell, or dispose of the products.

Notice - Rev.001

BD9161FVM_12 [ROHM]

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