ENA0965 [SANYO]
CMOS IC Internal 96K/80K/64K/48K-byte ROM 4096-byte RAM 8-bit 1-chip Microcontroller; CMOS IC内部96K / 80K / 64K / 48K字节的ROM 4096字节RAM的8位单芯片微控制器
| 型号： | ENA0965 |
| 厂家： | 
SANYO SEMICON DEVICE |
| 描述： | CMOS IC Internal 96K/80K/64K/48K-byte ROM 4096-byte RAM 8-bit 1-chip Microcontroller |
| 文件： | 总25页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering number : EN*A0965
CMOS IC
Internal 96K/80K/64K/48K-byte ROM
4096-byte RAM
LC877696B,LC877680B
LC877664B,LC877648B
8-bit 1-chip Microcontroller
Overview
The LC877600B series are an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 96K-48Kbyte ROM, 4K-byte RAM, an LCD
controller/driver, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer (may be divided
into 8-bit timers or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a day
and time counter, a synchronous SIO interface (with automatic block transmission/reception capabilities), an
asynchronous/synchronous SIO interface, a UART interface (full duplex), a 12-bit 12-channel AD converter, two 12-bit
PWM channels, a high-speed clock counter, a system clock frequency divider, a small signal detector, an infrared remote
controller receiver function, and a 23-source 10-vector interrupt feature.
Features
ROM
• 98304 × 8bits (LC877696B)
• 81920 × 8bits (LC877680B)
• 65536 × 8bits (LC877664B)
• 49152 × 8bits (LC877648B)
RAM
• 4096 × 9 bits
Minimum Bus Cycle Time
• 83.3ns (12MHz)
• 125ns (8MHz)
• 250ns (4MHz)
V
DD
V
DD
V
DD
V
DD
=3.0 to 5.5V (target value)
=2.5 to 5.5V (target value)
=2.2 to 5.5V (target value)
=1.7 to 5.5V (target value)
• 30.5μs (32.768kHz)
Note: The bus cycle time here refers to the ROM read speed.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
'
s products or
equipment.
Ver.0.010
61808HKIM No.A0965-1/25
LC877696B/80B/64B/48B
Minimum Instruction Cycle Time (tCYC)
• 250ns (12MHz)
• 375ns (8MHz)
• 750ns (4MHz)
• 91.5μs(32.768kHz)
V
V
V
V
=3.0 to 5.5V (target value)
DD
DD
DD
DD
=2.5 to 5.5V (target value)
=2.2 to 5.5V (target value)
=1.7 to 5.5V (target value)
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units 23 (P1n, P30 to P31, P70 to P73, P8n, XT2)
Ports whose I/O direction can be designated in 4-bit units 8 (P0n)
• Normal withstand voltage input port
• LCD ports
1 (XT1)
Segment output
32 (S00 to S31)
4 (COM0 to COM3)
3 (V1 to V3)
Common output
Bias terminals for LCD driver
Other functions
Input/output ports
Input ports
32 (PAn, PBn, PCn, PDn,)
7 (PLn)
• Dedicated oscillator ports
• Reset pins
• Power pins
2 (CF1, CF2)
1 (
RES
)
6 (V 1 to V 3, V 1 to V 3)
SS SS DD DD
LCD Controller
1) Seven display modes are available (static, 1/2, 1/3, 1/4 duty × 1/2, 1/3 bias)
2) Segment output and common output can be switched to general-purpose input/output ports
Small Signal Detection (MIC signals etc)
1) Counts pulses with the level which is greater than a preset value
2) 2-bit counter
Timers
• Timer 0: 16-bit timer/counter with capture registers.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with 8-bit capture registers) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with 8-bit capture registers)
+ 8-bit counter (with 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with 16-bit capture registers)
Mode 3: 16-bit counter (with 16-bit capture registers)
• Timer 1: 16-bit timer that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs)
+ 8-bit timer with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock,
and timer 0 prescaler output.
2) Interrupts programmable in 5 different time schemes
• Day and time counter
1) Used with a base timer, the day and time counter can be used as a 65000 day + minute + second counter.
No.A0965-2/25
LC877696B/80B/64B/48B
High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2) Can generate output real-time.
SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits specifiable in 1-bit units, suspension and resumption of
data transmission possible in 1-byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect)
UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator
AD Converter: 12 bits × 12 channels
PWM: Multi frequency 12-bit PWM × 2 channels
Infrared Remote Control Receiver Circuit
1) Noise reduction function
(Time constant of noise reduction filter: approx. 120μs, when selecting a 32.768kHz crystal oscillator as a
reference clock.)
2) X’tal HOLD mode cancellation function
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Clock Output Function
1) Can output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32,or 1/64 as system clock.
2) Can output the source oscillation clock for the sub clock.
No.A0965-3/25
LC877696B/80B/64B/48B
Interrupts Source Flags
• 23 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No.
1
Vector Address
00003H
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
INT1
2
0000BH
00013H
INT2/T0L/remote control receiver
INT3/base timer 0/base timer 1
T0H
3
4
0001BH
00023H
5
T1L/T1H
6
0002BH
00033H
SIO0/UART1 receive
SIO1/UART1 transmit
ADC/MIC/T6/T7/PWM4, PWM5
Port 0/T4/T5
7
8
0003BH
00043H
9
10
0004BH
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• IFLG (List of interrupt source flag function)
1) Shows a list of interrupt source flags that caused a branching to a particular vector address
Subroutine Stack Levels: 2048 levels maximum (The stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
• 24 bits × 16 bits
• 16 bits ÷ 8 bits
• 24 bits ÷ 16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal): For system clock
• CF oscillation circuit: For system clock, with internal Rf and external Rd
• Crystal oscillation circuit: For low-speed system clock, with internal Rf and external Rd
• Multifrequency RC oscillation circuit (internal): For system clock
1) Adjustable in 4% (typ) increments from the selected center frequency.
2) Measures the frequency of the source oscillation clock using the input signal from XT1 as the reference.
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs,
and 76.8μs (at a main clock rate of 10MHz).
System Clock Multiplier Function
• Allows the 2 or 3 times the clock frequency to be selected when the crystal oscillation output is used as the system
clock.
No.A0965-4/25
LC877696B/80B/64B/48B
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
(Some parts of the serial transfer function stops operation.)
1) Oscillation is not stopped automatically.
2) Canceled by a system reset or occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, X’tal, and multifrequency RC oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, and INT2, pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer
and infrared remote controller circuit.
1) The CF, RC, and multifrequency RC oscillators automatically stop operation
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, and INT2 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
(5) Having an interrupt source established in the infrared remote control receiver circuit
On-chip Debugger function
• Supports software debugging with the IC mounted on the target board.
Package Form
• QFP80(14×14):
• TQFP80J(12×12):
Lead-free type
Lead-free type
Development Tools
• On-chip debugger: TCB87-TypeB + LC87F76C8A
Flash ROM Programming Board
Package
Programming Board
W87F71256QF
QFP80(14×14)
TQFP80J(12×12)
W87F71256SQ
Same Package and Pin Assignment as Flash ROM Version
1) LC877600 series options can be specified by using flash ROM data. Thus the board used for mass production can
be used for debugging and evaluation without modifications.
2) If the program for the mask ROM version is used, the size of the available ROM/RAM spaces is the same as
that of the mask ROM version.
No.A0965-5/25
LC877696B/80B/64B/48B
Package Dimensions
unit : mm (typ)
3255
17.2
14.0
60
41
61
40
21
80
20
1
0.25
0.15
0.65
(0.83)
SANYO : QFP80(14X14)
Package Dimensions
unit : mm (typ)
3290
14.0
12.0
60
41
61
40
21
80
1
20
0.125
0.5
0.2
(1.25)
SANYO : TQFP80J(12X12)
No.A0965-6/25
LC877696B/80B/64B/48B
Pin Assignment
COM0/PL0
COM1/PL1
COM2/PL2
COM3/PL3
P30/ PWM4
40
V
V
2
2
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SS
DD
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
S14/PB6
S13/PB5
S12/PB4
S11/PB3
S10/PB2
S9/PB1
S8/PB0
S7/PA7
S6/PA6
S5/PA5
S4/PA4
S3/PA3
S2/PA2
S1/PA1
S0/PA0
V
V
3
3
SS
DD
P31/ PWM5
P00/UTX1
P01/URX1
P02
LC877696B
LC877680B
LC877664B
LC877648B
P03
P04
P05/CKO
P06/T6O
P07/T7O
P10/SO0
P11/SI0/SB0
P12/SCK0
P13/SO1
P73/INT3/T0IN/RMIN
P72/INT2/T0IN/NKIN
P71/INT1/T0HCP/AN9
Top view
SANYO: QFP80(14×14)
“Lead-free Type”
SANYO: TQFP80J(12×12) “Lead-free Type”
No.A0965-7/25
LC877696B/80B/64B/48B
System Block Diagram
Interrupt control
IR
PLA
Standby control
Flash ROM
CF
RC
PC
VMRC
X’tal
SIO0
SIO1
Bus interface
Port 0
ACC
B register
Timer 0
(High speed clock counter)
C register
Port 1
Port 3
Timer 1
ALU
Port 7
Port 8
Timer 4
Timer 5
PSW
RAR
INT0 to INT3
Noise rejection filter
Timer 6
Timer 7
RAM
Small signal detector
ADC
LCD
controller
Stack pointer
Watchdog
timer
Infrared remote
control receiver
UART1
Base timer
Day and time
counter
PWM4/PWM5
No.A0965-8/25
LC877696B/80B/64B/48B
Pin Description
Pin Name
I/O
Description
Option
No
V
V
V
V
V
V
1
-
- power supply pin
+ power supply pin
• 8-bit I/O port
SS
2
3
1
SS
SS
-
No
DD
DD
DD
2
3
PORT0
I/O
Yes
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• Input for HOLD release
• Input for port 0 interrupt
• Shared pins
P00: UART1 transmit
P01: UART1 receive
P05: Clock output (system clock/subclock selectable)
P06: Timer 6 toggle output
P07: Timer 7 toggle output
PORT1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1 PWML output
P17: Timer 1PWMH output/beeper output
• 2-bit I/O port
PORT3
I/O
I/O
Yes
• I/O specifiable in 1-bit units
P30 to P31
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P30: PWM4 output
P31: PWM5 output
PORT7
• 4-bit I/O port
No
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD release input/timer 0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/
infrared remote control receiver input
AD converter input ports: AN8 (P70), AN9 (P71)
• Interrupt acknowledge type
Rising &
Rising
Falling
H level
L level
Falling
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Continued on next page.
No.A0965-9/25
LC877696B/80B/64B/48B
Continued from preceding page.
Pin Name
PORT8
I/O
I/O
Description
Option
No
• 8-bit I/O port
• I/O specifiable in 1-bit units
P80 to P87
• Shared pins
AD converter input ports: AN0 to AN7
Small signal detector input port: MICIN (P87)
• Segment output for LCD
S0/PA0 to
S7/PA7
I/O
I/O
I/O
I/O
I/O
I/O
No
No
No
No
No
No
• Can be used as general-purpose I/O port (PA)
• Segment output for LCD
S8/PB0 to
S15/PB7
• Can be used as general-purpose I/O port (PB)
• Segment output for LCD
S16/PC0 to
S23/PC7
• Can be used as general-purpose I/O port (PC)
• Segment output for LCD
S24/PD0 to
S31/PD7
• Can be used as general-purpose I/O port (PD)
• Common output for LCD
COM0/PL0 to
COM3/PL3
V1/PL4 to
V3/PL6
• Can be used as general-purpose input port (PL)
• LCD drive bias power supply
• Can be used as general-purpose input port (PL)
• Shared pins
RES
XT1
Input
Input
Reset pin
No
No
• 32.768kHz crystal oscillator input pin
• Shared pins
General-purpose input port
Must be connected to V 1 if not to be used.
DD
AD converter input port: AN10
• 32.768kHz crystal oscillator output pin
• Shared pins
XT2
I/O
No
General-purpose I/O port
Must be set for oscillation and kept open if not to be used.
AD converter input port: AN11
Ceramic resonator input pin
CF1
CF2
Input
No
No
Output
Ceramic resonator output pin
No.A0965-10/25
LC877696B/80B/64B/48B
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Option Selected
Port Name
Option Type
Output Type
Pull-up Resistor
in Units of
1 bit
P00 to P07
1
2
CMOS
Programmable (Note)
No
N-channel open drain
CMOS
P10 to P17
P30 to P31
1 bit
1 bit
1
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
No
2
N-channel open drain
CMOS
1
2
N-channel open drain
N-channel open drain
CMOS
P70
-
-
-
-
-
-
-
-
No
No
No
No
No
No
No
No
P71 to P73
P80 to P87
S0/PA0 to S31/PD7
COM0/PL0 to COM3/PL3
V1/PL4 to V3/PL6
XT1
N-channel open drain
CMOS
Programmable
No
Input only
Input only
Input only
No
No
XT2
Output for 32.768kHz crystal oscillator (Nch-open
drain when in general-purpose output mode)
No
Note: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07).
*1 Connect the IC as shown below to minimize the noise input to the V 1 pin.
DD
Be sure to electrically short the V 1, V 2, and V 3 pins.
SS SS SS
LSI
V
1
DD
Power
supply
For backup *2
V
V
2
3
DD
DD
V
1
V
2
V
3
SS
SS
SS
*2 The internal memory is sustained by V 1. If none of V 2 and V 3 are backed up, the high level output at the
DD DD DD
ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus
shortening the backup time.
Make sure that the port outputs are held at the low level in the HOLD backup mode.
No.A0965-11/25
LC877696B/80B/64B/48B
Absolute Maximum Ratings at Ta = 25°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
-0.3
unit
DD
Maximum supply
voltage
V
max
V
1,V 2, V
3
V
V
1=V 2=V
DD
3
3
DD
DD
DD
DD
DD
DD
DD
+6.5
Supply voltage for
LCD
VLCD
V1/PL4, V2/PL5,
V3/PL6
1=V 2=V
DD
DD
-0.3
-0.3
V
DD
V
Input voltage
V (1)
I
• Port L
V
V
+0.3
DD
• XT1, CF1,
RES
Input/output
voltage
V
(1)
• Ports 0, 1, 3, 7, 8
• Ports A, B, C, D
• XT2
IO
-0.3
+0.3
DD
Peak output
current
IOPH(1)
IOPH(2)
Ports 0, 1
• CMOS output selected
• Per applicable pin
• CMOS output selected
• Per applicable pin
Per applicable pin
-10
-20
Port 3
IOPH(3)
IOPH(4)
IOMH(1)
Ports 71 to 73
Ports A, B, C, D
Ports 0, 1
-5
-5
Per applicable pin
Average
• CMOS output selected
• Per applicable pin
• CMOS output selected
• Per applicable pin
Per applicable pin
-7.5
-15
output current
(Note 1-1)
IOMH(2)
Port 3
IOMH(3)
IOMH(4)
ΣIOAH(1)
Ports 71 to 73
Ports A, B, C, D
Ports 0, 1, 31
-3
-3
Per applicable pin
Total output
current
Total of currents at all
applicable pins
-25
-15
-40
-5
ΣIOAH(2)
ΣIOAH(3)
ΣIOAH(4)
ΣIOAH(5)
ΣIOAH(6)
ΣIOAH(7)
Port 30
Total of currents at all
applicable pins
Ports 0, 1, 3
Ports 71 to 73
Ports A, B
Total of currents at all
applicable pins
mA
Total of currents at all
applicable pins
Total of currents at all
applicable pins
-25
-25
-45
Ports C, D
Total of currents at all
applicable pins
Ports A, B, C, D
Total of currents at all
applicable pins
Peak output
current
IOPL(1)
IOPL(2)
IOPL(3)
Ports 0, 1
Port 3
Per applicable pin
20
30
Per applicable pin
Per applicable pin
• Ports 7, 8
• XT2
10
IOPL(4)
IOML(1)
IOML(2)
IOML(3)
Ports A, B, C, D
Per applicable pin
Per applicable pin
Per applicable pin
Per applicable pin
10
15
20
Average
Ports 0, 1
Port 3
output current
(Note 1-1)
• Ports 7, 8
• XT2
7.5
7.5
IOML(4)
Ports A, B, C, D
Per applicable pin
Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms.
Continued on next page.
No.A0965-12/25
LC877696B/80B/64B/48B
Continued from preceding page.
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
DD
Total output
current
ΣIOAL(1)
Ports 0, 1, 31
Port 30
Total of currents at all
applicable pins
45
45
80
20
45
45
80
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
ΣIOAL(5)
ΣIOAL(6)
ΣIOAL(7)
Pd max
Total of currents at all
applicable pins
Ports 0, 1, 3
Total of currents at all
applicable pins
• Ports 7, 8
• XT2
Total of currents at all
applicable pins
mA
Ports A, B
Total of currents at all
applicable pins
Ports C, D
Total of currents at all
applicable pins
Ports A, B, C, D
Total of currents at all
applicable pins
Maximum power
dissipation
QFP80(14×14)
Ta=-40 to +85°C
289.51
236.74
mW
TQFP80J(12×12)
Operating ambient
temperature
Topr
Tstg
-40
+85
°C
Storage ambient
temperature
-55
+125
Note 1-1: Average output current refers to the average of output currents measured for a period of 100 ms.
Allowable Operating Range at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
typ max
5.5
Parameter
Symbol
Pin/Remarks
1=V 2=V 3
DD
Conditions
V
[V]
min
unit
DD
Operating
V
V
V
V
(1)
V
0.237μs≤tCYC≤200μs
0.356μs≤tCYC≤200μs
0.712μs≤tCYC≤200μs
10μs≤tCYC≤200μs
3.0
2.5
2.2
1.7
DD
DD
DD
supply voltage
(2)
(3)
(4)
5.5
5.5
5.5
DD
DD
DD
Memory
VHD
V
1
RAM and register contents
sustained in HOLD mode
DD
sustaining
supply voltage
High level input
voltage
1.5
5.5
V
(1)
• Ports 0, 3, 8
• Ports A, B, C, D
• Port L
Output disabled
IH
0.3V
DD
1.7 to 5.5
1.7 to 5.5
V
V
DD
+0.7
V
V
(2)
• Port 1
• Output disabled
• When INT1VTSL=0
(P71only)
IH
• Ports 71 to 73
• Port 70 port input/
interrupt side
0.3V
DD
DD
+0.7
V
V
V
V
(3)
(4)
(5)
(6)
Port 71 interrupt side
• Output disabled
• When INT1VTSL=1
Output disabled
IH
IH
IH
IH
1.7 to 5.5
1.7 to 5.5
0.85V
V
V
DD
DD
DD
Port 87 small signal
input side
0.75V
0.9V
DD
Port 70 watchdog
timer side
Output disabled
1.7 to 5.5
1.7 to 5.5
V
V
DD
DD
XT1, XT2, CF1,
RES
0.75V
DD
DD
Continued on next page.
No.A0965-13/25
LC877696B/80B/64B/48B
Continued from preceding page.
Specification
typ max
Parameter
Symbol
(1)
Pin/Remarks
Conditions
Output disabled
V
[V]
min
V
unit
DD
Low level input
voltage
V
• Ports 0, 3, 8
• Ports A, B, C, D
• Port L
0.15V
IL
DD
+0.4
4.0 to 5.5
2.2 to 4.0
4.0 to 5.5
SS
V
0.2V
SS
SS
DD
2)
• Port 1
• Output disabled
• When INT1VTSL=0
(P71 only)
0.1V
VIL(
DD
V
• Ports 71 to 73
• Port 70 port input/
interrupt side
+0.4
1.7 to 4.0
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
V
V
V
0.2V
DD
SS
SS
SS
V
V
V
V
V
(3)
(4)
(5)
(6)
Port 71 interrupt side
• Output disabled
• When INT1VTSL=1
Output disabled
IL
IL
IL
IL
0.45V
DD
DD
Port 87 small signal
input side
0.25V
0.8V
Port 70 watchdog
timer side
Output disabled
DD
V
V
SS
-1.0
XT1, XT2, CF1,
RES
1.7 to 5.5
3.0 to 5.5
2.5 to 5.5
2.2 to 5.5
1.7 to 5.5
3.0 to 5.5
2.5 to 5.5
0.25V
DD
SS
Instruction cycle
time
tCYC
0.237
0.356
0.712
10
200
200
200
200
12
μs
(Note 2-1)
External system
clock frequency
FEXCF(1)
CF1
• CF2 pin open
0.1
• System clock frequency
division ratio=1/1
0.1
8
• External system clock
DUTY50±5%
2.2 to 5.5
0.1
4
• CF2 pin open
3.0 to 5.5
2.5 to 5.5
2.2 to 5.5
0.2
0.2
0.2
24.4
16
8
• System clock frequency
division ratio=1/2
Oscillation
FmCF(1)
FmCF(2)
FmCF(3)
CF1, CF2
CF1, CF2
CF1, CF2
• 12MHz ceramic oscillation
• See figure 1.
3.0 to 5.5
2.5 to 5.5
12
frequency range
(Note 2-2)
• 8MHz ceramic oscillation
• See figure 1.
8
MHz
• 4MHz ceramic oscillation
• See figure 1.
2.2 to 5.5
2.2 to 5.5
4
FmRC
Internal RC oscillation
0.3
1.0
2.0
FmVMRC(1)
• Multifrequency RC source
oscillation
• VMRAJ2 to 0=4,
VMFAJ2 to 0=0,
2.2 to 5.5
10
When VMSL4M=0
• Multifrequency RC source
oscillation
FmVMRC(2)
• VMRAJ2 to 0=4,
VMFAJ2 to 0=0,
2.2 to 5.5
1.7 to 5.5
4
When VMSL4M=1
• 32.768kHz crystal oscillation
• See figure 2.
FsX’tal
XT1, XT2
32.768
kHz
Multifrequency
RC oscillation
usable range
Multifrequency
RC oscillation
adjustment
OpVMRC(1)
OpVMRC(2)
When VMSL4M=0
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
8
3.5
8
10
4
12
4.5
64
MHz
When VMSL4M=1
VmADJ(1)
VmADJ(2)
VMRAJn 1STEP (Wide range)
24
VMFAJn 1STEP
(Narrow range)
%
2.2 to 5.5
1
4
8
range
Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-2: See Tables 1 and 2 for the oscillation constants.
No.A0965-14/25
LC877696B/80B/64B/48B
Electrical Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ max
unit
DD
High level input
current
I
(1)
IH
• Ports 0, 1, 3, 7, 8
• Ports A, B, C, D
• Port L
• Output disabled
• Pull-up resistor off
• V =V (including output Tr's
1.7 to 5.5
1
IN DD
off leakage current)
I
I
(2)
IH
V
=V
RES
1.7 to 5.5
1.7 to 5.5
1
1
IN DD
(3)
IH
XT1, XT2
• When configured as input ports
• V =V
IN DD
I
I
(4)
IH
CF1
V
=V
IN DD
1.7 to 5.5
4.5 to 5.5
1.7 to 4.5
15
15
10
(5)
IH
Port 87 small signal
input side
V =VBIS+0.5V
IN
4.2
8.5
(VBIS denotes bias voltage)
1.5
5.5
μA
Low level input
current
I
(1)
IL
• Ports 0, 1, 3, 7, 8
• Ports A, B, C, D
• Port L
• Output disabled
• Pull-up resistor off
1.7 to 5.5
-1
• V =V
(including output Tr's
off leakage current)
IN SS
I
I
(2)
IL
V
=V
RES
1.7 to 5.5
1.7 to 5.5
-1
-1
IN SS
(3)
IL
XT1, XT2
• When configured as input ports
• V =V
IN SS
IIL(4)
(5)
CF1
V
=V
IN SS
1.7 to 5.5
4.5 to 5.5
1.7 to 4.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5-5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
-15
-15
-10
-1
I
Port 87 small signal
input side
V
=VBIS-0.5V
IN
-8.5
-5.5
-4.2
-1.5
IL
(VBIS denotes bias voltage)
High level output
voltage
V
V
V
V
V
V
V
V
V
V
V
V
(1)
CMOS output ports
0, 1
I
I
I
I
I
I
I
I
I
I
I
I
=-1mA
V
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
DD
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
=-0.4mA
=-0.2mA
=-10mA
=-1.6mA
=-1mA
V
V
V
V
V
V
V
-0.4
-0.4
-1.5
-0.4
-0.4
-0.4
-0.4
-1
DD
DD
DD
DD
DD
DD
CMOS output ports
30, 31
Ports 71 to 73
=-0.4mA
=-0.2mA
=-1mA
DD
V
Ports A, B, C, D
DD
=-0.4mA
=-0.2mA
V
V
-0.4
DD
DD
-0.4
Low level output
voltage
(1)
(2)
(3)
• Ports 0, 1
• Port 3 (PWM4, 5
function output
mode)
=10mA
=1.6mA
=1mA
1.5
0.4
OL
OL
OL
OL
OL
OL
V
V
I
I
3.0 to 5.5
2.2 to 5.5
4.5 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
3.0 to 5.5
2.2 to 5.5
0.4
1.5
0.4
0.4
0.4
0.4
0.4
0.4
V
V
V
V
V
V
V
V
(4)
(5)
(6)
(7)
(8)
(9)
(10)
Port 3
I
I
I
I
I
I
I
=30mA
=5mA
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
(Port function output
mode)
=2.5mA
=1.6mA
=1mA
• Ports 7, 8
• XT2
Ports A, B, C, D
=1.6mA
OH
=1mA
OL
LCD output
VODLS
S0 to S31
• I =0mA
O
voltage deviation
• VLCD, 2/3VLCD
1/3VLCD level output
• See Fig. 8.
2.2 to 5.5
0
0
±0.2
±0.2
VODLC
COM0 to COM3
• I =0mA
O
• VLCD, 2/3VLCD
1/2VLCD, 1/3VLCD level output
• See Fig. 8.
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
LCD bias resistor
RLCD(1)
RLCD(2)
Resistance per
one bias resister
• Resistance per
one bias resister
• 1/2 resistance
mode
See Fig. 8.
60
30
See Fig. 8.
kΩ
Continued on next page.
No.A0965-15/25
LC877696B/80B/64B/48B
Continued from preceding page.
Specification
typ max
35
Parameter
Symbol
Pin/Remarks
Conditions
DD
V
[V]
min
15
unit
DD
Pull-up MOS Tr.
resistance
Rpu(1)
Rpu(2)
VHYS(1)
• Ports 0, 1, 3, 7
• Ports A, B, C, D
V
=0.9V
4.5 to 5.5
2.2 to 4.5
80
OH
kΩ
18
50
150
Hysteresis voltage
Pin capacitance
Input sensitivity
• Ports 1, 7
2.2 to 5.5
2.2 to 5.5
0.1V
0.1V
DD
•
RES
V
VHYS(2)
CP
Port 87 small signal
input side
DD
10
All pins
• V =V
IN SS
for pins other than
that under test
• f=1MHz
1.7 to 5.5
2.2 to 5.5
pF
• Ta=25°C
Vsen
Port 87 small signal
input side
0.12V
Vp-p
DD
Serial I/O Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS
SS
SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Parameter
Frequency
Symbol
tSCK(1)
Pin/Remarks
SCK0(P12)
Conditions
See Fig. 6.
V
[V]
min
typ
max
unit
DD
2
1
1
Low level
tSCKL(1)
tSCKH(1)
tSCKHA(1)
pulse width
High level
pulse width
2.2 to 5.5
tCYC
• Continuous data
transmission/reception mode
• See Fig. 6.
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
• See Fig. 6.
4/3
Low level
tSCKL(2)
tSCKH(2)
tSCKHA(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
tCYC
2.2 to 5.5
• Continuous data
transmission/reception mode
• CMOS output selected
• See Fig. 6.
tSCKH(2)
+(10/3)
tCYC
tSCKH(2)
+2tCYC
Data setup time
Data hold time
tsDI(1)
SB0(P11),
SI0(P11)
• Must be specified with
respect to rising edge of
SIOCLK
0.03
0.03
2.2 to 5.5
• See Fig. 6.
thDI(1)
tdDO(1)
tdDO(2)
tdDO(3)
Output delay
time
SO0(P10),
SB0(P11)
• Continuous data
(
1/3)tCYC
+0.05
transmission/reception mode
• (Note 4-1-3)
μs
• Synchronous 8-bit mode
• (Note 4-1-3)
1tCYC
+0.05
2.2 to 5.5
(Note 4-1-3)
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous transmission/reception mode, a time from SI0RUN being set when
serial clock is "H" to the first falling edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning
of output state change in open drain output mode. See Fig. 6.
No.A0965-16/25
LC877696B/80B/64B/48B
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Parameter
Frequency
Symbol
tSCK(3)
Pin/Remarks
SCK1(P15)
Conditions
V
[V]
min
typ
max
unit
DD
See Fig.6.
2
1
1
2
Low level
tSCKL(3)
tSCKH(3)
tSCK(4)
tSCKL(4)
tSCKH(4)
tsDI(2)
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
pulse width
High level
pulse width
Frequency
tCYC
SCK1(P15)
• CMOS output selected
• See Fig. 6.
Low level
pulse width
1/2
1/2
tSCK
High level
pulse width
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6.
0.03
0.03
Data hold time
thDI(2)
μs
Output delay
time
tdDO(4)
SO1(P13),
SB1(P14)
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the time to
the beginning of output state
change in open drain output
mode.
(1/3)tCYC
+0.05
2.2 to 5.5
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -40°C to +85°C, V 1 = V 2 = V 3 = 0V
SS SS SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ
max
unit
DD
High/low level
pulse width
tPIH(1)
tPIL(1)
INT0(P70),
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
INT1(P71),
1.7 to 5.5
1.7 to 5.5
1.7 to 5.5
1
INT2(P72)
tPIH(2)
tPIL(2)
INT3(P73) when
noise filter time
constant is 1/1
INT3(P73) when
noise filter time
constant is 1/32
INT3(P73) when
noise filter time
constant is 1/128
MICIN(P87)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
2
tPIH(3)
tPIL(3)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
tCYC
64
tPIH(4)
tPIL(4)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
1.7 to 5.5
1.7 to 5.5
256
1
tPIH(5)
tPIL(5)
tPIH(6)
tPIL(6)
The pulses can be counted by the
small signal sensor/counter.
The pulses can be recognized as
signals by the infrared remote
control receiver circuit.
RMIN(P73)
RMCK
2.2 to 5.5
1.7 to 5.5
3
(Note5-1)
RES
tPIL(7)
Resetting is enabled.
2000
μs
Note 5-1: RMCK denotes the frequency of the base clock (1tCYC to 128tCYC/subclock source oscillation frequency) for the
infrared remote control receiver circuit
No.A0965-17/25
LC877696B/80B/64B/48B
AD Converter Characteristics at V 1 = V 2 = 0V
SS SS
<12-bit AD conversion mode at Ta = -30°C to +85°C> (To be determined after evaluation)
Specification
typ max
12
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
unit
bit
DD
Resolution
N
AN0(P80)
3.0 to 5.5
3.0 to 5.5
4.0 to 5.5
3.0 to 5.5
3.0 to 5.5
to AN7(P87),
AN8(P70),
AN9(P71),
AN10(XT1)
AN11(XT2)
Absolute
accuracy
ET
(Note 6-1)
16
115
115
LSB
(Note 6-1) Ta=-10 to 50°C
32
Conversion
time
TCAD
See "Conversion time calculation
method". (Note 6-2)
64
V
V
SS
DD
μs
See "Conversion time calculation
method". (Note 6-2)
3.0 to 5.5
1
Ta=-10 to 50°C
Analog input
voltage range
Analog port
input current
VAIN
3.0 to 5.5
3.0 to 5.5
-1
-1
V
IAINH
IAINL
VAIN=V
DD
12
μA
VAIN=V
SS
<8-bit AD conversion mode at Ta =-30 to +85°C>
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
typ
max
unit
bit
DD
Resolution
N
AN0(P10) to
2.0 to 5.5
3.0 to 5.5
2.0 to 5.5
4.0 to 5.5
3.0 to 5.5
8
AN7(P17),
Absolute
accuracy
ET(1)
Specified with tCAD(1) (Note 6-1)
Specified with tCAD(2) (Note 6-1)
±1.5
±4.0
90
LSB
AN8(P70),
ET(2)
AN9(Internal
reference voltage)
Conversion
time
tCAD(1)
See "Conversion time calculation
method". (Note 6-2)
20
μs
40
90
tCAD(2)
VAIN
Ta=-10 to +55°C
See "Conversion time calculation
method". (Note 6-2)
2.0 to 5.5
7.48
7.66
7.66
8.26
8.26
ms
See "Conversion time calculation
method". (Note 6-2)
3.0 to 5.5
2.0 to 5.5
7.48
Analog input
voltage range
Analog port
input current
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
2.0 to 5.5
2.0 to 5.5
1
μA
VAIN=V
SS
-1
<Conversion time calculation method>
12-bit AD conversion mode: TCAD (conversion time) = ((52/(division ratio)) + 2) × (1/3)×tCYC
8-bit AD conversion mode: TCAD (conversion time) = ((32/(division ratio)) + 2) × (1/3)×tCYC
<Recommended Operating Conditions>
Conversion Time (TCAD)
External
oscillator
Supply Voltage
Range
System Clock
Division
AD Frequency
Division Ratio
(ADDIV)
Cycle Time
tCYC
12-bit AD
8-bit AD
FmCF[MHz]
V
[V]
(SYSDIV)
DD
4.0 to 5.5
3.0 to 5.5
2.0 to 5.5
3.0 to 5.5
1/1
1/1
1/1
1/1
250ns
250ns
91.5μs
250μs
1/8
1/16
1/8
34.8μs
21.5μs
42.8μs
7.86ms
7.86ms
12MHz
69.5μs
-
-
32.768kHz
1/8
Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value. The absolute accuracy refers
to the accuracy that is measured while there is no change in the I/O state of the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the time the complete digital-conversion-value corresponding to the analog input value is loaded in the
required register.
The conversion time becomes twice the normal value in the following cases:
• The AD conversion is carried out in the 12-bit AD conversion mode for the first time after a system reset.
• The AD conversion is carried out for the first time after the AD conversion mode is switched from 8-bit to
12-bit AD conversion mode.
No.A0965-18/25
LC877696B/80B/64B/48B
Consumption Current Characteristics at Ta = -20°C to +70°C, V 1 = V 2 = V 3 = 0V
SS SS SS
(To be determined after evaluation)
Specification
typ max
Pin/Rema
Parameter
Symbol
Conditions
rks
1
V
[V]
min
unit
DD
Normal mode
consumption
current
IDDOP(1)
V
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side
• Internal RC oscillation stopped
DD
=V
=V
2
4.5 to 5.5
3.0 to 3.6
8.0
17.2
9.8
DD
DD
3
(Note 7-1)
IDDOP(2)
• Multifrequency RC oscillation stopped
• 1/1 frequency division ratio
4.1
IDDOP(3)
IDDOP(4)
IDDOP(5)
IDDOP(6)
IDDOP(7)
IDDOP(8)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
4.5 to 5.5
3.0 to 3.6
2.5 to 3.0
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
5.5
2.8
2.3
3.0
1.5
1.2
12.6
7.1
5.7
7.2
3.8
3.0
• Internal RC oscillation stopped
• Multifrequency RC oscillation stopped
• 1/1 frequency division ratio
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped
• Multifrequency RC oscillation stopped
• 1/2 frequency division ratio
mA
IDDOP(9)
IDDOP(10)
IDDOP(11)
IDDOP(12)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• Multifrequency RC oscillation stopped
• 1/2 frequency division ratio
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
0.6
0.3
0.2
1.5
0.7
0.6
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped
• System clock set to 10MHz multifrequency
RC oscillation
4.5 to 5.5
3.0 to 3.6
6.9
1.4
15.8
8.3
IDDOP(13)
• 1/1 frequency division ratio
IDDOP(14)
IDDOP(15)
IDDOP(16)
IDDOP(17)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped
• System clock set to 4MHz multifrequency
RC oscillation
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
4.5 to 5.5
3.4
1.4
7.2
5.0
1.1
4.1
• 1/1 frequency division ratio
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
27.6
126.3
IDDOP(18)
IDDOP(19)
μA
3.0 to 3.6
1.7 to 3.0
9.2
6.9
74.2
63.8
• Multifrequency RC oscillation stopped
• 1/2 frequency division ratio
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A0965-19/25
LC877696B/80B/64B/48B
Continued from preceding page.
Specification
typ max
Pin/
Parameter
Symbol
Conditions
Remarks
unit
V
[V]
min
DD
HALT mode
consumption
current
IDDHALT(1)
V
1
HALT mode
DD
=V
=V
2
3
• FmCF=12MHz ceramic oscillation
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 12MHz side.
• Internal RC oscillation stopped
• Multifrequency RC oscillation stopped
• 1/1 frequency division ratio
DD
DD
4.5 to 5.5
3.0 to 3.6
2.7
6.2
(Note 7-1)
IDDHALT(2)
IDDHALT(3)
1.2
3.2
HALT mode
4.5 to 5.5
3.0 to 3.6
2.5 to 3.0
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
2.0
0.9
0.7
1.2
0.5
0.4
12.6
7.1
5.7
3.3
1.5
1.1
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
• Multifrequency RC oscillation stopped
• 1/1 frequency division ratio
IDDHALT(4)
IDDHALT(5)
IDDHALT(6)
IDDHALT(7)
IDDHALT(8)
HALT mode
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped
• Multifrequency RC oscillation stopped
• 1/2 frequency division ratio
mA
IDDHALT(9)
IDDHALT(10)
IDDHALT(11)
IDDHALT(12)
HALT mode
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
0.3
0.13
0.10
0.8
0.4
0.3
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
• Multifrequency RC oscillation stopped
• 1/2 frequency division ratio
HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped
• System clock set to 10MHz multifrequency
RC oscillation
4.5 to 5.5
3.0 to 3.6
2.6
1.2
6.0
3.1
IDDHALT(13)
• 1/1 frequency division ratio
HALT mode
IDDHALT(14)
IDDHALT(15)
IDDHALT(16)
IDDHALT(17)
IDDHALT(18)
IDDHALT(19)
4.5 to 5.5
3.0 to 3.6
2.2 to 3.0
4.5 to 5.5
3.0 to 3.6
1.7 to 3.0
1.3
0.6
3.1
1.5
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped
• System clock set to 4MHz multifrequency RC
oscillation
0.5
1.2
• 1/1 frequency division ratio
HALT mode
20.2
5.1
114.6
67.1
57.9
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
• Multifrequency RC oscillation stopped
• 1/2 frequency division ratio
HOLD mode
3.5
μA
HOLD mode
consumption
current
IDDHOLD(1)
IDDHOLD(2)
IDDHOLD(3)
IDDHOLD(4)
V
V
1
4.5 to 5.5
3.0 to 3.6
1.7 to 3.0
4.5 to 5.5
0.14
0.03
0.03
17.5
35
28
DD
• CF1=V
DD
or open
(external clock mode)
26
Clock
1
Clock HOLD mode
125.3
DD
HOLD mode
consumption
current
• CF1=V or open
DD
(external clock mode)
IDDHOLD(5)
IDDHOLD(6)
3.0 to 3.6
1.7 to 3.0
3.8
2.4
60
50
• FmX’tal=32.768kHz crystal oscillation mode
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
No.A0965-20/25
LC877696B/80B/64B/48B
UART (Full Duplex) Operating Conditions at Ta = -20 to +70°C, V 1 = V 2 = V 3 = 0V
SS
SS
Specification
SS
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
min
16/3
typ
max
unit
DD
Transfer rate
UBR
UTX(P00),
URX(P01)
2.2 to 5.5
8192/3
tCYC
Data length: 7/8/9 bits (LSB first)
Stop bits: 1 bit (2-bit in continuous data transmission mode)
Parity bits: None
Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H)
Start bit
Stop bit
End of
transmission
Start of
transmission
Transmit data (LSB first)
UBR
Example of 8-bit Data Reception Mode Processing (Receive Data=55H)
Stop bit
Start bit
End of
reception
Start of
reception
Receive data (LSB first)
UBR
* When using UART, set P0LDDR (P0DDR: BIT0) to “0”
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Vendor
Name
Stabilization Time
Oscillator Name
Remarks
Frequency
C1
C2
Rf1
Rd1
typ
max
[ms]
[pF]
[pF]
[Ω]
[Ω]
[ms]
Built-in
C1, C2
12MHz
8MHz
MURATA
MURATA
CSTCE120G52-R0
(10)
(10)
OPEN
330
3.0 to 5.5
0.05
0.15
CSTLS8M00G53-B0
CSTCE8M00G52-R0
CSTLS4M00G53-B0
CSTCR4M00G53-R0
(15)
(10)
(15)
(15)
(15)
(10)
(15)
(15)
OPEN
OPEN
OPEN
OPEN
680
330
1.5k
1k
2.5 to 5.5
2.5 to 5.5
2.2 to 5.5
2.5 to 5.5
0.05
0.05
0.05
0.05
0.15
0.15
0.15
0.15
Built-in
C1, C2
Built-in
C1, C2
4MHz
MURATA
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after V
goes above the operating voltage lower limit (see Figure 4).
DD
No.A0965-21/25
LC877696B/80B/64B/48B
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Oscillation
Circuit Constant
Operating
Voltage Range
[V]
Nominal
Oscillator
Name
Stabilization Time
Vendor Name
Remarks
Frequency
C3
C4
Rf2
Rd2
typ
[s]
max
[s]
[pF]
[pF]
[Ω]
[Ω]
32.768kHz
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Caution: The components that are involved in oscillation should be placed as close to the IC and to one another as
possible because they are vulnerable to the influences of the circuit pattern.
XT1
XT2
CF1
CF2
Rf2
Rf1
Rd2
C4
Rd1
C2
C3
C1
X’tal
CF
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5V
DD
Figure 3 AC Timing Measurement Point
No.A0965-22/25
LC877696B/80B/64B/48B
V
DD
Operating V
lower limit
0V
DD
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
absent
HOLD reset signal
HOLD release signal VALID
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A0965-23/25
LC877696B/80B/64B/48B
V
DD
R
C
Note:
RES
Determine the value of C
and R so that the reset
RES
RES
signal is present for a period of 200μs after the supply
voltage goes beyond the lower limit of the IC's operating
voltage.
RES
RES
Figure 5 Reset Circuit
SIOCLK:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAIN:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
thDI
tSCKL
SIOCLK:
DATAIN:
tsDI
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK:
DATAIN:
tsDI
thDI
tdDO
DATAOUT:
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A0965-24/25
LC877696B/80B/64B/48B
V
DD
SW : ON/OFF (programmable)
RLCD
RLCD
RLCD
RLCD
SW: ON when VLCD=V
DD
VLCD
RLCD
RLCD
2/3VLCD
1/2VLCD
RLCD
RLCD
1/3VLCD
RLCD
RLCD
GND
Figure 8 LCD Bias Resistors
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of September, 2007. Specifications and information herein are subject
to change without notice.
No.A0965-25/25
PS
相关型号：
ENA0967
Bi-CMOS LSI PWM Constant-Current Control Stepping Motor Driver and Switching Regulator Controller
SANYO
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