SGM6061 [SGMICRO]

55V, 1.5A High Frequency Buck Converter;
SGM6061
型号: SGM6061
厂家: Shengbang Microelectronics Co, Ltd    Shengbang Microelectronics Co, Ltd
描述:

55V, 1.5A High Frequency Buck Converter

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SGM6061  
55V, 1.5A High Frequency Buck Converter  
GENERAL DESCRIPTION  
FEATURES  
The SGM6061 is a high voltage and high frequency  
Buck converter with 1.5A maximum output current and  
integrated high-side power MOSFET. It implements  
peak current mode control to simplify external  
compensation design.  
Input Voltage Range: 3.8V to 55V  
Adjustable Output Range: 0.8V to 24V  
Up to 95% Efficiency  
PFM Mode at Light Loads  
Quiescent Current: 131μA (TYP)  
Less than 18μA Shutdown Current  
Internal HS Power MOSFET RDSON: 250(TYP)  
Adjustable Switching Frequency: up to 2MHz  
Adjustable Soft-Start Time  
With a wide input voltage range of 3.8V to 55V, it is  
suitable for a broad range of applications such as  
industry equipment.  
The SGM6061 operates at fixed frequency and enters  
PFM (Pulse Frequency Modulation) mode automatically  
at light load to maintain high efficiency. During startup  
and thermal shutdown, the frequency foldback  
technique is used to avoid inductor current runaway for  
reliable and fault tolerant operation. The current limit  
foldback technique is used for reducing power  
consumption during output shorted and suppressing  
output voltage overshot during recovery.  
Accurate EN Input Threshold  
Stable with Ceramic Capacitor  
Available in a Green TDFN-3×3-10L Package  
APPLICATIONS  
Industrial and Commercial Power Systems  
Distributed Power Systems  
Aftermarket Automotive Accessories  
Switching frequency can be set as high as 2MHz. It  
minimizes the EMI noise issues that could interfere with  
nearby systems such as AM radio or ADSL modems.  
The SGM6061 is available in a Green TDFN-3×3-10L  
package. It operates over a junction temperature range  
of -40to +125.  
TYPICAL APPLICATION  
C4  
10  
VIN  
L1  
VOUT  
1
2
9
BOOT  
VIN  
SW  
SW  
D1  
R5  
R1  
C7  
SGM6061  
3
8
7
5
4
EN  
SS  
FB  
C1  
C2  
C3  
C9  
C10  
FREQ  
GND COMP  
6
R2  
C8  
R3  
R6  
R4  
C5  
C6  
Figure 1. Typical Application Circuit  
SG Micro Corp  
MARCH2022REV. A  
www.sg-micro.com  
SGM6061  
55V, 1.5A High Frequency Buck Converter  
PACKAGE/ORDERING INFORMATION  
SPECIFIED  
TEMPERATURE  
RANGE  
PACKAGE  
DESCRIPTION  
ORDERING  
NUMBER  
PACKAGE  
MARKING  
PACKING  
OPTION  
MODEL  
SGM  
6061D  
XXXXX  
SGM6061  
TDFN-3×3-10L  
SGM6061XTD10G/TR  
Tape and Reel, 4000  
-40to +125℃  
MARKING INFORMATION  
NOTE: XXXXX = Date Code, Trace Code and Vendor Code.  
X X X X X  
Vendor Code  
Trace Code  
Date Code - Year  
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If  
you have additional comments or questions, please contact your SGMICRO representative directly.  
ABSOLUTE MAXIMUM RATINGS  
OVERSTRESS CAUTION  
Supply Voltage Range, VIN ................................ -0.3V to 60V  
Switch Voltage Range, VSW ......................-0.5V to VIN + 0.5V  
BOOT to SW........................................................ -0.3V to 5V  
EN Pin Voltage Range, VEN ......................-0.3V to VIN + 0.3V  
All Other Pins....................................................... -0.3V to 5V  
Package Thermal Resistance  
Stresses beyond those listed in Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to  
absolute maximum rating conditions for extended periods  
may affect reliability. Functional operation of the device at any  
conditions beyond those indicated in the Recommended  
Operating Conditions section is not implied.  
TDFN-3×3-10L, θJA.................................................... 64/W  
Junction Temperature.................................................+150℃  
Storage Temperature Range.......................-65to +150℃  
Lead Temperature (Soldering, 10s)............................+260℃  
ESD Susceptibility  
ESD SENSITIVITY CAUTION  
This integrated circuit can be damaged if ESD protections are  
not considered carefully. SGMICRO recommends that all  
integrated circuits be handled with appropriate precautions.  
Failureto observe proper handlingand installation procedures  
can cause damage. ESD damage can range from subtle  
performance degradation tocomplete device failure. Precision  
integrated circuits may be more susceptible to damage  
because even small parametric changes could cause the  
device not to meet the published specifications.  
HBM.............................................................................4000V  
CDM ............................................................................1000V  
RECOMMENDED OPERATING CONDITIONS  
Supply Voltage Range, VIN ..................................3.8V to 55V  
Output Voltage Range, VOUT................................0.8V to 24V  
Operating Junction Temperature Range......-40to +125℃  
DISCLAIMER  
SG Micro Corp reserves the right to make any change in  
circuit design, or specifications without prior notice.  
SG Micro Corp  
www.sg-micro.com  
MARCH 2022  
2
SGM6061  
55V, 1.5A High Frequency Buck Converter  
PIN CONFIGURATION  
(TOP VIEW)  
SW  
SW  
1
2
3
4
5
10 BOOT  
9
8
7
6
VIN  
EN  
GND  
SS  
COMP  
FB  
FREQ  
GND  
TDFN-3×3-10L  
PIN DESCRIPTION  
PIN  
NAME  
FUNCTION  
1, 2  
SW  
Switching Node of the Converter.  
Active High Enable Input Pin. It has a weak internal pull-up current source. Pull it below 1.12V to  
disable the device. Leave EN floating when unused. When EN is directly connected to VIN or  
external signal source, a resistor greater than 10kΩ is necessary.  
3
EN  
Transconductance Error Amplifier Output. Use a compensation network between COMP and  
GND pins to compensate the internal loop.  
4
5
COMP  
FB  
Inverting Input of the Error Amplifier.  
Ground Pin.  
6
GND  
FREQ  
SS  
Switching Frequency Adjustment Pin. Connect an external resistor between FREQ and GND pins  
to adjust the switching frequency.  
Soft-Start Time Adjustment Pin. Connect an external capacitor between SS and GND pins to  
adjust the output ramp-up time.  
7
8
9
VIN  
Power Supply Input Pin.  
Power supply of the internal MOSFET gate driver. Connect a 0.1µF bootstrap capacitor between  
BOOT and SW pins.  
10  
BOOT  
Exposed Pad Exposed Pad. It should be soldered to the ground plane for enhanced heat dissipation.  
SG Micro Corp  
www.sg-micro.com  
MARCH 2022  
3
SGM6061  
55V, 1.5A High Frequency Buck Converter  
ELECTRICAL CHARACTERISTICS  
(VIN = 12V, VEN = 2V, TJ = +25, unless otherwise noted.)  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
0.786  
0.784  
TYP  
MAX  
0.820  
0.822  
315  
UNITS  
VIN = 12V  
0.803  
Feedback Voltage  
VFB  
V
TA = -40to +85℃  
VBOOT - VSW = 5V  
250  
Switch On-Resistance  
RDSON  
mΩ  
400  
TA = -40to +85℃  
VEN = 0V, VSW = 0V  
Switch Leakage Current  
ILKG  
ILIM  
1
μA  
A
Current Limit  
1.95  
2.55  
4.5  
3.15  
COMP to Sensed Current Transconductance  
Error Amplifier Voltage Gain (1)  
Error Amplifier Transconductance  
Error Amplifier Source Current  
Error Amplifier Sink Current  
GCS  
A/V  
dB  
AEA  
80  
GEA  
ICOMP = ±3µA  
120  
8.8  
µA/V  
µA  
ISOURCE  
ISINK  
VFB = 0.7V, VCOMP = 1V  
VFB = 0.9V, VCOMP = 1V  
-8.6  
3.14  
µA  
2.85  
2.7  
3.45  
3.6  
VIN Under-Voltage Lockout Threshold (UVLO)  
VUVLO  
V
TA = -40to +85℃  
VIN Under-Voltage Lockout Hysteresis  
Soft-Start Time (1)  
VHYS  
tSS  
0.59  
1.6  
V
Timing from EN available, C5 = 10nF  
VSS = 0V  
ms  
µA  
Soft-Start Current  
ISS  
4.9  
R4 = 89kΩ  
0.85  
0.82  
1.00  
1.15  
1.16  
18  
Switching Frequency  
fSW  
MHz  
TA = -40to +85℃  
VIN = 12V, VEN < 0.2V  
No Load, VFB = 0.86V  
Hysteresis = +20℃  
Shutdown Supply Current  
Quiescent Supply Current  
Thermal Shutdown Temperature  
Minimum Off Time (1)  
ISD  
IQ  
12.7  
131  
155  
100  
110  
1.58  
µA  
µA  
TSD  
tOFF_MIN  
tON_MIN  
ns  
ns  
Minimum On Time (1)  
1.40  
1.35  
1.75  
1.8  
EN Rising Threshold  
VENR  
V
TA = -40to +85℃  
EN Threshold Hysteresis  
VENHYS  
460  
mV  
NOTE: 1. Guaranteed by design.  
SG Micro Corp  
www.sg-micro.com  
MARCH 2022  
4
SGM6061  
55V, 1.5A High Frequency Buck Converter  
TYPICAL PERFORMANCE CHARACTERISTICS  
At TA = +25, VIN = 12V, VOUT = 3.3V, CIN = 10μF, COUT = 22μF, L1 = 10μH (DCR = 12mΩ), unless otherwise noted.  
Startup  
Shutdown  
ILOAD = 0.1A  
ILOAD = 0.75A  
ILOAD = 1.5A  
ILOAD = 0.1A, C5 = 10nF  
VEN  
VEN  
VOUT  
VOUT  
VSW  
VSW  
IL  
IL  
Time (2ms/div)  
Startup  
Time (1ms/div)  
Shutdown  
ILOAD = 0.75A, C5 = 10nF  
VEN  
VEN  
VOUT  
VOUT  
VSW  
IL  
VSW  
IL  
Time (2ms/div)  
Startup  
Time (200μs/div)  
Shutdown  
ILOAD = 1.5A, C5 = 10nF  
VEN  
VEN  
VOUT  
VOUT  
VSW  
VSW  
IL  
IL  
Time (2ms/div)  
Time (200μs/div)  
SG Micro Corp  
www.sg-micro.com  
MARCH 2022  
5
SGM6061  
55V, 1.5A High Frequency Buck Converter  
TYPICAL PERFORMANCE CHARACTERISTICS (continued)  
At TA = +25, VIN = 12V, VOUT = 3.3V, CIN = 10μF, COUT = 22μF, L1 = 10μH (DCR = 12mΩ), unless otherwise noted.  
Output Ripple  
Short-Circuit Entry  
ILOAD = 0.1A to short  
ILOAD = 0.1A  
AC Coupled  
VOUT  
VOUT  
VSW  
VSW  
IL  
IL  
Time (1μs/div)  
Time (500μs/div)  
Output Ripple  
Short-Circuit Recovery  
ILOAD = 0.75A  
AC Coupled  
ILOAD = short to 0.1A  
VOUT  
VOUT  
VSW  
VSW  
IL  
IL  
Time (1μs/div)  
Time (500μs/div)  
Output Ripple  
Short-Circuit Steady State  
ILOAD = 1.5A  
AC Coupled  
VOUT  
VOUT  
VSW  
VSW  
IL  
IL  
Time (1μs/div)  
Time (20μs/div)  
SG Micro Corp  
www.sg-micro.com  
MARCH 2022  
6
SGM6061  
55V, 1.5A High Frequency Buck Converter  
TYPICAL PERFORMANCE CHARACTERISTICS (continued)  
At TA = +25, VIN = 12V, VOUT = 3.3V, CIN = 10μF, COUT = 22μF, L1 = 10μH (DCR = 12mΩ), unless otherwise noted.  
Efficiency vs. Output Current  
Efficiency vs. Output Current  
100  
90  
80  
70  
60  
50  
40  
100  
90  
80  
70  
60  
50  
40  
VIN = 12V  
IN = 55V  
V
VIN = 12V  
IN = 55V  
V
VOUT = 3.3V, L1 = 10μH, fSW = 500kHz  
VOUT = 5V, L1 = 15μH, fSW = 500kHz  
0
0.3  
0.6  
0.9  
1.2  
1.5  
0
0.3  
0.6  
0.9  
1.2  
1.5  
Output Current (A)  
Output Current (A)  
Efficiency vs. Output Current  
RT Resistance vs. Oscillator Frequency  
100  
90  
80  
70  
60  
50  
40  
500  
400  
300  
200  
100  
0
VIN = 24V  
IN = 55V  
V
VOUT = 12V, L1 = 22μH, fSW = 500kHz  
IOUT = 1A  
200  
0
0.3  
0.6  
0.9  
1.2  
1.5  
600  
1000  
1400  
1800  
2200  
Output Current (A)  
Oscillator Frequency (kHz)  
SG Micro Corp  
www.sg-micro.com  
MARCH 2022  
7
SGM6061  
55V, 1.5A High Frequency Buck Converter  
FUNCTIONAL BLOCK DIAGRAM  
VIN  
VDD  
1μA  
BOOT  
Charger  
VDD  
Reference  
EN  
Internal  
Regulators  
BOOT  
UVLO  
_
ISW  
Logic  
+
VDD  
Current  
Limit  
SW  
5μA  
_
FB  
SS  
COMP  
Oscillator  
Slope  
Compensation  
+
0.8V  
COMP  
GND  
FREQ  
Figure 2. SGM6061 Functional Block Diagram  
DETAILED DESCRIPTION  
Overview  
Internal 2.6V Regulator  
The SGM6061 is a 3.8V to 55V, 1.5A non-synchronous  
Buck converter with integrated high-side N-channel  
MOSFET. It is a perfect solution for efficient single  
stage Buck applications. The integrated functions  
include precision current limiting, automatically  
switched PWM and PFM modes, adjustable soft-start  
ramp time and wide range switching frequency, which  
can meet different requirements. Peak current mode  
control is implemented to provide fast load transient  
response and simple compensation.  
An internal 2.6V regulator powers most of the device  
internal circuits. The 2.6V output is fully regulated when  
VIN exceeds 3.14V. It will drop if VIN falls below 3.14V.  
Enable Input  
The EN pin is an active high input to enable or disable  
the device. The EN rising threshold voltage VENR is  
1.58V (TYP) and has a 460mV (TYP) hysteresis.  
A 1μA internal current source pulls the EN pin up to  
approximately 3.0V. Therefore the device will be  
enabled when the EN pin is left floating. To disable the  
device, pull the EN pin down below 1.12V with at least  
1µA sink capability.  
VIN Under-Voltage Lockout (UVLO)  
The SGM6061 integrates VIN under-voltage lockout  
(UVLO) feature to protect the device from  
malfunctioning when the input voltage is insufficient to  
properly power up the internal circuits. The UVLO rising  
threshold is 3.14V (TYP) and has a 0.59V (TYP)  
hysteresis.  
SG Micro Corp  
www.sg-micro.com  
MARCH 2022  
8
SGM6061  
55V, 1.5A High Frequency Buck Converter  
DETAILED DESCRIPTION (continued)  
When VEN falls below 1.12V, the device is disabled and  
enters low shutdown current mode. When VEN exceeds  
0V and does not reach VENR, the device is still disabled  
but with slightly higher shutdown current.  
40  
35  
30  
25  
20  
15  
10  
5
Startup and Shutdown  
If both VIN and VEN exceed their thresholds, the device  
is enabled and starts operation. First, the bandgap  
circuit starts working to generate stable reference  
voltage and bias current. Then two internal regulators  
are established to provide supply voltage for internal  
analog and digital circuit respectively. About 30µs later,  
bootstrap capacitor voltage is charged above UVLO  
threshold. Then SS output starts to rise at the rate set  
by C5.  
0
5
25 45 65 85 105 125 145 165 185 205  
SS Capacitance (nF)  
220  
Figure 3. Recommended SS Time vs. SS Capacitance  
The device is disabled when any of invalid EN voltage,  
VIN UVLO and thermal shutdown events occurs. Once  
the device is disabled, the high-side switch is turned off  
immediately to avoid any other fault triggering.  
Figure 3 shows the soft-start time with a wide range of  
external soft-start capacitance values. The recommended  
soft-start capacitance range is from 5.6nF to 220nF.  
Soft-Start and Ramp  
PWM Operation Mode  
Every time the device is enabled (after power-up,  
pulling EN high or a fault recovery), the output voltage  
is gradually increased to its regulation value with a  
ramp (after a brief 50µs hold). Soft-start is needed to  
prevent triggering of current limit or short-circuit  
protections or to avoid output overshooting during  
startup. Without a soft-start, the inrush currents of the  
output capacitors or the load can cause over-current  
and the protection procedure results in non-monotonic  
startup or even instability. Overshooting may also occur  
during startup after short-circuit recovery. The internal  
soft-start voltage (VSS) is almost 0.2V higher than FB  
voltage (VFB). The VSS and reference (VREF) are both  
sent to the error amplifier and the lower value of them is  
the actual reference that is compared with the feedback  
voltage (VFB).  
In the moderate to heavy load conditions, the  
SGM6061 runs at fixed frequency with peak current  
control mode. The high-side MOSFET is turned on at  
the leading edge of internal clock until the sensing  
current ramp signal reaches the COMP voltage. If the  
switch current does not reach the reference value  
(conversion from VC) in a cycle, the switch will also be  
turned off for tOFF_MIN (100ns, TYP) before the next  
clock.  
PFM Mode  
In the light load condition, the frequency is reduced  
depending on the load to minimize the switching and  
gate driving losses and keep the efficiency high.  
PWM Comparator and Current Limit  
For peak current mode, a signal represent of high-side  
current is used as the input of PWM comparator, which  
is accurately sampled by internal sensing circuit. After  
100ns typical blanking time, the signal is compared with  
COMP to determine switching state of high-side  
MOSFET. The cycle-by-cycle current limit threshold is  
approximately 2.55A.  
A 4.9μA pull-up current source is internally connected  
to the SS pin. The soft-start time (tSS) is the time  
interval that the external soft-start capacitor (C5)  
voltage increases by 0.8V. Therefore, the soft-start time  
can be calculated from:  
C5(μF)×0.8V  
tSS (ms) =  
(1)  
ISS  
Note that the measured peak current limits in the  
closed-loop and open-loop test conditions are slightly  
different, mainly caused by the propagation delay.  
SG Micro Corp  
www.sg-micro.com  
MARCH 2022  
9
 
SGM6061  
55V, 1.5A High Frequency Buck Converter  
DETAILED DESCRIPTION (continued)  
A 5V rail is available.  
VIN is less than 5V.  
VOUT is between 3.3V and 5V.  
High duty cycle applications (VOUT/VIN > 65%).  
Bootstrap Floating MOSFET Driver  
The power of the high-side MOSFET driver is provided  
by an external capacitor between BOOT and SW pins.  
An internal bootstrap regulator keeps the bootstrap  
capacitor charged and regulated to approximately 4.5V.  
A low-cost diode like IN4148 or BAT54 can be used.  
The bootstrap voltage is detected by internal BOOT  
UVLO circuit with 2.4V rising threshold and 250mV  
hysteresis. If the bootstrap voltage falls below its UVLO  
threshold, the power MOSFET is turned off immediately.  
An internal transistor is used to pull down the SW node  
to make sure BOOT capacitor is charged sufficiently.  
This design can obviously reduce the output voltage  
ripple at small input/output voltage difference and no  
load. When the bootstrap voltage is charged above  
threshold, the pull-down transistor is turned off and  
high-side MOSFET is able to be turned on again.  
5V  
BOOT  
0.1μF  
SGM6061  
SW  
Figure 4. External Bootstrap Diode  
Adjustable Switching Frequency  
The switching frequency is adjusted by connecting an  
external resistor (R4) between the FREQ and GND.  
Use Equation 3 to calculate R4 resistance:  
Except for BOOT UVLO condition, the external circuit  
connected to the SW serves as the return path to GND  
for the charge current. Enough voltage headroom  
should be left to facilitate the charging. When the  
external freewheeling diode is on, bootstrap charging  
starts until the regulated voltage.  
94581  
(3)  
R4(kΩ) =  
- 7.24  
fSW (kHz)  
For Example, to get 500kHz switching frequency, the  
required R4 resistor is 180kΩ.  
The converter operates in PFM Mode at no load or light  
load, to minimize switching losses and keep the output  
regulated. In this mode, the available time for  
refreshing the BOOT voltage is reduced, bootstrap  
voltage will drop below the regulated voltage (4.5V).  
The maximum charged voltage is equal to VIN - VOUT. If  
the difference of VIN - VOUT is too small, BOOT UVLO  
can be triggered. The internal charging circuit charges  
the bootstrap capacitor by the set frequency, until  
BOOT UVLO is released.  
An internal frequency foldback technique is designed  
by monitoring the FB voltage. It can effectively avoid  
the inductor current runaway during startup or  
restarting in certain situation.  
Error Amplifier (EA)  
The output voltage is sensed by a resistor divider  
through the FB pin and is compared with the internal  
reference. The EA generates an output current that is  
proportional to the voltage difference (error). This  
current is fed into the external compensation network to  
generate the VC voltage on the COMP pin, which sets  
the reference value for the peak current that controls  
the on time of the power MOSFET.  
The designer should make sure that the SW node  
bleeding current is higher than the quiescent current of  
the floating driver (approximately 20µA). Usually the  
feedback resistors (R1 and R2) are selected such that  
the R1 + R2 value is small enough to provide that  
current:  
The operating voltage range of COMP (VC) is between  
0.75V and 2.0V in normal conditions. COMP is pulled  
down to the ground when the device shuts down. The  
COMP voltage must not be pulled higher than 2.6V.  
VOUT  
(2)  
IOUT _MIN  
+
> 20μA  
(R1 + R2 )  
Thermal Shutdown  
External Bootstrap Diode  
To protect the device from damage due to overheating,  
a thermal shutdown feature is implemented to disable  
the device when the die temperature exceeds +155℃  
(TYP). The chip is automatically enabled when the  
temperature falls below +135(20hysteresis, TYP).  
To improve the efficiency, using an external boot diode  
supplied from a 5V rail (in Figure 4) is recommended in  
the following cases:  
SG Micro Corp  
www.sg-micro.com  
MARCH 2022  
10  
 
SGM6061  
55V, 1.5A High Frequency Buck Converter  
APPLICATION INFORMATION  
In this section, power supply design with the SGM6061 non-synchronous Buck converter and selection of the  
external component will be explained based on the typical application that is applicable for various input and output  
voltage combinations.  
C4  
0.1μF  
L1  
10μH  
10  
VIN = 8V to 55V  
VOUT = 3.3V  
1
2
9
BOOT  
VIN  
SW  
SW  
R5  
R1  
C7  
D1  
100kΩ  
100kΩ  
NS  
SGM6061  
C2  
10μF  
100V  
C3  
0.1μF  
100V  
C9  
22μF  
25V  
3
8
7
5
4
EC  
NS  
C1  
NS  
C10  
NS  
+
EN  
SS  
FB  
1
FREQ  
GND COMP  
6
R2  
32.4kΩ  
C8  
1.5nF  
R6  
R4  
180kΩ  
C5  
10nF  
C6  
15pF  
24.9kΩ  
R3  
33kΩ  
NOTE: EC1 is optional. If the input voltage is far away from the VIN of SGM6061, EC1 should be installed.  
Figure 5. SGM6061 Application Example with 3.3V/1.5A Output  
off-time limits of the converter. In this design, fSW  
=
Design Requirements  
500kHz is chosen as a tradeoff. From Equation 3, the  
nearest standard resistor for this frequency is R4 =  
180kΩ.  
In this example, a high frequency regulator with  
ceramic output capacitors will be designed using  
SGM6061 and the details will be reviewed. The design  
requirements are typically determined at the system  
level. The known requirements are summarized in  
Table 1.  
Inductor Design  
Equation 4 is conventionally used to calculate the  
output inductance of a Buck converter. Generally, a  
smaller inductor is preferred to allow larger bandwidth  
and smaller size. The ratio of inductor current ripple (∆IL)  
to the maximum output current (IOUT) is represented as  
KIND factor (∆IL/IOUT). The inductor ripple current is  
bypassed and filtered by the output capacitor and the  
inductor DC current is passed to the output. Inductor  
ripple is selected based on a few considerations. The  
peak inductor current (IOUT + IL/2) must have a safe  
margin from the saturation current of the inductor in the  
worst-case conditions especially if a hard-saturation  
core type inductor (such as ferrite) is chosen. During  
power-up with large output capacitor, over-current,  
output shorted or load transient conditions, the actual  
peak current of inductor can be greater than ILPEAK  
calculated in equation 7. For peak current mode  
converter, selecting an inductor with saturation current  
above the switch current limit is sufficient. Typically, a  
20% to 40% ripple is selected (KIND = 0.2 ~ 0.4).  
Choosing a higher KIND value reduces the selected  
inductance.  
Table 1. Design Parameters  
Design Parameter  
Output Voltage  
Example Value  
3.3V  
Maximum Output Current  
1.5A  
Load Transient Response of 0.75A - 1.5A Step  
Input Voltage Range  
ΔVOUT = 7%  
12V nominal, 8V to 55V  
33mVP-P  
Maximum Output Voltage Ripple  
Turn-On Input Voltage (Rising VIN)  
Turn-Off Input Voltage (Falling VIN)  
7.9V  
5.6V  
Switching Frequency (fSW  
)
500kHz  
Operating Frequency  
Usually the first parameter to design is the switching  
frequency (fSW). Higher switching frequencies allow  
smaller solution size and smaller filter inductors and  
capacitors, and the bandwidth of the converter can be  
increased for faster response. It is also easier to filter  
noises because they also shift to higher frequencies.  
The drawbacks are increased switching and gate  
driving losses that result in lower efficiency and tighter  
thermal limits. Also the duty cycle range and step-down  
ratio will be limited due to the minimum on-time and/or  
V
- VOUT  
VOUT  
VINMAX × fSW  
INMAX  
(4)  
L1 =  
×
IOUT ×KIND  
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SGM6061  
55V, 1.5A High Frequency Buck Converter  
APPLICATION INFORMATION (continued)  
In this example, KIND = 0.4 is chosen and the  
two or more cycles for the loop to detect the output  
inductance is calculated to be 10.4μH. In this example,  
change and respond (change the duty cycle). It may  
also be expressed as the maximum output voltage drop  
or rise when the full load is connected or disconnected  
(100% load step). Equation 8 can be used to calculate  
the minimum output capacitance that is needed to  
supply or absorb a current step (ΔIOUT) for at least 2  
cycles until the control loop responds to the load  
change with a maximum allowed output transient of  
ΔVOUT (overshoot or undershoot).  
the nearest standard value 10μH is selected. The ripple,  
RMS and peak inductors current calculations are  
summarized in Equations 5, 6 and 7 respectively.  
V
- VOUT  
VOUT  
INMAX  
(5)  
IL =  
×
L1  
IOUT  
ILPEAK = IOUT  
V
INMAX × fSW  
2
IL  
12  
2
ILRMS  
=
+
(6)  
(7)  
IL  
2
2× ∆IOUT  
+
(8)  
COUT  
>
fSW × ∆VOUT  
The ripple, RMS, and peak inductor currents are  
calculated as 0.62A, 1.51A and 1.81A respectively. A  
10μH inductor from Sunlord SWPA8040S100MT with  
4.1A saturation and 3.3A RMS current ratings is selected.  
For example, if the acceptable transient to a 0.75A load  
step is 7%, by inserting ΔVOUT = 0.07 × 3.3V = 0.231V  
and ΔIOUT = 0.75A, the minimum required capacitance  
will be 13μF. Generally, the ESR of ceramic capacitors  
is small enough. The impact of output capacitor ESR on  
the transient is not taken into account in Equation 8.  
External Diode (D)  
The SGM6061 adopts non-synchronous architecture.  
Therefore an external diode is required to place  
between SW and GND pins. A Schottky diode is  
recommended due to the characteristics of fast  
recovery and small forward conduction voltage drop,  
which can help improve the efficiency and reduce the  
rising edge ring of SW node.  
Equation 9 can be used for the output ripple criteria and  
finding the minimum output capacitance needed.  
VORIPPLE is the maximum acceptable ripple. In this  
example, the allowed ripple is 33mV that results in  
minimum capacitance of 4.7μF.  
1
IL  
(9)  
COUT  
>
×
8× fSW VORIPPLE  
For main parameters of diode, the maximum reverse  
voltage rating of the selected diode must be greater  
than the maximum applicable input voltage. The peak  
current rating must be greater than the current limit,  
and the average forward current should be greater than  
typical load current with enough margin.  
Note that the impact of output capacitor ESR on the  
ripple is not considered in Equation 9. Use Equation 10  
to calculate the maximum acceptable ESR of the output  
capacitor to meet the output voltage ripple requirement.  
In this example, the ESR must be less than  
33mV/0.62A = 53.2mΩ.  
In this example, a B380-13-F from Diodes Inc. with 80V  
reverse voltage and 3A forward current is selected.  
VORIPPLE  
(10)  
RESR  
<
IL  
Output Capacitor Design  
Three primary criteria must be considered for design of  
the output capacitor (COUT): (1) the converter pole  
location, (2) the output voltage ripple, (3) the transient  
response to a large change in load current. The  
selected value must satisfy all of them. The desired  
transient response is usually expressed as maximum  
overshoot, maximum undershoot, or maximum recovery  
time of VOUT in response to a large load step. Transient  
response is usually the more stringent criteria in low  
output voltage applications. The output capacitor must  
provide the increased load current or absorb the  
excess inductor current (when the load current steps  
down) until the control loop can re-adjust the current of  
the inductor to the new load level. Typically, it requires  
Higher nominal capacitance value must be chosen due  
to aging, temperature, and DC bias derating of the  
output capacitors. In this example, a 22μF 25V ceramic  
capacitor with X7R dielectric and 3mΩ ESR is selected.  
There is a limit to the amount of ripple current that a  
capacitor can handle without damage or overheating.  
The inductor ripple is bypassed through the output  
capacitor. Equation 11 calculates the RMS current that  
the output capacitor must support. In this example, it is  
179mA.  
IL  
ICORMS  
=
(11)  
12  
SG Micro Corp  
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MARCH 2022  
12  
SGM6061  
55V, 1.5A High Frequency Buck Converter  
APPLICATION INFORMATION (continued)  
Input Capacitor Design  
UVLO Setting  
A high-quality ceramic capacitor (X5R or X7R or better  
dielectric grade) must be used for input decoupling of  
the SGM6061. If input power is far away from  
SGM6061, additional bulk capacitor is recommended in  
parallel to stabilize input voltage. The RMS value of  
input capacitor can be calculated from Equation 12 and  
the maximum ICIRMS occurs at 50% duty cycle. For this  
example, the maximum input RMS current is 0.75A.  
The ripple current rating of input capacitor should be  
greater than ICIRMS.  
The under-voltage lockout (UVLO) can be programmed  
by an external voltage divider network. In this design,  
the turn-on (enable to start switching) occurs when VIN  
rises above 7.9V (VSATRTUP). When the regulator is in  
operation, it will not stop switching (disabled) until the  
input falls below 5.6V (VSHUTDOWN). Use Equations 13 to  
calculate the resistors value. In this example, choose  
R5 = 100kΩ and R6 = 24.9kΩ.  
VSTARTUP - VENR  
(13)  
R5 = R6 ×  
VENR  
ICIRMS = IOUTMAX × D× 1-D  
(
)
Feedback Resistors  
(12)  
Choosing a 100kΩ value for the upper resistor (R1), the  
lower resistor (R2) can be calculated from Equation 14.  
The nearest 1% resistor for the calculated value (32kΩ)  
is 32.4kΩ. For higher output accuracy, choose resistors  
with better tolerance (0.5% or better).  
where D is the duty cycle.  
In this example, the voltage rating of capacitor should  
have a safe margin from maximum input voltage.  
Therefore, two 2.2μF/100V ceramic capacitors are  
selected for VIN to cover all DC bias, thermal and aging  
deratings, and a 0.1μF/100V capacitor is selected for  
further decoupling of high frequency noise. The small  
capacitor should be connected between VIN and GND  
pins as close as possible.  
VREF  
(14)  
R2 =  
×R1  
VOUT - VREF  
Loop Compensation Design  
Several techniques are used by engineers to  
compensate a DC/DC regulator. In this simplified  
method, the effects of the slope compensation are  
ignored. Because of this approximation, the actual  
cross over frequency is usually lower than the  
calculated value.  
The input voltage ripple can be calculated from  
Equation 13, and the maximum ripple occurs at 50%  
duty cycle.  
IOUTMAX ×D× 1-D  
(
)
V =  
(13)  
IN  
CIN × fSW  
First, the converter pole (fP), and ESR zero (fZ) are  
calculated from Equations 15 and 16. For COUT, the  
worst derated value of 20μF should be used. Equations  
17 and 18 can be used to find an estimation for  
closed-loop crossover frequency (fCO) as a starting  
point (choose the lower value).  
Soft-Start Capacitor  
The soft-start capacitor programs the ramp-up time of  
the output voltage during power-up. The ramp is  
needed in many applications due to limited voltage  
slew rate required by the load or limited available input  
current to avoid input voltage sag during startup (UVLO)  
or to avoid over-current protection that can occur during  
output capacitor charging. Soft-start will solve all these  
issues by limiting the output voltage slew rate.  
IOUT  
(15)  
(16)  
fP =  
fZ =  
2π× VOUT ×COUT  
1
2π×RESR ×COUT  
In this example, the output capacitor value is relatively  
small and the soft-start time is not critical because it  
does not require too much charge for 3.3V output  
voltage. However, it is better to set a small arbitrary  
value, like C5 = 10nF that results in 1.6ms startup time.  
fCO  
fCO  
=
fP × fZ  
(17)  
(18)  
fSW  
=
fP ×  
2
For this design, fP = 3.62kHz and fZ = 2.65MHz.  
Equation 17 yields 98kHz for crossover frequency and  
Equation 18 gives 30kHz. As the influence of slope  
compensation in the actual circuit, a slightly higher  
frequency of 33kHz is selected.  
Bootstrap Capacitor Selection  
A 0.1μF ceramic capacitor with 10V or higher voltage  
rating must be connected between the BOOT and SW  
pin. X5R or better dielectric types are recommended.  
SG Micro Corp  
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MARCH 2022  
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SGM6061  
55V, 1.5A High Frequency Buck Converter  
APPLICATION INFORMATION (continued)  
Having the crossover frequency, the compensation  
network (R3 and C8) can be calculated. R3 sets the gain  
of the compensated network at the crossover frequency  
and can be calculated by Equation 19.  
Place the larger input ceramic capacitor and  
Schottky diode close to relevant pins for minimizing  
the influence of ground bounce.  
Use short and wide trace to connect SW node to the  
inductor. Minimize the area of switching loop.  
Otherwise, large voltage spikes on the SW node and  
poor EMI performance are inevitable.  
2π× fCO × VOUT ×COUT  
GEA × VREF ×GCS  
(19)  
R3 =  
C8 sets the location of the compensation zero along  
with R3. To place this zero on the converter pole, use  
Equation 20.  
Sensitive signal like FB, COMP, EN traces must be  
placed away from high dv/dt nodes (such as SW)  
and not inside any high di/dt loop (like capacitor or  
switch loops). The ground of these signals should be  
connected to GND pin and separated with power  
ground.  
VOUT ×COUT  
IOUT ×R3  
C8 =  
(20)  
From Equations 19 and 20, the standard selected  
values are R3 = 33kΩ and C8 = 1.5nF.  
To improve the thermal relief, use a group of thermal  
vias under the exposed pad to transfer the heat to  
the ground planes in the opposite side of the PCB.  
Use small vias (approximately 15mil) such that they  
can be filled up during the reflow soldering process to  
provide a good metallic heat conduction path from  
the IC exposed pad to the other PCB side.  
A high frequency pole can also be added by a parallel  
capacitor if needed (not used in this example). The pole  
frequency can be calculated from Equation 21.  
IOUT  
(21)  
fP =  
2π×R3 ×C6  
Layout Considerations  
Connect VIN, GND and exposed pad pins to large  
copper areas to increase heat dissipation and  
long-term reliability. Keep SW area small to avoid  
emission issue.  
PCB layout is critical for stable and high-performance  
converter operation. The recommend layout is shown in  
Figure 6.  
Place the nearest input high frequency decoupling  
capacitor (0.1μF) between VIN and GND pins as  
close as possible.  
Top Layer  
Bottom Layer  
Figure 6. PCB Layout Guide  
SG Micro Corp  
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MARCH 2022  
14  
SGM6061  
55V, 1.5A High Frequency Buck Converter  
ADDITIONAL TYPICAL APPLICATION CIRCUITS  
C4  
0.1μF  
L1  
15μH  
10  
VIN = 10V to 55V  
V
OUT = 5V  
1
2
9
BOOT  
VIN  
SW  
SW  
R5  
R1  
C7  
D1  
100kΩ  
180kΩ  
NS  
SGM6061  
C1  
10μF  
100V  
C2  
10μF  
100V  
C3  
0.1μF  
100V  
C9  
22μF  
25V  
C10  
22μF  
25V  
3
8
7
5
4
EN  
SS  
FB  
FREQ  
GND COMP  
6
R2  
34kΩ  
C8  
1nF  
R6  
R4  
180kΩ  
C5  
10nF  
C6  
15pF  
20kΩ  
R3  
56kΩ  
Figure 7. 5V Output Typical Application (NS: not soldered)  
C4  
0.1μF  
L1  
33μH  
10  
VIN = 24V to 55V  
VOUT = 12V  
1
2
9
BOOT  
VIN  
SW  
SW  
R5  
R1  
C7  
D1  
100kΩ  
390kΩ  
NS  
SGM6061  
C1  
10μF  
100V  
C2  
10μF  
100V  
C3  
0.1μF  
100V  
C9  
22μF  
25V  
C10  
22μF  
25V  
3
8
7
5
4
EN  
SS  
FB  
FREQ  
GND COMP  
6
R2  
28kΩ  
C8  
820pF  
R6  
R4  
180kΩ  
C5  
10nF  
C6  
15pF  
7.5kΩ  
R3  
68kΩ  
Figure 8. 12V Output Typical Application (NS: not soldered)  
C4  
0.1μF  
L1  
47μH  
10  
VIN = 36V to 55V  
V
OUT = 24V  
1
2
9
BOOT  
VIN  
SW  
SW  
R5  
R1  
C7  
D1  
100kΩ  
806kΩ  
NS  
SGM6061  
C1  
10μF  
100V  
C2  
10μF  
100V  
C3  
0.1μF  
100V  
C9  
10μF  
50V  
C10  
10μF  
50V  
3
8
7
5
4
EN  
SS  
FB  
FREQ  
GND COMP  
6
R2  
28kΩ  
C8  
680pF  
R6  
R4  
180kΩ  
C5  
10nF  
C6  
15pF  
4.7kΩ  
R3  
91kΩ  
Figure 9. 24V Output Typical Application (NS: not soldered)  
REVISION HISTORY  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from Original (MARCH 2022) to REV.A  
Page  
Changed from product preview to production data.............................................................................................................................................All  
SG Micro Corp  
www.sg-micro.com  
MARCH 2022  
15  
PACKAGE INFORMATION  
PACKAGE OUTLINE DIMENSIONS  
TDFN-3×3-10L  
D
e
N10  
D1  
k
E
E1  
N5  
N1  
b
L
BOTTOM VIEW  
TOP VIEW  
2.4  
1.7 2.8  
A
A1  
A2  
0.6  
SIDE VIEW  
0.24  
0.5  
RECOMMENDED LAND PATTERN (Unit: mm)  
Dimensions  
In Millimeters  
Dimensions  
In Inches  
Symbol  
MIN  
MAX  
0.800  
0.050  
MIN  
0.028  
0.000  
MAX  
0.031  
0.002  
A
A1  
A2  
D
0.700  
0.000  
0.203 REF  
0.008 REF  
2.900  
2.300  
2.900  
1.500  
3.100  
2.600  
3.100  
1.800  
0.114  
0.091  
0.114  
0.059  
0.122  
0.103  
0.122  
0.071  
D1  
E
E1  
k
0.200 MIN  
0.500 TYP  
0.008 MIN  
0.020 TYP  
b
0.180  
0.300  
0.300  
0.500  
0.007  
0.012  
0.012  
0.020  
e
L
SG Micro Corp  
TX00060.000  
www.sg-micro.com  
PACKAGE INFORMATION  
TAPE AND REEL INFORMATION  
REEL DIMENSIONS  
TAPE DIMENSIONS  
P2  
P0  
W
Q2  
Q4  
Q2  
Q4  
Q2  
Q4  
Q1  
Q3  
Q1  
Q3  
Q1  
Q3  
B0  
Reel Diameter  
P1  
A0  
K0  
Reel Width (W1)  
DIRECTION OF FEED  
NOTE: The picture is only for reference. Please make the object as the standard.  
KEY PARAMETER LIST OF TAPE AND REEL  
Reel Width  
Reel  
Diameter  
A0  
B0  
K0  
P0  
P1  
P2  
W
Pin1  
Package Type  
W1  
(mm)  
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant  
TDFN-3×3-10L  
13″  
12.4  
3.35  
3.35  
1.13  
4.0  
8.0  
2.0  
12.0  
Q1  
SG Micro Corp  
TX10000.000  
www.sg-micro.com  
PACKAGE INFORMATION  
CARTON BOX DIMENSIONS  
NOTE: The picture is only for reference. Please make the object as the standard.  
KEY PARAMETER LIST OF CARTON BOX  
Length  
(mm)  
Width  
(mm)  
Height  
(mm)  
Reel Type  
Pizza/Carton  
13″  
386  
280  
370  
5
SG Micro Corp  
www.sg-micro.com  
TX20000.000  

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