SI3471A-A01-IMR [SILICON]
Power Supply Module,;
| 型号： | SI3471A-A01-IMR |
| 厂家： | 
SILICON |
| 描述： | Power Supply Module, |
| 文件： | 总25页 (文件大小：630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3471 Data Sheet
Autonomous Single Ethernet Port IEEE 802.3bt PoE PSE Device
KEY FEATURES
The Si3471 is a fully autonomous Power over Ethernet (PoE) Power Sourcing Equip-
ment (PSE) device. It is fully IEEE 802.3bt compliant and compatible with IEEE 802.3af
and 802.3at. It is optimized for use in PSE mid-spans and injectors that do not require
a host or MCU. The Si3471 integrates one Ethernet port with the IEEE-required pow-
ered device (PD) detection and classification functionality. In addition, it features pow-
ered device (PD) disconnect using dc sense algorithms and a robust multipoint detec-
tion algorithm. Intelligent protection circuitry includes input undervoltage detection, out-
put current limit, and short-circuit protection. The Si3471 works autonomously and does
not require a host or MCU to program it. The Si3471 is programmed for maximum
available power by pulling its configration pins high or low.
• Single Ethernet port PoE Power Sourcing
Equipment (PSE) device
• IEEE 802.3bt compliant
• IEEE 802.3af and 802.3at compatible
• Multi-point detection
• Comprehensive fault protection circuitry
includes:
• Power undervoltage lockout
• Output current limit and short-circuit
protection
Applications
• Thermal overload detection
• IEEE 802.3af, 802.3at, and 802.3bt Power Sourcing Equipment (PSE)
• Power over Ethernet Injectors
• Single Port Mid-Spans
• Operating temp range: –40 °C to +85 °C
• 38-pin 5 x 7 mm QFN package (RoHS-
compliant)
• Power over Ethernet Switches
• IP Phone Systems
• Smartgrid Switches
• Ruggedized and Industrial Switches
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Preliminary Rev. 0.5
Si3471 Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Si3471 Ordering Guide
Ordering
Part Number1
Product Revision
Package
Temperature Range (Ambient)
38-pin, 5 x 7 mm QFN
RoHS-compliant2
Si3471A-A01-IM
A01
–40 to 85 °C
Note:
1. Add an “R” to the end of the part number for tape and reel option (e.g., Si3471A-A01-IM or Si3471A-A01-IMR).
2. Pin 1 is oriented in Quadrant 1 in the tape:
1
2
3 4
Quadrant
Designations
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Preliminary Rev. 0.5 | 2
Table of Contents
1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Summary of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. Typical Application Example . . . . . . . . . . . . . . . . . . . . . . . . . 5
4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5. Power Available Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6. Operational Sequences and Example Waveforms. . . . . . . . . . . . . . . . . . 9
7. Reset Behavior
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
8. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 12
9. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10. Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . 19
11. Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
13. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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Preliminary Rev. 0.5 | 3
Si3471 Data Sheet
Summary of Operation
2. Summary of Operation
The Si3471 operates autonomously, without any external host or MCU control. All power on reset and brownout reset circuitry is inter-
nal. Upon VDD and VDDA being applied, an internal pull up sets the RESETb pin high, releasing the Si3471 from reset. The Si3471 then
reads the PWRAVL pins and configures itself to grant the maximum class set by the PWRAVL pins. The multi-point detection algorithm
runs until a valid PoE PD signature is detected and then proceeds with classification. If the Si3471 is configured to grant the class the
PD requests, it internally sets the current limit to the class requested by the PD and proceeds to grant power. Otherwise, the Si3471
follows the IEEE 802.3bt specification for power demotion. The Si3471 automatically detects when a PD disconnects and restarts the
detection process, continuously looking for a valid detection signature. If any error or fault condition occurs, the Si3471 removes power
from the PD and automatically restarts the detection process.
The Si3471 includes an LED pin for driving a status indicator LED. If a status LED is not used, then the pin can be left floating. The LED
operation is shown in the table below and is not configurable.
Table 2.1. LED Operation
LED Indication
LED on, no blinking
LED blinking slowly
LED blinking quickly
Status
Port successfully powered at requested power level
Looking for a valid detection signature
Error condition, such as port overload or loss of VPWR
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Preliminary Rev. 0.5 | 4
Si3471 Data Sheet
Typical Application Example
3. Typical Application Example
+54V
+54V
VPWR
+54V
DRAIN1
MIDb
GATE1
ALT A
PWRAVL0
Class 8 avail.
power shown
Data
Pair
Data
Pair
PWRAVL1
SENSE1
PWRAVL2
0.255Ω
0.255Ω
ALT A
+3.3V
VDD
RJ45
JACK
RJ45
JACK
KSENSE
Si3471
VDDA
+54V
ALT B
Spare
Pair
Spare
Pair
SENSE2
GATE2
RESETb
LED1
ALT B
DECPL
DRAIN2
Non-POE
Ethernet
Data In
Magnetics to
Power and
Add CM
Data Out
Voltage
GND
AGND
Figure 3.1. Typical 802.3bt Application Diagram
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Preliminary Rev. 0.5 | 5
Si3471 Data Sheet
Typical Application Example
+54V
ALT A
Data
Pair
Data
Pair
ALT A
RJ45
JACK
RJ45
JACK
ALT B
Spare
Pair
Spare
Pair
+54V
+54V
ALT B
VPWR
+54V
MIDb
Class 4 avail.
power shown
DRAIN1
PWRAVL0
PWRAVL1
PWRAVL2
GATE1
ALT A
Data
Pair
Data
Pair
SENSE1
0.255Ω
0.255Ω
ALT A
RJ45
JACK
ALT B
+3.3V
RJ45
JACK
VDD
KSENSE
Si3471
VDDA
+54V
SENSE2
GATE2
Spare
Pair
Spare
Pair
ALT B
RESETb
LED1
LED2
DRAIN2
Non-POE
Ethernet
Data In
Magnetics to
Power and
Add CM
Data Out
Voltage
DECPL
GND
AGND
Figure 3.2. Typical 802.3at Midspan Application Diagram
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Preliminary Rev. 0.5 | 6
Si3471 Data Sheet
Functional Block Diagram
4. Functional Block Diagram
VDD RESETb
VDDA
VPWR
Power-On
Reset
Power-On
Reset
VPWR
UVLO
Analog
Subsystem
Reset
PWRAVLn
MIDb
Detection and
Classification
Current Sense
IEEE 802.3bt PSE Controller
LED1
Control
Interface
LED2
Detection and
Classification
Voltage Driver
Temp
Voltage Ref
DECPL
Sensor
DRAINn
GATEn
Analog
Analog
Front
End
ADC
Mux
Gate
Drive
SENSEn
Current Sense
KSENSE
High Voltage Analog Subsystem
AGND
Controller
DGND
Figure 4.1. Si3471 Functional Block Diagram
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Preliminary Rev. 0.5 | 7
Si3471 Data Sheet
Power Available Settings
5. Power Available Settings
The Si3471 can be configured to grant a maximum amount of power to a PD based on the PWRAVL pins. The Si3471 reads the
PWRAVL pins at power up, upon being released from reset, or after auto-clearing a UVLO or over-temperature event. The PWRAVL
pins are only read during these three conditions and cannot be dynamically adjusted while the Si3471 is operational.
The IEEE 802.3bt specification provides an option for powering a Class 4 PD using either two of the twisted pairs in the Ethernet cable
or all four pairs. Using all four twisted pairs in the Ethernet cable reduces power loss in the cable, making the system more efficient.
Class 2 and 3 always use only two of the four twisted pairs. An IEEE 802.3at compliant PD can be powered by either two or four pairs.
When the maximum power available is Class 4, the Si3471 can be configured for either two pair or four pair operation. When the maxi-
mum power available is set to Class 5–8, the Si3471 automatically uses four pair powering for Class 4 PDs.
Table 5.1. Available Power by Class
IEEE 802.3bt PSE
Maximum Class1
PWRAVL23
PWRAVL13
PWRAVL03
Output Power2
90 W
Class 84
Class 74
Class 64
Class 54
1
1
1
1
1
1
0
0
1
0
1
0
75 W
60 W
45 W
Class 4
30 W
0
0
0
0
1
1
0
0
1
0
1
0
(Four-Pair Power)4
Class 4
(Two-Pair Power)5
60 W
(30 W per Ethernet port)
Class 3
(Two-Pair Power)5
30 W
(15 W per Ethernet port)
Class 2
(Two-Pair Power)5
14 W
(7 W per Ethernet port)
Note:
1. The Si3471 fully supports dual signature PDs and will provide total maximum power to the dual signature PD based on the
PWRAVL pin configuration.
2. Si3471 PSE power supply must be sized to account for maximum class and power to operate support circuitry including the
Si3471.
3. 0 = DGND; 1 = VDD. Setting MIDb = 0, PWRAVL = 011b is a reserved configuration.
4. Tie MIDb to VDD for Class 8–5 and Class 4, four-pair power. For more information see 9. Pin Descriptions.
5. In two-pair power operation, the Si3471 can be used to power one or two Ethernet ports. If only one Ethernet port is used in two-
pair power operation, tie unused SENSE pin and unused GATE pin to AGND and leave unused DRAIN pin floating.
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Preliminary Rev. 0.5 | 8
Si3471 Data Sheet
Operational Sequences and Example Waveforms
6. Operational Sequences and Example Waveforms
The Si3471 follows the IEEE 802.3bt specification for detection, connection check, classification, and power on. The waveforms shown
below illustrate Si3471 operation for single-signature and dual-signature PDs.
Si3471 Boot-up
Upon being released from reset (RESETb pulled high), the Si3471 boots up and reads the PWRAVL configuration pins and internally
sets the maximum class. The Si3471 auto-clears UVLO and over-temperature events, which also triggers the Si3471 to read the
PWRAVL pins.
Detection and Connection Check
After boot up, regardless of configuration, the Si3471 checks for a MOSFET fault. If a fault is found the Si3471 blinks the LED to signal
an error condition and does not continue with detection and classification.
When configured for four-pair operation (PWRAVL 111b, 110b, 101b, 100b, 011b), the Si3471 starts detection on one of the two pair
sets. If a valid PD signature is found, the Si3471 executes a connection check on both pair sets. The connection check algorithm deter-
mines if a single signature or dual signature PD is connected. The Si3471 then performs detection on the second pair set to confirm a
valid detection signature on both.
When configured for two-pair operation (PWRAVL 010b, 001b, 000b), each pair set is connected to a different Ethernet port, and the
Si3471 treats each independently of the other. Therefore, a connection check is not performed, and the Si3471 performs detection in-
dependently on each pair set/Ethernet port.
Classification and Power On—Four Pair, Single Signature
After two valid detection signatures and a single signature connection check, the Si3471 beings the classification and power-on se-
quence. The first step is a class probe to determine what power the PD is requesting. Regardless of the PWRAVL setting, the Si3471
always performs a class probe. Next, the PD is reset using a class reset and the final classification and power-on sequence begins. The
Si3471 always starts with a long first-class pulse to signal to the PD that it supports short maintain power signature (MPS). The Si3471
then continues with the full classification sequence to notify the PD of the granted class. In the following figure, pair set A and pair set B
the represent the primary and secondary pair sets. The Si3471 alternates which pair set detection beings on with each new detection
and classification cycle.
Vpwr
Pair set A
Pair set B
Vclass
Vmark
Vdet2
Vdet1
Figure 6.1. Example Waveform for 802.3bt Class 8 Single Signature Class 8
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Preliminary Rev. 0.5 | 9
Si3471 Data Sheet
Operational Sequences and Example Waveforms
Classification and Power On—Four Pair, Dual Signature
After a valid detection signature and a dual signature connection check, the Si3471 begins the classification and power-on sequence for
one of the pair sets. The first step is a class probe to determine what power the dual signature PD is requesting on one of the pair sets.
Regardless of the PWRAVL setting, the Si3471 always performs a class probe. Next, the PD is reset using a class reset and the final
classification and power-on sequence begins. The Si3471 always starts with a long first-class pulse to signal to the PD that it supports
short maintain power signature (MPS). The Si3471 then continues with the full classification sequence to notify the PD of the granted
class on one pair set. The figure below shows the classification waveform on one pair set for a Class 5 dual signature PD. Power is
then applied to this pair set. The Si3471 then repeats the same procedure on the second pair set and applies power. In the following
figure, Pair Set A and Pair Set B represent the primary and secondary pair sets. The Si3471 alternates which pair set detection begins
with each new detection and classification cycle.
Vpwr
Pair set A
Pair set B
Vclass
Vmark
Vdet2
Vdet1
Figure 6.2. Example Waveform for 802.3bt Dual Signature PD, Class 5 on Both Pair Sets
Classification and Power On—Two Pair
After a valid detection signature, the Si3471 begins the classification and power-on sequence. The first step is a class probe to deter-
mine what power the PD is requesting. Regardless of the PWRAVL setting, the Si3471 always performs a class probe. Next, the PD is
reset using a class reset and the final classification and power-on sequence begins. The Si3471 always starts with a long first-class
pulse to signal to the PD that it supports short maintain power signature (MPS) even in two-pair mode. The Si3471 then continues with
the full classification sequence to notify the PD of the granted class. Finally, it powers on the PD.
Vpwr
Pair set A
Vclass
Vmark
Vdet2
Vdet1
Figure 6.3. Example Waveform for 802.3at Two Pair Class 4
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Preliminary Rev. 0.5 | 10
Si3471 Data Sheet
Reset Behavior
7. Reset Behavior
In a typical application, the Si3471’s RESETb pin is tied to VDD through a pull up resistor. However, if the RESETb pin is not tied to
VDD, several conditions apply. The Si3471’s internal digital controller is responsible for resetting the analog subsystem. RESETb resets
the Si3471’s internal digital controller, which then reboots and resets the analog subsystem. If RESETb is held low, the internal digital
controller is held in reset and does not reset the analog subsystem. Furthermore, if the Si3471 is providing power when RESETb is
asserted, the analog subsystem will continue to provide power without any supervision or over-current protection from the digital con-
troller. The time between the RESETb pulse and the analog subsystem being reset is specified by t_an_resetb in the diagram and table
below. After the analog subsystem is reset, the Si3471 begins detection and classification based on the PWRAVL pin configuration. It is
also possible to hold the Si3471 in reset such that it is powered but inactive.
External Resetb
Internal Analog
Subsystem Resetb
Figure 7.1. Reset Timing
Table 7.1. Reset Timing Characteristics
Parameter
Symbol
Test Condition/Note
Min
Typ
Max
Units
tRESETb
RESETb Pulse Width
15
—
—
µs
If the Si3471 port is on, it will
remain on for t_anRESETb after
the rising edge of RESETb.
Analog Subsystem Reset after
RESETb deasserted
t_anRESETb
—
—
—
300
—
µs
Time from RESETb pulse end
to first detection sequence.
tBOOTUP
Boot up time
45
ms
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Preliminary Rev. 0.5 | 11
Si3471 Data Sheet
Electrical Characteristics
8. Electrical Characteristics
Table 8.1. Recommended Operating Conditions1
Parameter
Symbol
Test Condition/Note
Min
44
Typ
—
Max
57
Unit
V
IEEE Type 1 when port is ON
IEEE Type 2–3 when port is ON
IEEE Type 4 when port is ON
VPWR
VPWR Input Supply Voltage
50
—
57
V
52
—
57
V
VDD
VDD Supply Voltage
3.0
–40
3.3
—
3.6
85
V
Operating Ambient Temperature2
TAMB
°C
Note:
1. All specification voltages are referenced with respect to DGND. These specifications apply over the recommended operating volt-
age and temperature ranges of the device unless noted otherwise.
2. The Si3471 includes internal thermal shutdown above 125 °C.
Table 8.2. Electrical Specifications
These specifications apply over the recommended operating voltage and temperature ranges of the device specified in Table 8.1 Rec-
ommended Operating Conditions unless otherwise noted. Typical performance is for TA = 25 °C, VDD = AGND + 3.3 V, AGND and
DGND = 0 V, and VPWR at 54 V. VPORTn, VCLASS, and VMARK voltages are referenced with respect to VDRAIN. All other voltages are
referenced with respect to GND.
Parameter
Symbol
Test Condition/Note
Min
Typ
Max
Unit
Power Supply Voltages
VPWR Under Voltage
Lock Out
Level below which chip is not
operational
VPWR_UVLO
VUVLO_ON
VUVLO_OFF
25
25
—
31
28
31
34
—
34
V
V
V
VPWR UVLO Input Voltage
(to turn on)
VPWR UVLO Input Voltage
(to turn off)
VDD Under Voltage Lock Out
Hardware Reset Voltage
Power Supply Currents1
VDD_UVLO
VRESET
Voltage at which ports turn off
VDD voltage causing reset
2.6
—
2.8
1.8
3.0
—
V
V
During normal operation
VPWR = 8 V, VDD = 0 V
—
—
—
2
5
mA
µA
VPWR Supply Current
IVPWR
—
17
100
25
IDD
VDD Supply Current
During normal operation
mA
MOSFET Fault Specifications
VPORT
IFET
15
—
—
—
—
V
When VDRAIN = VPWR, if either condition is
met, a MOSFET fault is detected
MOSFET Fault Detected
2.5
mA
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Preliminary Rev. 0.5 | 12
Si3471 Data Sheet
Electrical Characteristics
Parameter
Symbol
Test Condition/Note
Min
Typ
Max
Unit
Detection Specifications
Measured when Vdrain is
shorted to VPWR
Detection Short Circuit
Current
IDET_SC
—
3.0
4.9
mA
Primary detection voltage
2.8
—
4.0
8.0
25
—
10.0
—
V
V
Detection voltage
when RDET =25.5 kΩ
VPORTn
Secondary detection voltage
RGOOD
Signature Resistance
—
kΩ
Minimum Signature
Resistance @ PD
RDET_MIN
15
26.5
—
17
30
—
19
33
10
kΩ
kΩ
µF
Maximum Signature
Resistance @ PD
RDET_MAX
Reject Signature Capaci-
tance
CREJECT
Classification Specifications
VCLASS
0 mA < ICLASS < 51 mA
Class Event Voltage
15.5
55
—
—
20.5
95
V
Measured when Vdrain is
shorted to VPWR
Classification Short Circuit
Current
ICLASS_SC
mA
Class Signature 0
Threshold between Class Signature 0 or 1
Class Signature 1
0
—
—
—
—
—
—
—
—
—
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
5
8
8
13
16
21
25
31
35
45
Threshold between Class Signature 1 or 2
Class Signature 2
13
16
21
25
31
35
Classification Current
Region
ICLASS_REGION
Threshold between Class Signature 2 or 3
Class Signature 3
Threshold between Class Signature 3 or 4
Class Signature 4
Threshold between Class Signature 4
or invalid class
45
—
51
mA
Classification Mark Specifications
VMARK
Mark Event Voltage
Mark current between 0 and 5 mA
7
5
—
—
10
V
Mark Event Current
Limitation
IMARK_LIM
100
mA
Output Voltage
IDRAINn
VDRAINn = 0 V
Bias Current of DRAINn Pin
—
—
–25
—
—
µA
V
Measured at VDRAIN with
respect to GND
Current Limit Detection
Threshold
VDRAIN_ILIM
3.00
Resistance from DRAIN
to AGND
RDRAIN
—
2.5
—
MΩ
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Si3471 Data Sheet
Electrical Characteristics
Parameter
Current Sense2
Symbol
Test Condition/Note
Min
Typ
Max
Unit
16.27
5
Class 0, 2-pair power, 15.4 W nominal
—
—
W
Class 1, 2-pair power, 4 W nominal
Class 2, 2-pair power, 7 W nominal
—
—
4.2
—
—
W
W
7.35
16.27
5
Class 3, 2-pair power, 15.4 W nominal
—
—
—
—
—
—
—
—
W
W
W
W
Class 4, 2 or 4-pair power3, 30 W nominal4
31.5
47.25
47.25
PCUT
Power Limit
Class 5, dual signature, 2 pair power,
45 W nominal5
Class 5, single signature, 4 pair power3,
45 W nominal
Class 6, 4-pair power3, 60 W nominal
Class 7, 4-pair power3, 75 W nominal
—
—
63
—
—
W
W
78.75
Class 8, 4-pair power3, 90 W nominal
Policy settings < 15 W
—
0
94.5
5
—
10
6
W
%
%
Parameter PCUT Tolerance
PCUT
Policy settings ≥ 15 W
0
3
Inrush, all assigned PD classes,
Vport > 30 V
400
60
425
—
450
—
mA
mA
mA
Inrush, all assigned PD classes,
Vport < 30 V
Power-on, assigned PD Class 0, 1, 2, 3, 4+
Type 1 limited
—
425
—
Power-on, assigned PD Class 4, 5, 6 7
Power-on, assigned PD Class 7, 8 7
—
—
850
—
—
mA
mA
Current Limit6
ILIM
1275
Power-on, assigned dual-signature PD
Class 1, 2, 3
—
—
—
425
850
—
—
—
mA
mA
mA
Power-on, assigned dual-signature PD
Class 4
Power-on, assigned dual-signature PD
Class 5
1275
Disconnect with power
provided over two pairs8
IPORT_DIS_2P
IPORT_DIS_4P
Current per pairset
—
—
6.5
3.5
—
—
mA
mA
Disconnect with power
provided over four pairs8
Current per pairset. While powering over
four pairs, if either pairset current is above
this threshold, the PD is considered to be
presenting the MPS signal.
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Preliminary Rev. 0.5 | 14
Si3471 Data Sheet
Electrical Characteristics
Parameter
Symbol
Test Condition/Note
Min
Typ
Max
Unit
MOSFET Gate Drive9
Drive Current
from GATEn Pin (Active)
GATEn pin active VGATEn = AGND
GATEn pin shut off VGATEn = AGND+ 5 V
IGATEn = –1 µA
–70
—
–50
50
–20
—
µA
mA
V
Drive Current
from GATEn Pin (Off)
Voltage Difference between
any GATEn and AGND Pin
10
11
12
Digital Pin Characteristics
Input Low Voltage
VIL
VIH
0.3 x VDD
—
PWRAVLn, RESETb, MIDb
RESETb, PWRAVLn, MIDb
—
—
—
V
V
0.7 x VDD
Input High Voltage
GND < VIN < VDD, RESETb, PWRAVLn,
MIDb
ILK
Input Leakage
–1.1
—
—
4
µA
µA
IPU
Pullup Current to VDD
RESETb, PWRAVLn, MIDb
–20
—
Note:
1. Positive values indicate currents flowing into the device. Negative currents indicate current flowing out of the device.
2. Current sense resistor, RSENSE, has a value of 0.255 Ω.
3. PCUT is within 802.3bt specified unbalance limits.
4. Class 4 can be powered over either 4-pair or 2-pair power. When powered over 4-pair, the total current across both alternatives is
used for PCUT measurements, when powered over a single pair PCUT is taken from the lone alternative.
5. Class 5 dual signature is on a per-alternative basis. The summed PCUT of both alternatives are held to Class 8 Single Signature
power levels.
6. Setting applies to each active alternative.
7. When powered in 4-pair mode, the ILIM value applies to each alternative; so, the total ILIM for the load is effectively doubled.
8. An MPS signal is considered present on an alternative when the current on that alternative is above these thresholds.
9. See "AN1228: FET Selection Guide for Si347x PSE Families" for detailed information on FET selection.
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Preliminary Rev. 0.5 | 15
Si3471 Data Sheet
Electrical Characteristics
Table 8.3. Absolute Maximum Ratings1
Range
Parameter
Unit
Supply Voltage
VDD
–0.3 to 4.0
V
V
V
VPWR
–0.3 to 80.0
DGND with Respect to AGND
0
Digital Signals
Analog Signals
All
–0.3 to 3.6
V
GATEn with Respect to AGND
SENSEn with Respect to AGND
DRAINn with Respect to AGND
–0.3 to 20.0
–0.3 to 3.0
–3 to 80
V
V
V
Temperature
Junction2
Storage
+150
–55 to +150
+300
°C
°C
°C
Solder (10 seconds)
Note:
1. Permanent device damage may occur if the maximum ratings are exceeded. Functional operation should be restricted to those
conditions specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may adversely affect device reliability.
2. The Si3471 includes internal thermal shutdown above 125 °C.
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Preliminary Rev. 0.5 | 16
Si3471 Data Sheet
Pin Descriptions
9. Pin Descriptions
RESETb
LED1
LED2
1
2
3
4
5
6
7
8
9
31
30 VDD
DGND
29 DGND
DECPL
GATE1
SENSE1
DRAIN1
KSENSE
DRAIN2
28
27 AGND
26
25 AGND
24
DNC
DNC
DNC
AGND
DGND
23 AGND
22 DNC
21 AGND
20 DNC
SENSE2 10
GATE2 11
AGND 12
Pin
1
Name
LED1
LED2
Type
Description
Turns on an external LED when a PoE PD is connected and pow-
ered. When using Si3471 in 802.3at mode, LED1 turns on an ex-
ternal LED to indicate the status of Ethernet Port 1.
Digital Output
Digital Output
2
Leave floating when using Si3471 in 802.3bt mode. When using
Si3471 in 802.3at mode, LED2 turns on an external LED to indi-
cate the status of Ethernet Port 2.
15, 17, 18, 19,
20, 22, 24, 26,
28, 32, 37, 38
DNC
No Connect
No connections or nets allowed. Leave floating.
Ground connection for 3.3 V digital supply (VDD). DGND and
AGND are tied together inside the Si3471 package.
3, 29, ePAD
DGND
Digital Ground
Analog Input
4
5
DECPL
GATE1
Add a 0.1 µF capacitor between this pin and AGND.
Gate drive outputs to external MOSFETs. Connect the GATEn
outputs to the external MOSFET gate node gate. A 50 μA pull-up
source is used to turn on the external MOSFET. When a current
limit is detected, the GATEn voltage is reduced to maintain con-
stant current through the external MOSFET. If the fault timer limit
is reached, GATEn pulls down, shutting off the external MOSFET.
GATEn will clamp to 11.5 V (typical) above AGND. If the port is
unused, leave the GATEn pin disconnected or tie to AGND.
Analog Output
11
GATE2
6
SENSE1
SENSE2
Current sense inputs for external MOSFETs. The SENSEn pin
measures current through an external 0.255 Ω resistor tied be-
tween the AGND supply rail and the SENSEn input. If the voltage
across the sense resistor subsequently triggers (the overcurrent
limit), the voltage driven onto the GATEn pin is modulated to pro-
vide constant current through the external MOSFET. Tie the
SENSEn pin to AGND when the port is not used.
Analog Input
10
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Preliminary Rev. 0.5 | 17
Si3471 Data Sheet
Pin Descriptions
Pin
Name
Type
Description
7
DRAIN1
Analog input with
25 μA pull-up to
VPWR
MOSFET drain output voltage sense. DRAINn pins should be left
floating if the port is unused.
9
8
DRAIN2
Kelvin point for accurate measurement of voltage across 0.255 Ω
sense resistor
KSENSE
Analog Input
13
14
VPWR
VDDA
Analog Power
Analog Power
Positive PoE voltage (+44 to +57 V) relative to AGND.
3.3 V supply to the analog side; tied with VDD at the PCB level.
12, 16, 21, 23,
25, 27, ePAD
Ground connection for VPWR supply. DGND and AGND are tied
together inside the Si3471 package.
AGND
VDD
Analog Ground
Digital Power
3.3 V digital supply (relative to DGND). Bypass VDD with a 0.1 μF
capacitor to DGND as close as possible to the Si3471 power sup-
ply pins; tied with VDDA.
30
31
Active low device reset input. See 7. Reset Behavior for more in-
formation.
Digital input with
20 μA pull-up to
VDD
RESETb
If RESETb is not used, RESETb should be left floating.
For 802.3bt operation, tie MIDb to VDD.
For 802.3at 2 pair operation, configures the Si3471 to operate as
a mid span or end span as follows:
33
MIDb
Digital Input
Digital Input
DGND = mid span, 2 second detection back off mode for power-
ing on ALTB.
VDD = end span, <400 msec detection intervals for powering on
ALTA.
34
35
36
PWRAVL0
PWRAVL1
PWRAVL2
Sets the maximum power available to the Si3471.
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Preliminary Rev. 0.5 | 18
Si3471 Data Sheet
Package Outline: 38-Pin QFN
10. Package Outline: 38-Pin QFN
The figure below illustrates the package details for the Si3471. The table lists the values for the dimensions shown in the illustration.
The Si3471 is packaged in an industry-standard, RoHS-compliant, 38-pin QFN package. The lead plating material is matte tin.
Figure 10.1. 38-Pin QFN Package
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Preliminary Rev. 0.5 | 19
Si3471 Data Sheet
Package Outline: 38-Pin QFN
Table 10.1. Package Diagram Dimensions
Dimension
Min
0.80
0.00
Nom
0.85
Max
0.90
0.05
A
A1
A3
b
0.035
0.203 REF
0.25
0.20
4.90
6.90
3.50
5.50
0.30
5.10
7.10
3.70
5.70
D
5.00
E
7.00
D2
E2
e
3.60
5.60
0.50 BSC
0.40
L
0.35
0.45
aaa
bbb
ccc
ddd
eee
0.10
0.10
0.08
0.10
0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VLLD-5.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Preliminary Rev. 0.5 | 20
Si3471 Data Sheet
Land Pattern
11. Land Pattern
The following figure illustrates the land pattern details for the Si3471. The table lists the values for the dimensions shown in the illustra-
tion. The stencil design and notes are shared as recommendations only. A customer or user may find it necessary to use different pa-
rameters and fine tune their SMT process as required for their application and tooling.
Figure 11.1. Si3471 Recommended Land Pattern
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Preliminary Rev. 0.5 | 21
Si3471 Data Sheet
Land Pattern
Table 11.1. PCB Land Pattern Dimensions
Symbol
C1
mm
5.00
7.00
0.50
0.30
0.80
3.70
5.70
C2
e
X1
Y1
X2
Y2
Notes:
General
1. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-
cation Allowance of 0.05 mm.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 mm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
4. A 3 x 5 array of 0.90 mm square openings on 1.10 mm pitch should be used for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Preliminary Rev. 0.5 | 22
Si3471 Data Sheet
Top Marking
12. Top Marking
Figure 12.1. Si3471A Top Marking (QFN)
Table 12.1. Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Bottom-Left-Justified
Device Part Number
YY = Year
Line 1 Mark Format:
Si3471AA01
Year and Work Week of Assembly
WW = Work Week
Line 2 Mark Format:
Line 3 Mark Format:
Manufacturing Code
“e3” Pb-Free Symbol
TTTTTT = Mfg Code
Circle = 1.3 mm Diameter
Country of Origin
TW = Taiwan
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Preliminary Rev. 0.5 | 23
Si3471 Data Sheet
Revision History
13. Revision History
Revision 0.5
March, 2020
• Initial release.
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Preliminary Rev. 0.5 | 24
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without
further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Without prior
notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the performance
of the product. Silicon Labs shall have no liability for the consequences of use of the information supplied in this document. This document does not imply or expressly grant any license
to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket approval is
required, or Life Support Systems without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health,
which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs
products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering
such weapons. Silicon Labs disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such
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Silicon Laboratories Inc.®, Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, ClockBuilder®, CMEMS®, DSPLL®, EFM®, EFM32®,
EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®,
Gecko OS, Gecko OS Studio, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® , Zentri, the Zentri logo and Zentri DMS, Z-
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