CXD2428Q [SONY]
Video Scan Converter; 视频扫描转换器
| 型号： | CXD2428Q |
| 厂家： | 
SONY CORPORATION |
| 描述： | Video Scan Converter |
| 文件： | 总16页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD2428Q
Video Scan Converter
Description
100 pin QFP (Plastic)
The CXD2428Q is an IC which generates control
signals and performs line interpolation calculations
for field memory (CXK1206AM/ATM) in order to
perform video signal scanning line conversion. In
addition, this IC performs the aspect conversion of
the ZOOM mode and WIDE-ZOOM mode in order to
support wide screens.
Features
• Video signal (NTSC/PAL) scanning line conversion function
• ZOOM function
(Function to cut top and bottom areas of 4:3 image and expand it to 16:9)
• WIDE-ZOOM function
(Function to vertically compress 4:3 image and expand it to 16:9)
• Operating frequency: 28.6MHz (typ.)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
VI
VSS – 0.5 to +7.0
VSS – 0.5 to VDD +0.5
VSS – 0.5 to VDD +0.5
–20 to +75
V
V
• Input voltage
• Output voltage
VO
V
• Operating temperature
• Storage temperature
Topr
Tstg
°C
°C
–55 to +150
Operating Conditions
Supply voltage
VDD
4.5 to 5.5
V
Applications
Liquid crystal projectors, etc.
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E95442-ST
CXD2428Q
Block Diagram
14 17 18 19
51
40
65 79 90
6
3
28 53 78
4
15 29
54
11
52
55
CSD0
CSD1
12 FSL1
13 FSL2
93
CSD2 56
CSD3 57
CSD4 58
CSD5 59
CSD6 60
CSD7 61
ADCK
94 ODEV
96 HIN
H-WRITE
98 CKI
99 RYOE
100
BYOE
CFD0 62
CFD1 63
CFD2 64
HOUT
HBLK
RDCK
21
22
45
66
67
68
69
CFD3
CFD4
CFD5
CFD6
H-READ
95 HRET
HCR0
VCR0
WEN0
VIN
89
91
92
97
CFD7 70
71
72
73
74
75
YSD0
YSD1
YSD2
YSD3
YSD4
V-WRITE
INTERPOLATION
VBLK
VOUT
REN1
VCR1
HCR1
INC1
10
20
46
47
48
49
YSD5 76
77
80
YSD6
YSD7
V-READ
81
82
83
84
85
YFD0
YFD1
YFD2
YFD3
YFD4
50 INC2
1
2
5
7
8
9
SCLK
SCTR
SDAT
P0
COEFFICIENT
SERIAL-
INTERFACE
YFD5 86
YFD6 87
YFD7 88
P1
P2
BLNK 16
1/2
35
23
25 26 27 30 31 32 33 34
36 37 38 39 41
42 43 44
24
– 2 –
CXD2428Q
Pin Description
Pin
Symbol
No.
I/O
Description
1
2
3
4
5
6
7
8
9
SCLK
SCTR
VDD0
VSS0
SDAT
TST0
P0
I
I
Serial transfer clock
Serial transfer control
Power supply
—
—
I
GND
Serial transfer data
Leave open.
O
I/O I/O port
I/O I/O port
I/O I/O port
P1
P2
10 VBLK
11 TST1
12 FSL1
13 FSL2
14 TST2
O
I
Vertical blanking output
Fixed to high.
I
Field identification selection (High: internal, Low: external)
Field information polarity switching
Fixed to low.
I
I
15
VSS1
—
I
GND
16 BLNK
17 TST3
18 TST4
19 TST5
20 VOUT
21 HOUT
22 HBLK
23 CD7
24 CD6
25 CD5
26 CD4
27 CD3
Output data control (High: black display)
Fixed to high.
I
I
Leave open.
I
Leave open.
O
O
O
O
O
O
O
O
—
—
O
O
O
O
O
O
O
O
Vertical sync signal output
Horizontal sync signal output
Horizontal blanking signal
B-Y/R-Y data output (MSB)
B-Y/R-Y data output
B-Y/R-Y data output
B-Y/R-Y data output
B-Y/R-Y data output
Power supply
28
29
VDD1
VSS2
GND
30 CD2
31 CD1
32 CD0
33 YD7
34 YD6
35 YD5
36 YD4
37 YD3
B-Y/R-Y data output
B-Y/R-Y data output
B-Y/R-Y data output (LSB)
Y data output (MSB)
Y data output
Y data output
Y data output
Y data output
– 3 –
CXD2428Q
Pin
No.
Symbol
I/O
Description
38 YD2
39 YD1
O
O
—
O
O
O
I
Y data output
Y data output
40
VSS3
GND
41 YD0
Y data output (LSB)
42 BYCK
43 RYCK
44 YCK
45 RDCK
46 REN1
47 VCR1
48 HCR1
49 INC1
50 INC2
51 TST6
52 CSD0
DA converter (B-Y) clock output
DA converter (R-Y) clock output
DA converter clock input
Readout clock input
I
O
O
O
O
O
I
Readout memory enable
Readout memory vertical clear
Readout memory horizontal clear
Readout memory line increment
Readout memory line increment
Fixed to high.
I
B-Y/R-Y lower line data input (LSB)
Power supply
53
54
VDD2
—
—
I
VSS4
GND
55 CSD1
56 CSD2
57 CSD3
58 CSD4
59 CSD5
60 CSD6
61 CSD7
62 CFD0
63 CFD1
64 CFD2
B-Y/R-Y lower line data input
B-Y/R-Y lower line data input
B-Y/R-Y lower line data input
B-Y/R-Y lower line data input
B-Y/R-Y lower line data input
B-Y/R-Y lower line data input
B-Y/R-Y lower line data input (MSB)
B-Y/R-Y upper line data input (LSB)
B-Y/R-Y upper line data input
B-Y/R-Y upper line data input
GND
I
I
I
I
I
I
I
I
I
65
VSS5
—
I
66 CFD3
67 CFD4
68 CFD5
69 CFD6
70 CFD7
71 YSD0
72 YSD1
73 YSD2
74 YSD3
B-Y/R-Y upper line data input
B-Y/R-Y upper line data input
B-Y/R-Y upper line data input
B-Y/R-Y upper line data input
B-Y/R-Y upper line data input (MSB)
Y lower line data input (LSB)
Y lower line data input
I
I
I
I
I
I
I
Y lower line data input
I
Y lower line data input
– 4 –
CXD2428Q
Pin
No.
Symbol
I/O
Description
75 YSD4
76 YSD5
77 YSD6
I
I
Y lower line data input
Y lower line data input
Y lower line data input
Power supply
I
78
79
VDD3
VSS6
—
—
I
GND
80 YSD7
81 YFD0
82 YFD1
83 YFD2
84 YFD3
85 YFD4
86 YFD5
87 YFD6
88 YFD7
89 HCR0
Y lower line data input (MSB)
Y upper line data input (LSB)
Y upper line data input
Y upper line data input
Y upper line data input
Y upper line data input
Y upper line data input
Y upper line data input
Y upper line data input (MSB)
Write memory horizontal clear
GND
I
I
I
I
I
I
I
I
O
—
O
O
O
I
90
VSS7
91 VCR0
92 WEN0
93 ADCK
94 ODEV
95 HRET
96 HIN
Write memory vertical clear
Write memory enable
AD converter clock
Field information input
Phase comparison output
Horizontal sync signal input
Vertical sync signal input
Write clock input
O
I
97 VIN
I
98 CKI
I
99 RYOE
100 BYOE
O
O
AD converter (R-Y) enable
AD converter (B-Y) enable
– 5 –
CXD2428Q
Electrical Characteristics
DC Characteristic
(VDD = 5.0V ± 0.5V, VSS = 0V, Topr = –20 to +75°C)
Item
Symbol
Conditions
Min.
Vss
Typ.
Max.
Unit
V
Applicable pin
Input, output voltage VI, VO
VDD
VIH
0.7VDD
1
Input voltage 1
V
V
V
V
VIL
0.3VDD
0.2VDD
0.4
VIH
0.8VDD
2
3
4
5
Input voltage 2
VIL
VOH1
IOH = –2mA
IOL = 4mA
VDD – 0.8
VDD – 0.8
VDD – 0.8
Output voltage 1
VOH1
IOH = –4mA
IOL = 8mA
Output voltage 2
0.4
VOH1
IOH = –6mA
IOL = 12mA
VIN = VSS or VDD
VIN = VSS
V
Output voltage 3
0.4
10
µA
µA
µA
µA
µA
µA
mA
6
ILI1
–10
–40
40
7
ILI2
Input leak current
ILI3
–100
100
–240
240
40
8
VIN = VDD
9
ILI4
VIN = VSS or VDD
VIN = VSS or VDD
VDD = 5.0V
–40
–40
10
Output leak current
ILZ
40
Current consumption IDD
70
1
2
All input pins other than
2
Pins 1, 2, 5, 96 and 97
3
5
All output pins other than 4 and
Pins 10, 22, 42, 43, 46 to 50, 89, 91, 92 and 93
Pins 20 and 21
4
5
6
7,
9
All input pins other than
Pins 11, 12, 19 and 51
8 and
7
8
Pins 13, 14, 16, 17 and 18
Pins 7, 8 and 9
Pin 6
9
10
– 6 –
CXD2428Q
I/O Pin Capacitance
(VDD = VI = 0V, f = 1MHz)
Max.
9
Item
Symbol
CIN
Min.
Typ.
Unit
pF
Input pin capacitance
Output pin capacitance
COUT
pF
11
Input/output pin capacitance CI/O
pF
11
Serial Block AC Characteristics
tw1
ts1
SCLK
SDAT
tw1
th1
ts0
th0
SCTL
(VDD = 5.0V ± 0.5V, VSS = 0V, Topr = –20 to +75°C)
Symbol
Item
Min.
Max.
Setup time of SDAT in relation to the rise of SCLK
Hold time of SDAT in relation to the rise of SCLK
SCLK pulse width
ts1
th1
tw1
ts0
th0
100ns
100ns
100ns
100ns
100ns
Setup time of SCTL in relation to the rise of SCLK
Hold time of SCTL in relation to the rise of SCLK
2tw1
2tw1
– 7 –
CXD2428Q
AC Characteristics
CKI
RDCK
tpd max
tpd min
Output
Input
invalid
ts2
th2
1) Output block
(VDD = 5.0V ± 0.5V, VSS = 0V, Topr = –20 to +75°C)
Item
Delay of ADCK in relation to CKI
tpd min
3ns
tpd max
28ns
70ns
32ns
30ns
45ns
22ns
38ns
32ns
25ns
Condition
Delay of HCR0, VCR0 and WEN0 in relation to CKI
Delay of REN1, VCR1, HCR1, INC1 and INC2 in relation to RDCK
Delay of HOUT in relation to RDCK
Load 25pF
10ns
6ns
5ns
Delay of VOUT in relation to RDCK
7ns
Delay of RYCK and BYCK in relation to YCK
Delay of YD0 to YD7 and CD0 to CD7 in relation to RDCK
Delay of HRET in relation to CKI
1ns
Load 20pF
5ns
5ns
Delay of BYOE and RYOE in relation to CKI
2ns
2) Input block
Item
ts2
th2
Setup and hold time of CSD0 to CSD7, CFD0 to CFD7, YSD0 to
YSD7 and YFD0 to YFD7 in relation to RDCK
3ns
9ns
3ns
20ns
2ns
Setup and hold time of HIN in relation to CKI
Setup and hold time of VIN in relation to CKI
Setup and hold time of YCK in relation to CKI
3ns
0ns
20ns
– 8 –
CXD2428Q
Description of Operation
1. CXD2428Q Control System
The operation timing of this IC is controlled by serial data.
An 8-bit address and 8-bit data are sequentially transferred from the falling edge of SCTL, and each control
data is taken in at the rising edge of SCLK up to the rising edge of SCTL.
SCLK
SCTL
SDAT
ADDRESS
DATA
Serial transfer timing
2. Control Mode
The following timing and modes are changed by control data:
Variable
H SHIFT
V SHIFT
H PHASE
V PHASE
H SZ RD
Address
00H
Function
Horizontal write start timing
10H
Vertical write start timing
20H
Horizontal readout start timing
Vertical readout start timing
Number of readout line dots (0 to 7 bits)
Number of readout line dots (8 to 10 bits)
Number of write line dots (0 to 7 bits)
Number of write line dots (8 to 10 bits)
Conversion mode address
30H
40H
50H
H SZ WR
41H
51H
LN DAT0 to 7
MD DAT0 to 7
TOP BLK
BTM BLK
LFT BLK
RGT BLK
IODAT
60 to 67H
70 to 77H
A0H
Conversion mode data
Vertical blanking rise timing
Vertical blanking fall timing
B0H
C0H
Horizontal blanking rise timing
Horizontal blanking fall timing
D0H
1
80H
I/O port output data
2
IOSL
E0H
OUT port select
3
TEST
90H
1
Transfer xxxx.1xxx (binary) for PAL (4:3 display) and xxxx.0xxx (binary) for the other systems.
Transfer 00 (hexadecimal).
2
3
Transfer 00 (hexadecimal).
– 9 –
CXD2428Q
3. Scanning Line Conversion Function
LN DAT (address 6x) and MD DAT (address 7x) are data which indicate scanning line conversion coefficients.
There are the following 8 conversion coefficients:
1.67/1.75/2/2.22/2.33/2.67/2.8 = K
number of scanning lines of output signal
K =
number of scanning lines of input signal
The conversion coefficient equals the ratio of one scanning line to scan lines generated by interpolation. The
coefficient can be changed on the screen.
In the WIDE-ZOOM mode, compression and expansion on the screen can be changed by combining these 8
coefficients as desired.
Compression and expansion are carried out by setting the coefficient and the number of switching lines.
The upper 6 MD DAT bits (bits 3 to 8) provide coefficient data.
The lower 2 MD DAT bits (bits 1 and 2) and 8 LN DAT bits provide line number data.
The coefficients and corresponding MD DAT are shown below.
Coefficient
MD DAT
MSB LSB
1.67
1.75
000100xx
001000xx
000001xx
000000xx
2.0
2.1
010000xx
011100xx
101000xx
110000xx
110110xx
2.22
2.33
2.67
2.8
The interpolation coefficient 2.0 has two modes which are determined by the value of bit 3.
When bit 3 is 1, an interpolation line is generated by outputting the same signal as that of the
preceding line. This mode realizes images with a higher vertical resolution.
When bit 3 is 0, an interpolation line is output by averaging signals of the preceding and following
lines. This mode realizes images with smoother diagonal lines.
4. DA Converter Clock
RYCK and BYCK, which are YCK halved and phase inverted, are output as D/A converter clocks.
5. Output Control
A black signal is output when BLNK is high.
– 10 –
CXD2428Q
Mode Setting and Operation
1. Horizontal Write
CKI is input after phase comparison with HSYNC input.
PLL frequency division value is set by H SZ WR (standard 38C (hexadecimal)), and HRET is output.
Write start timing is set by H SHIFT.
An ADCK pulse, which is CKI halved, is output.
The enable pulses RYOE and BYOE for R-Y and B-Y A/D converter are output.
HIN
H SZ WR + 2ck
HRET
HWEN
(Internal pulse)
(H SHIFT + 1) × 2ck
HCR0
RYOE
BYOE
CKI
ADCK
RYOE
BYOE
– 11 –
CXD2428Q
2. Horizontal Readout
In this IC, the readout and write clocks are asynchronous.
The readout 1H sample coefficient is set by H SZ RD.
An HOUT pulse with a pulse width of 68ck is output from horizontal readout reference pulse HRSP (internal
pulse).
Readout start timing is set by H PHASE.
The HBLK pulse set by LFT BLK and RGT BLK is output. However, this pulse does not stop readout, so it has
no relation to the actual blanking interval.
HRSP
H SZ RD + 2ck
68ck
HOUT
HREN
(Internal pulse)
H PHASE + 2ck
LFT BLK + 2ck
HBLK
HCR1
RGT BLKck
– 12 –
CXD2428Q
3. Vertical Write
Write start timing is set by V SHIFT.
The CXK1206AM/ATM write control pulses VCR0, HCR0 and WEN0 are output.
HIN
VIN
VSP
V SHIFT + 1H
(Internal pulse)
VWEN
(Internal pulse)
VCR0
HCR0
WEN0
– 13 –
CXD2428Q
4. Vertical Readout
The VBLK pulse set by TOP BLK and BTM BLK is output. However, this pulse does not stop readout, so it
has no relation to the actual blanking interval.
Readout start timing is set by V PHASE.
The CXK1206AM/ATM readout control pulses VCR1, HCR1, REN1, INC1 and INC2 are output.
The VSP pulse (internal pulse) corresponding to V SHIFT is the vertical readout reference pulse.
A VOUT pulse with a pulse width of 6H ( indicates double scan H) is output.
HOUT
VSP
(Internal pulse)
6H
VOUT
Note 1)
Note 1) PAL (4:3): 65H , Others: 0H
VREN
(Internal pulse)
V PHASE + 1H
TOP BLK + 1H
320 + BTM BLKH
VBLK
VCR1
HCR1
REN1
Note 2) INC1 and INC2 timing varies with modes.
INC1
INC2
– 14 –
CXD2428Q
Application Circuit
CAD
YAD
+5V
+5V
0.1µ
20
21
22
23
24
25
26
27
28
29
30
31
32
0.1µ
20
21
22
23
24
25
26
27
28
29
30
31
32
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
VSS
NC
VDD
NC
VSS
NC
VDD
NC
CKW0
HCLR0
INC0
VCLR0
WE
HCLR1
INC1
VCLR1
OE1
DO13
DO12
DO11
DO10
CKR1
TSM
TR1
APM
PW
DIN3
DIN2
DIN1
DIN0
HCLR2
INC2
VCLR2
OE2
DON23
DO22
DO21
DO20
CKR2
TR2
APM
PW
DIN3
DIN2
CKW0
HCLR0
INC0
VCLR0
Y07
HCR0
VCR0
WEN0
C07
C06
C05
HCR0
Y06
Y05
VCR0
WEN0
DIN1
DIN0
HCLR2
INC2
VCLR2
OE2
WE
HCLR1
INC1
VCLR1
OE1
DO13
Y04
HCR1
INC1
VCR1
REN1
C04
HCR1
INC1
HCR1
HCR1
INC2
VCR1
REN1
INC2
VCR1
VCR1
REN1
REN1
Y87
Y86
Y85
Y84
C87
C86
Y97
C97
C96
C95
DON23
DO22
DO21
DO20
CKR2
TR2
DO12
DO11
DO10
CKR1
TSM
TR1
Y96
Y95
33
34
35
36
37
38
33
34
35
36
37
38
C85
C84
Y94
4
3
2
1
C94
4
3
2
1
VSS
TR0
VSS
TR0
CXK1206
CXK1206
10k × 4
10k × 4
10k × 4
10k × 4
+5V
+5V
0.1µ
0.1µ
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
VSS
VDD
NC
CKW0
HCLR0
INC0
VCLR0
WE
HCLR1
INC1
VCLR1
OE1
DO13
DO12
DO11
DO10
CKR1
TSM
TR1
TR0
VSS
VDD
NC
CKW0
HCLR0
INC0
VCLR0
WE
HCLR1
INC1
VCLR1
OE1
DO13
DO12
DO11
DO10
CKR1
TSM
TR1
TR0
NC
APM
PW
DIN3
DIN2
DIN1
DIN0
HCLR2
INC2
VCLR2
OE2
DON23
DO22
DO21
DO20
CKR2
TR2
VSS
NC
APM
PW
DIN3
DIN2
DIN1
DIN0
HCLR2
INC2
VCLR2
OE2
DON23
DO22
DO21
DO20
CKR2
TR2
VSS
Y03
Y02
Y01
HCR0
VCR0
WEN0
C03
C02
C01
HCR0
VCR0
WEN0
HCR1
Y00
HCR1
INC1
VCR1
REN1
C00
HCR1
HCR1
INC2
VCR1
REN1
INC1
VCR1
INC2
VCR1
REN1
C83
REN1
Y83
Y82
Y81
Y80
Y93
Y92
Y91
C93
C92
C91
C82
C81
C80
Y90
C90
36
37
38
3
2
1
36
37
38
3
2
1
CXK1206
CXK1206
10k × 4
10k × 4
10k × 4
10k × 4
+5V
10µ
16V
0.1µ
80 7978 7776 7574 7372 7170 6968 6766 6564 6362 6160 5958 5756 5554 5352 51
50
49
48
47
46
45
44
43
42
Y80
Y81
Y82
Y83
Y84
Y85
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
INC2
INC1
HCR1
VCR1
YFD0
YFD1
YFD2
YFD3
YFD4
YFD5
YFD6
YFD7
HCR0
VSS7
VCR0
WEN0
ADCK
ODEV
HRET
HIN
VIN
CKI
RYOE
INC2
INC1
HCR1
VCR1
REN1
RDCK
YCK
RYCK
BYCK
YD0
VSS3
YD1
YD2
YD3
YD4
YD5
YD6
YD7
CD0
CD1
28.6MHz
REN1
Y86
Y87
YCLK
R-YCLK
B-YCLK
HCR0
YDA0
YDA1
YDA2
YDA3
41
CXD2428Q
40
39
38
37
36
35
34
33
32
VCR0
WEN0
YDA4
YDA5
HD
VD
CKI
97
98
99
YDA6
YDA7
100
31
BYOE
1
2 3 4 5 6 7 8 9 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 30
10µ
16V
0.1µ
+5V
SCLK
SCTR
SDAT
SIO
YDA
CDA
HRCK
HOUT
VOUT
VBLK
B-YOE
R-YOE
HRET
ADCK
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 15 –
CXD2428Q
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1
0.15 – 0.05
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12
M
0.15
0° to 15°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER PLATING
QFP-100P-L01
SONY CODE
QFP100-P-1420-A
EIAJ CODE
LEAD MATERIAL
COPPER / 42 ALLOY
1.4g
PACKAGE WEIGHT
JEDEC CODE
– 16 –
相关型号：
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