SSM4507GM [SSC]
N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET; N和P沟道增强型功率MOSFET
| 型号： | SSM4507GM |
| 厂家： | 
SILICON STANDARD CORP. |
| 描述： | N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET |
| 文件： | 总8页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSM4507GM
N AND P-CHANNEL ENHANCEMENT
MODE POWER MOSFET
PRODUCT SUMMARY
N-CH BVDSS
RDS(ON)
30V
D2
Simple Drive Requirement
Low On-resistance
Fast Switching Performance
D2
36mΩ
D1
D1
ID
P-CH BVDSS
RDS(ON)
6.0A
-30V
72mΩ
-4.2A
G2
S2
G1
S1
SO-8
DESCRIPTION
ID
The advanced power MOSFETs from Silicon Standard Corp.
provide the designer with the best combination of fast switching,
ruggedized device design, low on-resistance and cost-effectiveness.
D2
The SO-8 package is universally preferred for all commercial-
industrial surface mount applications and suited for low voltage
applications such as DC/DC converters.
D1
S1
G2
G1
Pb-free; RoHS-compliant
S2
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
Units
N-channel
P-channel
-30
VDS
VGS
Drain-Source Voltage
30
±20
6
V
V
Gate-Source Voltage
±20
ID@TA=25℃
ID@TA=70℃
IDM
Continuous Drain Current3
Continuous Drain Current3
Pulsed Drain Current1
-4.2
A
4.8
20
-3.4
A
-20
A
PD@TA=25℃
Total Power Dissipation
Linear Derating Factor
2.0
0.016
W
W/℃
℃
℃
TSTG
TJ
Storage Temperature Range
Operating Junction Temperature Range
-55 to 150
-55 to 150
THERMAL DATA
Symbol
Parameter
Thermal Resistance Junction-ambient3
Value
62.5
Unit
Rthj-a
Max.
℃/W
08/06/2007 Rev.1.00
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1
SSM4507GM
N-CH ELECTRICAL CHARACTERISTICS
@TJ=25 oC (unless otherwise specified )
Symbol
BVDSS
Parameter
Test Conditions
VGS=0V, ID=250uA
Min. Typ. Max. Units
Drain-Source Breakdown Voltage
30
-
-
0.02
-
-
-
V
ΔBVDSS/ΔTj
Breakdown Voltage Temperature Coefficient Reference to 25℃, ID=1mA
Static Drain-Source On-Resistance2 VGS=10V, ID=6A
VGS=4.5V, ID=4A
V/℃
mΩ
RDS(ON)
-
36
-
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
60
mΩ
V
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
Drain-Source Leakage Current (Tj=25oC)
Drain-Source Leakage Current (Tj=70oC)
Gate-Source Leakage
Total Gate Charge2
VDS=VGS, ID=250uA
VDS=10V, ID=6A
VDS=30V, VGS=0V
VDS=24V, VGS=0V
VGS=±20V
3
8
-
-
S
IDSS
1
uA
uA
nA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
-
25
IGSS
Qg
-
±100
ID=6A
6
2
3
7
6
15
4
10
-
Qgs
Qgd
td(on)
tr
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time2
Rise Time
VDS=24V
VGS=4.5V
-
VDS=15V
-
ID=1A
-
td(off)
tf
Turn-off Delay Time
RG=3.3Ω,VGS=10V
RD=15Ω
-
Fall Time
-
Ciss
Coss
Crss
Input Capacitance
VGS=0V
430 690
Output Capacitance
VDS=25V
100
70
-
-
Reverse Transfer Capacitance
f=1.0MHz
SOURCE-DRAIN DIODE
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
VSD
trr
Forward On Voltage2
Reverse Recovery Time2
IS=1.7A, VGS=0V
IS=6A, VGS=0V
dI/dt=100A/µs
-
-
-
-
1.2
V
19
11
-
-
ns
nC
Qrr
Reverse Recovery Charge
08/06/2007 Rev.1.00
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2
SSM4507GM
P-CH ELECTRICAL CHARACTERISTICS
@TJ=25 oC (unless otherwise specified )
Symbol
BVDSS
Parameter
Test Conditions
VGS=0V, ID=-250uA
Min. Typ. Max. Units
Drain-Source Breakdown Voltage
-30
-
-
-
-
V
ΔBVDSS/ΔTj
Breakdown Voltage Temperature Coefficient Reference to 25℃,ID=-1mA
Static Drain-Source On-Resistance2 VGS=-10V, ID=-4A
VGS=-4.5V, ID=-2A
-0.02
V/℃
mΩ
RDS(ON)
-
-
-
72
-
120 mΩ
VGS(th)
gfs
Gate Threshold Voltage
VDS=VGS, ID=-250uA
VDS=-10V, ID=-4A
VDS=-30V, VGS=0V
VDS=-24V, VGS=0V
VGS=±20V
-1
-
-
-3
V
Forward Transconductance
Drain-Source Leakage Current (T=25oC)
7.2
-
-
S
IDSS
uA
uA
nA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
-
-1
j
Drain-Source Leakage Current (T=70oC)
-
-
-25
j
IGSS
Qg
Gate-Source Leakage
Total Gate Charge2
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time2
Rise Time
-
-
±100
ID=-4A
-
6
1
3
8
7
18
4
10
-
Qgs
Qgd
td(on)
tr
VDS=-24V
-
VGS=-4.5V
-
-
VDS=-15V
-
-
ID=-1A
-
-
td(off)
tf
Turn-off Delay Time
Fall Time
RG=3.3Ω,VGS=-10V
RD=15Ω
-
-
-
-
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VGS=0V
-
400 640
VDS=-25V
-
90
65
-
-
f=1.0MHz
-
SOURCE-DRAIN DIODE
Symbol
Parameter
Forward On Voltage2
Reverse Recovery Time2
Test Conditions
IS=-1.7A, VGS=0V
IS=-4A, VGS=0V
Min. Typ. Max. Units
VSD
trr
-
-
-
-
-1.2
V
15
20
-
-
ns
nC
Qrr
Reverse Recovery Charge
dI/dt=-100A/µs
Notes:
1.Pulse width limited by Max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on 1 in2 copper pad of FR4 board ; 135℃/W when mounted on min. copper pad.
08/06/2007 Rev.1.00
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3
SSM4507GM
N-Channel
40
25
20
15
10
5
T A =25 o C
10V
7.0V
5.0V
T A =150 o
C
10 V
7.0V
35
30
25
20
15
10
5
5.0V
4.5V
4.5V
V
G =3.0V
VG =3.0V
0
0
0
1
2
3
4
5
0
1
1
2
2
3
3
4
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1.8
1.6
1.4
1.2
1.0
0.8
0.6
61
I D =6A
ID =4 A
56
51
46
41
36
31
26
T
A =25o C
V
G =10V
Ω
Ω
Ω
Ω
-50
0
50
100
150
3
5
7
9
11
T j ,Junction Temperature ( o C)
VGS , Gate-to-Source Voltage (V)
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
3
2.5
2
6
5
4
3
2
1
0
T j =150 o
C
T j =25 o C
1.5
1
0.5
0
0.2
0.4
0.6
0.8
1
1.2
-50
0
50
100
150
T j ,Junction Temperature ( o C)
VSD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
Fig 6. Gate Threshold Voltage v.s.
Junction Temperature
08/06/2007 Rev.1.00
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4
SSM4507GM
N-Channel
f=1.0MHz
1000
100
10
12
I D = 6 A
10
8
C iss
V
DS =24V
C oss
C rss
6
4
2
0
0
2
4
6
8
10
12
1
5
9
13
17
21
25
29
VDS , Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
100
1
Duty factor=0.5
0.2
10
0.1
0.1
1ms
10ms
100ms
1s
0.05
1
0.02
0.01
PDM
Single Pulse
t
0.01
T
0.1
T A =25 o C
10s
DC
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Single Pulse
o
Rthja=135 C/W
0.01
0.001
0.1
1
10
100
0.0001
0.001
0.01
0.1
1
10
100
1000
VDS , Drain-to-Source Voltage (V)
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
VDS
VG
90%
QG
4.5V
QGS
QGD
10%
VGS
tr
t
d(off)tf
td(on)
Charge
Q
Fig 11. Switching Time Waveform
Fig 12. Gate Charge Waveform
08/06/2007 Rev.1.00
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5
SSM4507GM
P-Channel
40
30
25
20
15
10
5
-10V
-7.0V
A =25 o C
T A =150 o C
T
-10 V
-7.0V
30
20
10
0
-5.0V
-4.5V
-5.0V
-4.5V
V G =-3.0V
V
G =-3.0V
0
0
1
2
3
4
5
0
1
2
3
4
5
-V DS , Drain-to-Source Voltage (V)
-V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
90
80
70
60
50
1.6
1.4
1.2
1.0
0.8
0.6
I D = - 2 A
T A =25 o C
I D =-4A
V
G =-10V
Ω
Ω
Ω
Ω
3
5
7
9
11
-50
0
50
100
150
T j , Junction Temperature ( o C)
-V GS ,Gate-to-Source Voltage (V)
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
5
2.5
4
3
2
1
0
2
T j =150 o C
T j =25 o C
1.5
1
0.5
-50
0
50
100
150
0
0.2
0.4
0.6
0.8
1
1.2
-V SD , Source-to-Drain Voltage (V)
T j , Junction Temperature ( o C)
Fig 5. Forward Characteristic of
Reverse Diode
Fig 6. Gate Threshold Voltage v.s.
Junction Temperature
08/06/2007 Rev.1.00
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6
SSM4507GM
P-Channel
f=1.0MHz
1000
100
10
12
I D =-4A
V DS =-24V
10
8
C iss
6
C oss
C rss
4
2
0
1
5
9
13
17
21
25
29
0.0
2.5
5.0
7.5
10.0
12.5
-V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
100
1
Duty factor=0.5
0.2
0.1
10
1ms
0.1
0.05
1
10ms
0.02
0.01
PDM
100ms
0.01
t
Single Pulse
T
0.1
T A =25 o C
1s
10s
DC
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja=135oC/W
Single Pulse
0.01
0.001
0.1
1
10
100
0.0001
0.001
0.01
0.1
1
10
100
1000
-V DS , Drain-to-Source Voltage (V)
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
VDS
VG
90%
QG
-4.5V
QGS
QGD
10%
VGS
td(off)
tr
td(on)
tf
Q
Charge
Fig 11. Switching Time Waveform
Fig 12. Gate Charge Waveform
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08/06/2007 Rev.1.00
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SSM4507GM
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
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