SSM4509GM [SSC]
N- AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS; N和P沟道增强型功率MOSFET
| 型号： | SSM4509GM |
| 厂家： | 
SILICON STANDARD CORP. |
| 描述： | N- AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS |
| 文件： | 总8页 (文件大小：401K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSM4509GM
N- AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS
N-CH BVDSS
RDS(ON)
ID
30V
14mW
10A
Simple drive requirement
Low on-resistance
D2
D2
D1
D1
Fast switching characteristic
G2
S2
P-CH BVDSS
RDS(ON)
ID
-30V
G1
SO-8
S1
20mW
-8.4A
Description
Advanced Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and cost-effectiveness.
D2
S2
D1
S1
G2
G1
The SSM4509GM is in the SO-8 package, which is widely preferred for
commercial and industrial surface mount applications, and is well suited
for applications such as low-voltage motor drives and inverters.
Pb-free lead finish (second-level interconnect)
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
N-channel
P-channel
-30
VDS
VGS
Drain-Source Voltage
30
±20
10
V
V
Gate-Source Voltage
±20
ID @ TA=25°C
ID @ TA=70°C
IDM
Continuous Drain Current3
Continuous Drain Current3
Pulsed Drain Current1
-8.4
A
7.9
30
-6.7
A
-30
A
PD @ TA=25°C
Total Power Dissipation
Linear Derating Factor
2.0
W
0.016
W/°C
°C
°C
TSTG
TJ
Storage Temperature Range
Operating Junction Temperature Range
-55 to 150
-55 to 150
Thermal Data
Symbol
Parameter
Value
62.5
Unit
Rthj-a
Thermal Resistance Junction-ambient3
Max.
°C/W
3/10/2005 Rev.1.01
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SSM4509GM
N-channel Electrical Characteristics @ Tj= 25oC (unless otherwise specified)
Symbol
BVDSS
Parameter
Test Conditions
VGS=0V, ID=250uA
Min. Typ. Max. Units
Drain-Source Breakdown Voltage
30
-
-
-
V
V/°C
mΩ
mΩ
V
∆BVDSS/ ∆Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA
Static Drain-Source On-Resistance2 VGS=10V, ID=9A
VGS=4.5V, ID=5A
0.02
-
RDS(ON)
-
-
-
14
20
3
-
VGS(th)
gfs
Gate Threshold Voltage
VDS=VGS, ID=250uA
VDS=10V, ID=9A
1
-
-
Forward Transconductance
14
-
S
IDSS
Drain-Source Leakage Current (T=25oC)
uA
uA
nA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
VDS=30V, VGS=0V
VDS=24V, VGS=0V
VGS=±20V
ID=9A
-
-
-
-
-
-
-
-
-
-
1
j
Drain-Source Leakage Current (T=70oC)
-
25
j
IGSS
Qg
±100
Gate-Source Leakage
Total Gate Charge2
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time2
Rise Time
-
23
6
65
-
Qgs
Qgd
td(on)
tr
VDS=24V
VGS=4.5V
14
14
10
36
17
-
VDS=15V
-
ID=1A
-
td(off)
tf
Turn-off Delay Time
Fall Time
RG=3.3Ω , VGS=10V
RD=15Ω
-
-
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VGS=0V
-
-
-
1770 2830
VDS=25V
430
350
-
-
f=1.0MHz
Source-Drain Diode
Symbol
Parameter
Forward On Voltage2
Reverse Recovery Time2
Test Conditions
IS=1.7A, VGS=0V
IS=9A, VGS=0V
Min. Typ. Max. Units
VSD
trr
-
-
-
-
1.2
V
31
25
-
-
ns
nC
Qrr
Reverse Recovery Charge
dI/dt=100A/µs
3/10/2005 Rev.1.01
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2 of 8
SSM4509GM
P-channel Electrical Characteristics @ Tj= 25oC (unless otherwise specified)
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
BVDSS
Drain-Source Breakdown Voltage
VGS=0V, ID=-250uA
-30
-
-
0.02
-
-
V
V/°C
mΩ
mΩ
V
∆BVDSS/∆Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=-1mA-
Static Drain-Source On-Resistance2 VGS=-10V, ID=-8A
VGS=-4.5V, ID=-4A
-
RDS(ON)
-
20
-
-
30
VGS(th)
gfs
Gate Threshold Voltage
VDS=VGS, ID=-250uA
VDS=-10V, ID=-8A
VDS=-30V, VGS=0V
VDS=-24V, VGS=0V
VGS=±20V
-1
-
-
-3
Forward Transconductance
14
-
-
S
Drain-Source Leakage Current (T=25oC)
IDSS
uA
uA
nA
nC
nC
nC
ns
-
-1
j
Drain-Source Leakage Current (T=70oC)
-
-
-25
j
IGSS
Qg
Gate-Source Leakage
Total Gate Charge2
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time2
Rise Time
-
-
±100
ID=-8A
-
27
4
45
-
Qgs
Qgd
td(on)
tr
VDS=-24V
-
VGS=-4.5V
-
18
16
11
40
25
-
VDS=-15V
-
-
ns
ID=-1A
-
-
ns
td(off)
tf
Turn-off Delay Time
Fall Time
RG=3.3Ω , VGS=-10V
RD=15Ω
-
-
ns
-
-
pF
pF
pF
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VGS=0V
-
1580 2530
VDS=-25V
-
540
450
-
-
f=1.0MHz
-
Source-Drain Diode
Symbol
Parameter
Forward On Voltage2
Reverse Recovery Time2
Test Conditions
IS=-1.7A, VGS=0V
IS=-8A, VGS=0V
Min. Typ. Max. Units
VSD
trr
-
-
-
-
-1.2
V
40
32
-
-
ns
nC
Qrr
Reverse Recovery Charge
dI/dt=-100A/µs
Notes:
1.Pulse width limited by max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on 1 in2 copper pad of FR4 board ; 135°C/W when mounted on min. copper pad.
3/10/2005 Rev.1.01
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SSM4509GM
N-Channel
160
140
120
100
80
T A = 25 o C
T A = 150 o
C
10V
7.0V
140
10V
7.0V
120
100
80
60
40
20
0
5.0V
4.5V
5.0V
4.5V
60
40
20
VG =3.0V
V
G =3.0V
0
0
1
2
3
4
0
1
2
3
4
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
18
1.6
1.4
1.2
1.0
0.8
0.6
I D = 9 A
I D = 5 A
VG =10V
T
A =25 o C
15
12
9
3
5
7
9
11
-50
0
50
100
150
VGS , Gate-to-Source Voltage (V)
T j , Junction Temperature ( o C)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
2.5
2.0
1.5
1.0
10
8
6
T j =150 o
C
T j =25 o C
4
2
0
0
0.2
0.4
0.6
0.8
1
1.2
-50
0
50
100
150
T j , Junction Temperature ( o C)
VSD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
3/10/2005 Rev.1.01
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4 of 8
SSM4509GM
N-Channel
f=1.0MHz
14
10000
1000
100
I D =9A
12
VDS =24V
10
8
C iss
6
C oss
C rss
4
2
0
0
10
20
30
40
50
1
5
9
13
17
21
25
29
VDS , Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
100
1
Duty factor=0.5
100us
0.2
0.1
10
1ms
10ms
100ms
1s
0.1
0.05
0.02
1
0.01
PDM
0.01
t
T
Single Pulse
0.1
Duty factor = t/T
T A =25 o C
DC
Peak Tj = PDM x Rthja + Ta
Rthja =135oC/W
Single Pulse
0.01
0.001
0.1
1
10
100
0.0001
0.001
0.01
0.1
1
10
100
1000
VDS , Drain-to-Source Voltage (V)
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedanc
VDS
VG
90%
QG
4.5V
QGS
QGD
10%
VGS
tr
t
d(off)tf
td(on)
Charge
Q
Fig 11. Switching Time Waveform
Fig 12. Gate Charge Waveform
3/10/2005 Rev.1.01
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5 of 8
SSM4509GM
P-Channel
160
120
100
80
60
40
20
0
-10V
-10V
T A = 25 o C
T A = 150 o C
140
120
100
80
-7.0V
-7.0V
-5.0V
-4.5V
-5.0V
-4.5V
60
40
V G =-3.0V
V G =-3.0V
20
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
-V DS , Drain-to-Source Voltage (V)
-V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
33
1.6
1.4
1.2
1.0
0.8
0.6
I D =- 8 A
I D = - 4 A
T A =25 o C
30
V G =-10V
27
24
21
18
15
3
5
7
9
11
-50
0
50
100
150
T j , Junction Temperature ( o C)
-V GS ,Gate-to-Source Voltage (V)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
8
2.5
6
2
1.5
1
T j =150 o C
T j =25 o C
4
2
0
0
0.2
0.4
0.6
0.8
1
1.2
-50
0
50
100
150
T j , Junction Temperature ( o C)
-V SD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
3/10/2005 Rev.1.01
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6 of 8
SSM4509GM
P-Channel
f=1.0MHz
14
10000
1000
100
12
I D =- 8 A
V
DS =-24V
10
8
C iss
6
C oss
C rss
4
2
0
0
10
20
30
40
50
60
1
5
9
13
17
21
25
29
-V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
100
1
Duty factor=0.5
0.2
100us
1ms
10
0.1
0.1
0.05
10ms
1
0.02
0.01
PDM
100ms
1s
t
0.01
Single Pulse
T
0.1
T
A =25 o C
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Single Pulse
Rthja=135oC/W
DC
0.01
0.001
0.1
1
10
100
0.0001
0.001
0.01
0.1
1
10
100
1000
-V DS , Drain-to-Source Voltage (V)
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
VDS
VG
90%
QG
-4.5V
QGS
QGD
10%
VGS
td(off)
tr
td(on)
tf
Q
Charge
Fig 11. Switching Time Waveform
Fig 12. Gate Charge Waveform
3/10/2005 Rev.1.01
www.SiliconStandard.com
7 of 8
SSM4509GM
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
3/10/2005 Rev.1.01
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