SSM4513M [SSC]
N AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS; N型和P沟道增强型功率MOSFET
| 型号： | SSM4513M |
| 厂家： | 
SILICON STANDARD CORP. |
| 描述： | N AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS |
| 文件： | 总8页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSM4513M/GM
N AND P-CHANNEL ENHANCEMENT-MODE POWER MOSFETS
Simple drive requirement
Low on-resistance
N-CH BVDSS
35V
D2
D2
W
36m
R DS(ON)
D1
D1
Fast switching performance
ID
P-CH BVDSS
RDS(ON)
5.8A
-35V
G2
S2
G1
SO-8
S1
W
68m
Description
ID
-4.3A
Advanced Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching, ruggedized
device design, low on-resistance and cost-effectiveness.
D2
D1
G2
G1
The SSM4513M is in the SO-8 package, which is widely
preferred for commercial and industrial surface mount applications,
and is well-suited for most low voltage applications.
S1
S2
This device is available with Pb-free lead finish (second-level interconnect) as SSM4513GM.
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
N-channel
P-channel
-35
VDS
VGS
Drain-Source Voltage
35
±20
5.8
4.7
20
V
V
Gate-Source Voltage
±20
ID @ TA=25°C
ID @ TA=70°C
IDM
Continuous Drain Current3
Continuous Drain Current3
Pulsed Drain Current1
-4.3
A
-3.4
A
-20
A
PD @ TA=25°C
Total Power Dissipation
Linear Derating Factor
2.0
0.016
W
W/°C
°C
°C
TSTG
TJ
Storage Temperature Range
Operating Junction Temperature Range
-55 to 150
-55 to 150
Thermal Data
Symbol
Parameter
Value
62.5
Unit
Rthj-a
Thermal Resistance Junction-ambient3
Max.
°C/W
10/12/2004 Rev.2.01
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1 of 8
SSM4513M/GM
N-ch Electrical Characteristics @ Tj=25oC (unless otherwise specified)
Symbol
BVDSS
Parameter
Test Conditions
VGS=0V, ID=250uA
Min. Typ. Max. Units
Drain-Source Breakdown Voltage
35
-
-
-
V
V/°C
mW
mW
V
DBVDSS/DT j
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA
Static Drain-Source On-Resistance2 VGS=10V, ID=5A
VGS=4.5V, ID=3A
0.03
-
RDS(ON)
-
-
-
36
60
3
-
VGS(th)
gfs
Gate Threshold Voltage
VDS=VGS, ID=250uA
VDS=10V, ID=5A
1
-
-
Forward Transconductance
Drain-Source Leakage Current (Tj=25oC)
Drain-Source Leakage Current (Tj=70oC)
Gate-Source Leakage
Total Gate Charge2
7
-
S
IDSS
uA
uA
nA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
VDS=30V, VGS=0V
VDS=24V, VGS=0V
VGS=±20V
ID=5A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
25
IGSS
Qg
-
±100
6
2
3
8
7
16
3
10
-
Qgs
Qgd
td(on)
tr
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time2
Rise Time
VDS=28V
VGS=4.5V
-
VDS=15V
-
ID=1A
-
td(off)
tf
Turn-off Delay Time
RG=3.3Ω ,V =10V
-
GS
Fall Time
RD=15W
VGS=0V
-
Ciss
Coss
Crss
Input Capacitance
470 750
Output Capacitance
VDS=25V
f=1.0MHz
90
60
-
-
Reverse Transfer Capacitance
Source-Drain Diode
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
VSD
trr
Forward On Voltage2
IS=1.7A, VGS=0V
IS=5A, VGS=0V
dI/dt=100A/µs
-
-
-
-
1.2
V
Reverse Recovery Time
Reverse Recovery Charge
17
11
-
-
ns
nC
Qrr
10/12/2004 Rev.2.01
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2 of 8
SSM4513M/GM
P-ch Electrical Characteristics @ Tj=25oC (unless otherwise specified)
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
BVDSS
Drain-Source Breakdown Voltage
VGS=0V, ID=-250uA
-35
-
-
-
V
DBVDSS/DTj
Breakdown Voltage Temperature Coefficient Reference to 25°C,ID=-1mA
Static Drain-Source On-Resistance2 VGS=-10V, ID=-4A
-0.03
-
V/°C
mW
RDS(ON)
-
-
-
68
VGS=-4.5V, ID=-2A
-
100 mW
VGS(th)
gfs
Gate Threshold Voltage
VDS=VGS, ID=-250uA
VDS=-10V, ID=-4A
VDS=-30V, VGS=0V
VDS=-24V, VGS=0V
VGS=±20V
-1
-
-
-3
V
Forward Transconductance
Drain-Source Leakage Current (T=25oC)
6
-
-
S
IDSS
uA
uA
nA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
-
-1
j
Drain-Source Leakage Current (T=70oC)
-
-
-25
j
IGSS
Qg
Gate-Source Leakage
Total Gate Charge2
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time2
Rise Time
-
-
±100
ID=-4A
-
6
1
4
8
7
20
4
10
-
Qgs
Qgd
td(on)
tr
VDS=-28V
-
VGS=-4.5V
-
-
VDS=-15V
-
-
ID=-1A
-
-
td(off)
tf
Turn-off Delay Time
Fall Time
RG=3.3W , VGS=-10V
RD=15W
-
-
-
-
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VGS=0V
-
410 660
VDS=-25V
-
95
70
-
-
f=1.0MHz
-
Source-Drain Diode
Symbol
Parameter
Forward On Voltage2
Test Conditions
IS=-1.7A, VGS=0V
IS=-4A, VGS=0V
Min. Typ. Max. Units
VSD
trr
-
-
-
-
-1.2
V
Reverse Recovery Time
Reverse Recovery Charge
21
16
-
-
ns
nC
Qrr
dI/dt=-100A/µs
Notes:
1.Pulse width limited by max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on 1 in2 copper pad of FR4 board , t <10sec ; 135°C/W when mounted on min. copper pad.
10/12/2004 Rev.2.01
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3 of 8
SSM4513M/GM
N-channel
30
30
20
10
0
10V
7.0V
T A =25 o C
T A = 150 o
C
10V
7.0V
5.0V
4.5V
20
5.0V
4.5V
10
VG =3.0V
V
G =3.0V
0
0
1
2
3
4
5
0
1
2
3
4
5
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1.8
1.4
1.0
0.6
65
I D =5A
I D =3A
A =25 o C
VG =10V
T
55
45
35
25
2
4
6
8
10
-50
0
50
100
150
T j , Junction Temperature ( o C)
VGS , Gate-to-Source Voltage (V)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
5
1.5
1.1
0.7
0.3
4
3
2
1
0
T j =150 o
C
T j =25 o C
0
0.2
0.4
0.6
0.8
1
1.2
-50
0
50
100
150
T j ,Junction Temperature ( o C)
VSD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
10/12/2004 Rev.2.01
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4 of 8
SSM4513M/GM
N-channel
f=1.0MHz
12
1000
100
10
I D = 5 A
C iss
VDS =2 8 V
9
6
3
C oss
C rss
0
0
1
5
9
13
17
21
25
29
4
8
12
16
VDS , Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
100
1
Duty factor=0.5
0.2
10
1ms
0.1
0.1
0.05
10ms
1
0.02
0.01
PDM
100ms
1s
0.01
t
Single Pulse
T
0.1
T A =25 o C
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Rthja =135oC/W
10s
DC
Single Pulse
0.01
0.001
0.1
1
10
100
0.0001
0.001
0.01
0.1
1
10
100
1000
t , Pulse Width (s)
VDS , Drain-to-Source Voltage (V)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
VG
VDS
90%
QG
4.5V
QGS
QGD
10%
VGS
tr
t
d(off)tf
td(on)
Charge
Q
Fig 11. Switching Time Waveform
Fig 12. Gate Charge Waveform
10/12/2004 Rev.2.01
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5 of 8
SSM4513M/GM
P-Channel
30
30
20
10
0
T A =25 o C
- 10V
- 7.0V
T A = 150 o C
- 10V
- 7.0V
- 5.0V
20
10
0
- 4.5V
- 5.0V
- 4.5V
V G = - 3.0V
V G = - 3.0V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
-V DS , Drain-to-Source Voltage (V)
-V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1.8
95
I D = -4 A
I D = -2 A
T A =25 o C
V G = - 10V
85
1.4
75
65
55
1.0
0.6
-50
0
50
100
150
2
4
6
8
10
T j , Junction Temperature ( o C)
-V GS , Gate-to-Source Voltage (V)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
4
1.5
3
1.1
0.7
0.3
2
T j =150 o C
T j =25 o C
1
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
-50
0
50
100
150
T j , Junction Temperature ( o C)
-V SD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
10/12/2004 Rev.2.01
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6 of 8
SSM4513M/GM
P-Channel
f=1.0MHz
12
1000
100
10
I D =-4A
10
8
V
DS =-28V
C iss
6
C oss
C rss
4
2
0
1
5
9
13
17
21
25
29
0.0
3.0
6.0
9.0
12.0
-V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
100
1
Duty factor=0.5
0.2
10
0.1
0.1
1ms
0.05
1
0.02
10ms
0.01
PDM
t
0.01
100ms
Single Pulse
T
0.1
T A =25 o C
Duty factor = t/T
1s
10s
DC
Peak Tj = PDM x Rthja + Ta
Rthja=135oC/W
Single Pulse
0.01
0.001
0.0001
0.1
1
10
100
0.001
0.01
0.1
1
10
100
1000
-V DS , Drain-to-Source Voltage (V)
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
VDS
VG
90%
QG
-4.5V
QGS
QGD
10%
VGS
td(off)
tr
td(on)
tf
Q
Charge
Fig 11. Switching Time Waveform
Fig 12. Gate Charge Waveform
10/12/2004 Rev.2.01
www.SiliconStandard.com
7 of 8
SSM4513M/GM
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
10/12/2004 Rev.2.01
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