STE2001DIE2_技术文档

STE2001

65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

PRODUCT PREVIEW

■

65 x 128 bits Display Data RAM

Low Power Consumption, suitable for battery

operated systems

Configurable matrix: 65 x 128 or 33 x 128

Programmable (65/33) MUX rate

Row by Row Scrolling

■

Logic Supply Voltage range from 1.9 to 5V

High Voltage Generator Supply Voltage range

from 2.4 to 4.5V

■ Automatic data RAM Blanking procedure

■

Display Supply Voltage range from 4.5 to 9V

■

Selectable Input Interface:

2

• I C Bus Fast and Hs-mode (read and write)

DESCRIPTION

• Parallel Interface (write only)

• Serial Interface (write only)

The STE2001 is a low power CMOS LCD controller

driver. Designed to drive a 65 rows by 128 columns

graphic display, provides all necessary functions in a

single chip, including on-chip LCD supply and bias

voltages generators, resulting in a minimum of exter-

nals components and in a very low power consump-

tion. The STE2001 features three standard interfaces

■

Fully Integrated Oscillator requires no external

components

■

Fully Integrated Configurable LCD bias voltages

generator with:

• Selectable (5X, 4X, 3X, 2X) multiplication factor

• Effective sensing for High Precision Output

• Four selectable temperature compensation

coefficients

2

(Serial, parallel, I C) for ease of interfacing with the

host µcontroller.

■

Type

Bumped Wafers

BumpedDice on Waffle Pack

Ordering Number

STE2001DIE1

Designed for chip-on-glass (COG) applications

■ Programmable bottom row pads mirroring and

top row pads mirroring for compatible with both

TCP and COG applications

STE2001DIE2

Figure 1. Block Diagram

CO to C127

R0 to R64

TIMING

GENERATOR

COLUMN

DRIVERS

ROW

DRIVERS

OSC

CLOCK

BIAS VOLTAGE

GENERATOR

VLCDIN

DATA

SHIFT

LATCHES

REGISTER

VLCDSENSE

VLCDOUT

HIGH VOLTAGE

GENERATOR

65 x 128

RAM

SCROLL

LOGIC

RES

RESET

TEST_0_13

BSY_FLG

VDD1,2,3

TEST

DISPLAY

CONTROL

LOGIC

DATA

REGISTER

INSTRUCTION

REGISTER

V

_SS1,2

SEL1,2

2

I CBUS

PARALLEL

SERIAL

D00IN1137

SAO SCL

SDA_IN SDA_OUT DB0 to DB7 E

PD/C SCE SDIN SCLK SD/C

October 2001

1/36

This is preliminary information on a new product now in development. Details are subject to change without notice.

STE2001

PIN DESCRIPTION

N°

Pad

Type

Function

R0 to R64

1 to 16

O

LCD Row Driver Output

145 to 177

257 to 272

C0 to C127 17 to 144

227 to 238

O

LCD Column Driver Output

V

,

GND

Ground pads. V

is GND for V

, V

DD1 SS2

for V

and V

DD2 DD3

SS1 2

SS1

V

186 to 191 Supply IC Positive Power Supply

192 to 201 Supply Internal Generator Supply Voltages.

DD1

V

,

DD2 3

V

246 to 251 Supply LCD Supply Voltages for the Column and Row Output Drivers.

239 to 244 Supply Voltage Multiplier Ouput

LCDIN

V

LCDOUT

V

245

Supply Voltage Multiplier Regulation Input. V Sensing for Output Voltage Fine

LCDOUT

LCDSENSE

Tuning

SEL1,2

183, 184

223

I

Interface Mode Selection

2

SDA_IN

I C Bus Data In

2

SDA_OUT

SCL

222

224

225

O

I

I C Bus Data Out

2

I C bus Clock

2

SA0

I

I C Slave Address LSB

OSC

RES

185

221

I

External Oscillator Input

Reset Input. Active Low.

DB0 to

DB7

211 to 218

Parallel Interface 8 Bit Data Bus

E

220

219

207

210

209

208

206

I

Parallel Interface Data Latch Signal. Data are Latched on the Falling EDGE.

Parallel Interface Data/Command Selector

Serial Interface Data Input

PD/C

SDIN

SCLK

SCE

I

Serial Interface Clock

I

Serial Interface ENABLE. When Low the Incoming Data are Clocked In.

Serial Interface Data/Command selection

SD/C

BSYFLG

I

O

Active Procedure Flag. Notice if There is an ongoing Internal Operation. Active

Low.

T1 to T13 178 to 181

202 to 205

I/O

Test Pads.

226

252 to 256

2/36

STE2001

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

V

Supply Voltage Range

LCD Supply Voltage Range

Supply Current

- 0.5 to + 6.5

- 0.5 to + 5

- 0.5 to + 10

- 50 to +50

DD1

V

DD2,3

V

LCD

I

mA

V

SS

V

Input Voltage (all input pads)

DC Input Current

-0.5 to V

+ 0.5

DD2,3

i

I

- 10 to + 10

mA

mW

°C

in

I

DC Output Current

- 10 to + 10

300

out

P

Total Power Dissipation (T = 85°C)

tot

j

P

Power Dissipation per Output

Operating Junction Temperature

Storage Temperature

30

o

T

-40 to + 85

- 65 to 150

j

T

stg

ELECTRICAL CHARACTERISTICS

DC OPERATION

(V

= 1.9to V

+ 0.5V; V

= 2.4 to 4.5 V; V

= 0V; V

= 4.5 to9V; T

=-40 to 85°C; unless otherwise

DD1

DD2,3

ss1,2

LCD

amb

specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Supply Voltages

Supply Voltage

V

1.9

1.8

2.4

V

DD1

DD2,3

+ 0.5

T

=-20 to 85°C

V

DD2,3

+ 0.5

amb

V

Supply Voltage

LCD Voltage Internally

generated

4.5

DD2,3

V

LCD Supply Voltage

Supply Current

LCD Voltage Supplied externally

Internally generated; note 1

4.5

9

V

LCDIN

V

LCDOUT

I(V

)

V

DD

= 2.8V; V

LCD

= 7.6V; 4x

= 0;

8

15

µA

DD1

charge pump; f

sclk

T

amb

= 25°C; note 3.

I(V

)

Voltage Generator Supply

Current

with VOP = 0 and PRS = 0

with external V = 7.6V

10

70

15

A

µ

DD2,3

LCD

V

=7.6V; V =2.8V;

115

µA

LCD

DD

f

= 0; T

= 25°C; no display

sclk

amb

load; 4x charge pump; note 3,6

= 0

F

osc

3/36

STE2001

ELECTRICAL CHARACTERISTICS

(continued)

Symbol

I(V

Parameter

Test Condition

= 7.6V; V =2.8V;

Min.

Typ.

Max.

Unit

)

Total Supply Current

V

80

125

µA

DD1,2,3

LCD

DD

4x charge pump; f

= 0; T

amb

sclk

= 25°C; no display load; note 3,6

F

osc

= 0

I(V

)

External LCD Supply Voltage

Current

V

=2.8V; V

LCD

=7.6V;no

= 0;

15

25

µA

LDCIN

DD

display load; f

sclk

T

amb

= 25°C; note 3. F

= 0

osc

Logic Inputs

V

Logic LOW voltage level

V

= V (t < 10µs)

V

SS

0.3

V

IL

IN

ih

p

V

DD

V

Logic HIGH Voltage Level

= V (t < 10µs)

0.7

V

IH

il

p

DD2,3

+ 0.5

V

DD

I

Input Current

V

= V

or V

DD1

-1

1

µA

in

SS1

Column and Row Driver

R

ROW Output Resistance

12

20

kohm

mV

row

R

V

Column Output resistance

Column Bias voltage accuracy

Row Bias voltage accuracy

col

No load

-100

100

V

mV

row

LCD Supply Voltage

V

LCD Supply Voltage accuracy;

Internally generated

V

= 2.8V; V = 7.6V;

LCD

-300

300

mV

LCD

DD

fsclk=0; Tamb=25 C;

no display load; note 2, 3, 6 & 7

TC

Temperature coefficient

00

01

10

11

-550

-1350

-1650

-2650

PPM/°C

Notes: 1. The maximum possible V

2. Internal clock

voltage that can be generated is dependent on voltage, temperature and (display) load.

LCD

3. When f

= 0 there is no interface clock.

sclk

4. Power-down mode. During power-down all static currents are switched-off.

5. If external V , the display load current is not transmitted to I

LCD

DD

6. Tolerance depends on the temperature; (typically zero at T

ature range limit.

= 27°C), maximum tolerance values are measured at the temper-

amb

7. For TC0 to TC3

AC OPERATION

(V = 1.9to V

+ 0.5V; V

= 2.4 to 4.5 V; V

= 0V; V

= 4.5 to9V; T

=-40 to 85°C; unless otherwise

DD1

DD2,3

ss1,2

LCD

amb

specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

INTERNAL OSCILLATOR

F

Internal Oscillator frequency

External Oscillator frequency

V

= 2.8V;

DD

20

38

70

kHz

OSC

F

100

EXT

4/36

STE2001

ELECTRICAL CHARACTERISTICS

(continued)

Symbol

Parameter

Frame frequency

Test Condition

fosc or fext = 38 kHz; note 1

Min.

Typ.

Max.

Unit

Hz

ms

ns

F

73

FRAME

T

Vdd1 to RES Low

note 2 and 10; C = 1µF

VLCD

0

5

VHRL

T

RES LOW pulse width

Reset Pulse Rejection

Reset Pulse vs. Device Ready

note 3

600

w(RES)

T

amb

= 25°C; note 11

370

µs

note 11

200

s

µ

T

1

0

ms

START

T

VDD

2

I C BUS INTERFACE (See note 4)

F

SCL Clock Frequency

Fast Mode ; V

=4.5V

DD1

DC

400

kHz

SCL

V

=18V; T

= -20 to 70°C

DD1

amb

High Speed Mode; Cb=100pF

(max); note 6; V =4.5V

DC

3.4

MHz

DD1

High Speed Mode; Cb=400pF

1.7

MHz

(max); note 6 ; V

=4.5V

DD1

T

Cb=100pF

Cb=400pF

Cb=100pF

Cb=400pF

Cb=100pF

Cb=400pF

Cb=100pF

Cb=400pF

Cb=100pF

Cb=400pF

Cb=100pF

Cb=400pF

Cb=100pF

Cb=400pF

Cb=100pF

Cb=400pF

Cb=100pF

Cb=400pF

160

320

ns

SCLL

T

SCLH

T

SCLL

T

SCLH

T

30

SU;DAT

HD;DAT

SU;DAT

HD;DAT

SU;STA

HD;STA

SU;STO

30

Note 8

170

330

170

330

170

330

25

Note 8

T

Note 8

T

Note 5, 8

rCL

T

50

rCL

T

30

rCL1

T

120

30

rCL1

T

rDA

T

120

25

rDA

T

fCL

T

50

5/36

STE2001

ELECTRICAL CHARACTERISTICS

(continued)

Symbol

Parameter

Test Condition

Min.

Typ.

25

Max.

Unit

ns

T

Cb=100pF

Cb=400pF

fDA

120

ns

C

Capacitive load for SDAH and

SCLH

100

400

pF

b

C

b

Capacitive load for SDAH + SDA

line and SCLH + SCL line

pF

ns

T

note 5

10

SW

PARALLEL INTERFACE

T

Enable Cycle Time

Enable Pulse width

Address Set-up Time

Address Hold Time

Data Set-Up Time

Data Hold Time

V

= 4.5V; Write

125

60

30

50

30

50

ns

CY(EN)

DD

T

= 4.5V; Write

W(EN)

T

SU(A)

T

H(A)

T

SU(D)

T

H(D)

SERIAL INTERFACE

F

Clock Frequency

V

= 4.5V

8

5

MHz

ns

SCLK

DD

= 1.8V

DD1

T

Clock Cycle SCLK

SCLK pulse width HIGH

SCLK Pulse width LOW

SCE setup time

= 4.5V

125

70

50

60

40

CYC

DD

T

ns

PWH1

T

PWL1

ns

T

ns

S2

H2

SCE hold time

ns

T

SCE minimum high time

SCE start hold time

SD/C setup time

ns

PWH2

T

Note 8

ns

H5

S3

H3

S4

H4

ns

SD/C hold time

ns

SDIN setup time

ns

SDIN hold time

ns

f_osc

F_frame

Notes: 1.

= --------

520

2. RES may be LOW or HIGH before V

goes HIGH.

DD1

3. If T

is longer than 500ns (typical) a reset may be generated.

w(RES)

4. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to V and V with

IL

IH

an input voltage swing of V to V

SS

DD

5. The rise and fall times specified here refer to the driver device and are part of general Hs-mode specification.

6. The device inputs SDA and SCL are filtered and will reject any spike on the bus-lines of with T

7. Cb is the capacitive load for each bus line.

SW

8. T is the time from the previous SCLK positive edge to the negative edge of SCE

H5

9. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated

10.C is the filtering capacitor on VLCDOUT

VLCD

11.If T

is shorter than max. value a reset pulse is rejected.

w(RES)

6/36

STE2001

CIRCUIT DESCRIPTION

Supplies Voltages and Grounds

V

and V

are supply voltages to the internal voltage generator (see below). They must be externally connected.

DD2

DD3

If the internal voltagegenerator is not used, these should be connected to V pad. V

supplies the rest of the IC.

DD1

This supply voltage could be different form V

and V . V

DD3 DD1

must be lower than V

+ 0.5V.

DD2

DD2,3

Internal Supply Voltage Generator

The IC has a fully integrated (no external capacitors required) charge pump for the LiquidCrystal Display supply volt-

age generation. The multiplying factor can be programmed to be: X5; X4; X3; X2, using the ’set CP Multiplication’

Command. The output voltage (V

) is tightly controlled through the V

pad. For this voltage, four dif-

LCDOUT

LCDSENSE

ferent temperature coefficients(TC, rateof change withtemperature) can be programmed using the bits TC1 and TC0.

This will ensure no contrast degradation over the LCD operating range. Using the internal charge pump, the V

LCDIN

and V

pads must be connected together. An external supply could be connected to V

to supply the LCD

LCDOUT

LCDIN

without using the internal generator. In such event the V

and V

must be connected to GND and the

LDCOUT

LCDSENSE

internal voltage generator must be programmed to zero (PRS = 0, Vop = 0 - Reset condition).

Oscillator

A fully integrated oscillator (requires no external components) is present to provide the clock for the Display System.

Whenused the OSC padmustbe connectedtoVDD1pad. An external oscillatorcould beused andfedintothe OSC pin.

Display Data RAM

The STE2001, provides an 65X128 bits Static RAM to store Display data. This is organized into 8 (Bank0 to

Bank7) banks with 128 Bytes and one Bank (Bank8) with 128 Bits to be used for icons. RAM access is accom-

plished in either one of the Bus Interfaces provided (see below). Allowed addresses are X0 to X127 (Horizontal)

and Y0 to Y8 (Vertical). When writing to RAM, four addressing mode are provided:

• Normal Horizontal (MX = 0 and V = 0), having the columnwith address X = 0 located on the left of the memory map.

The X pointeris increased after each byte written. After the last column address (X = 127), Y address pointer is mod-

ified to jump to next row. X restarts from X = 0 (Fig.2).

• Normal Vertical (MX = 0 and V = 1), having the column with address X = 0 located on the left of the memory map.

The Y pointer is increased after each byte written. After the last row address (Y = 8), the X pointer is modified to

jump to next column and Y restarting from Y = 0. (Fig. 3).

• Mirrored Horizontal (MX = 1 and V = 0), having the column with address X = 0 located on the right of the memory

map. The X pointer is increased after each byte written. After the last column address (X = 127), Y address pointer

is modified to jump to nextrow. X restarts from X = 0 (fig. 4).

• Mirrored Vertical (MX =1 and V = 1), having the column with address X = 0 located on the right of the memory map.

The Y pointer is increased after each byte written. After the last row address (Y = 8), the X pointer is modified to

jump to next column and Y restarting from Y = 0. (Fig. 5).

After the last allowed address (X;Y) = (128;8), the address pointers always jump to the cell with address (X;Y) = (0;0). Data

bytes in the memory could have the MSB either on top (D0 = 0, Fig. 6) or on the bottom (D0 = 1, Fig. 7).

Mux 65 Mode

The STE2001 provides also means to alter the normal output addressing. A mirroring of the Display along the X axis

is enabled setting to a logic one the MY bit. This function is achieved reading the matrix from physical row 63 to 0,

since the relation between the physical memory rows and the output row drivers is only dependent on the memory

reading sequence (1st row read output on R0, 2nd on R1... last on R65). This function doesn’t affect the content of

the memory map. It is only related to the visualizatio nprocess (Fig. 8 & Fig. 9).

It is also possible to modify the why with which row drivers are connected with DDRAM memory. A flip along y-axis of

each sub-block can be applied on both the Row Pads located on the Interface Side (the edge of the chip where the

Interface Pads are located), setting the TRS bit to a logic one, and on the Row Pads located on the other edge, setting

the BRS bit to a logic one.

Figure 2 Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0) Figure 3 Automatic

data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)

7/36

STE2001

Figure 2. Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0)

0

1

2

3

124 125 126 127

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

BANK 8

D00IN1138

Figure 3. Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)

0

1

2

3

124 125 126 127

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

BANK 8

D00IN1139

Figure 4. Automatic data RAM writing sequence with V=0 and Data RAM Mirrored Format (MX=1)

127 126 125 124

3

2

1

0

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

BANK 8

D00IN1140

Figure 5. Automatic data RAM writing sequence with V=1 and Data RAM Mirrored Format (MX=1)

127 126 125 124

3

2

1

0

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

BANK 8

D00IN1141

8/36

STE2001

Figure 6. Data RAM Byte organization with D0 = 0

MSB

0

1

2

3

124 125 126 127

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

BANK 8

LSB

D00IN1142

Figure 7. Data RAM Byte organization with D0 = 1

LSB

0

1

2

3

124 125 126 127

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

BANK 8

MSB

D00IN1143

Figure 8. Output drivers rows and physical memory rows correspondence with MY =0

ROW DRIVER PHYSICAL MEMORY ROW

0

1

2

3

124 125 126 127

R 0

R 1

R 2

R 3

R 4

R 5

ROW 0

ROW 1

ROW 2

ROW 3

ROW 4

ROW 5

R 60

R 61

R 62

R 63

R 64

ROW 60

ROW 61

ROW 62

ROW 63

ROW 64

D00IN1144

Figure 9. Output drivers rows and physical memory rows correspondence with MY =1

ROW DRIVER PHYSICAL MEMORY ROW

0

1

2

3

124 125 126 127

R 63

R 62

R 61

R 60

R 59

R 58

ROW 0

ROW 1

ROW 2

ROW 3

ROW 4

ROW 5

R 3

R 2

R 1

R 0

R 64

ROW 60

ROW 61

ROW 62

ROW 63

ROW 64

D00IN1145

9/36

STE2001

MUX 33 Mode

When using the 1:33 MUX ratio (MUX bit Set), the memory map is changed so that the only ”active” row drivers

are the ones related to Bank4 to Bank7.

When writing data RAM, as for Mux 65, four addressing mode are provided. The memory matrix is written as in

mux 65 mode so the user must take care of updating X and Y pointers to fill the memory matrix in the correct

way.

In MUX 33 mode only the MUX 33 memory logic matrix is read. The MY bit control the reading process. If MY

is set to a logic zero the row reading sequence is 0-1-2..........33 (fig.11). If MY is set to a logic one the reading

sequence is 32....1-33 (Fig 12).

The icon row (BANK8) is always the last being output either MY bit is a logic one or zero.

The functions related to bit TRS is the same as in MUX 65 mode.

In fig. 11 is shown the output drivers pad connection for MUX 33 mode. Note that the unused BANK 0-3 row

drivers become columns drivers.

If a 33x128 LCD matrix is driven, the output row drivers R0-R15 and R32-R47 must be floating.

Figure 10. Physical 65x128 memory matrix and 33x128 correspondence

0

1

14 15 16 17 18

109110 111112 113

126127

BANK 0

BANK 1

BANK 2

BANK 3

BANK 4

BANK 5

BANK 6

BANK 7

BANK 8

NOT USED

D00IN1146

R16-R23

R24-R31

R48-R55

R56-R63

R64

D00IN1147

10/36

STE2001

Figure 11. Output drivers rows and logical memory rows correspondence with MY = 0

ROW DRIVER

MUX 33 PHYSICAL MEMORY ROW

0

1

2

3

4

5

6

7

120 121 122123 124 125126 127

R16

to

Row 0

to

BANK 4

BANK 5

BANK 6

R23

Row 7

R24

Row 8

to

R31

Row15

R48

Row 16

to

R55

Row 23

R56

Row 24

to

BANK 7

BANK 8

R63

Row 31

R64

Row 32

D00IN1148

Figure 12. Output drivers rows and logical memory rows correspondence with MY = 1

ROW DRIVER

MUX 33 PHYSICAL MEMORY ROW

0

1

2

3

4

5

6

7

120 121 122123 124 125126 127

R16

to

R23

R24

to

R31

R48

to

Row 0

to

Row 7

Row 8

to

Row15

Row 16

to

BANK 4

BANK 5

BANK 6

R55

R56

to

Row 23

Row 24

to

BANK 7

BANK 8

R63

Row 31

R64

Row 32

D00IN1148

Instruction Set

Two different instructions formats are provided:

- With D/C set to LOW

commands are sent to the Control circuitry.

- With D/C set to HIGH

the Data RAM is addressed Instructions have the syntax summarized in Table.1.

Reset (RES)

At power-on, all internal registers and RAM content are not defined. A Reset pulse must be applied on RES pad

(active low) to initialize the internal registers content (see Tables 3,4,5,&6). Every on-going communication with

the host controller is interrupted. The IC after the reset pulse is programmed in Power Down mode.

The Default configurations is:

- Horizontal addressing (V = 0)

- Normal instruction set (H = 0)

- Normal display (MX = MY = TRS =BRS = 0)

- MUX 65 mode (MUX = 0)

11/36

STE2001

- Display blank (E = D = 0)

- Address counter X[6: 0] = 0 and Y[3 : 0] = 0

- Temperature coefficient (TC[1 : 0] = 0)

- Bias system (BS[2 : 0] = 0)

- V = 0

OP

- Power Down (PD = 1)

To clear the RAM content a MEMORY BLANK instruction should be executed.

Power Down (PD = 1)

When at Power Down, all LCD outputs are kept at V (display off). Bias generator and V

generator are OFF

SS

LCD

(V

LCDOUT

output is discharged to V , and then is possible to disconnect V

). The internal Oscillator is in

LCDOUT

SS

off state. An external clock can be provided. The RAM contents is not cleared.

Charge Pump Factor

The desired Charge Pump Multiplication Factor can be programmed though the S1 and S0 bits, as follows:

S1

0

S0

0

Multiplication Factor

2X

3X

4X

5X

0

1

0

1

At Reset the X2 factor is selected.

Bias Levels

To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated. The ra-

tios among these levels and VLCD, should be selected according to the MUX ratio (m). They are established to

be (Fig. 14):

+

2

n

3

4

n

2

+

1

+

n 4

------------

-------------

, V

LCD

V

,

V

,

V

,

V

,V

LCD SS

LCD

+

4

n

4

Figure 13. Bias level Generator

V_LCD

R

n + 3

n + 4

·V_LCD

n + 2

n + 4

nR

R

2

n + 4

1

n + 4

R

V_SS

D00IN1150

12/36

STE2001

thus providing an 1/(n+4) ratio, with n calculated from:

=

–

3

n

m

For m = 65, n = 5 and an 1/9 ratio is set.

For m = 33, n =3 and an 1/7 ratio is set.

The STE2001 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below:

BS2

0

BS1

0

BS0

0

n

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

The following table Bias Level for m = 65 and m = 33 are provided:

Symbol

V1

m = 65 (1/9)

m = 33 (1/7)

V

LCD

V2

8/9*V

7/9*V

6/7* V

5/7* V

2/7* V

1/7* V

LCD

V3

V4

2/9*V V

LCD

V5

1/9 *V

V6

V

SS

LCD Voltage Generation

The LCD Voltage at reference temperature (To = 35°C) can be set using the VOP register content according to

the following formula:

V

LCD

(T=To) = V

o = (Ai+V · B)

(i=0,1)

LCD

OP

with the following values:

Symbol

Value

2.90

6.91

0.034

35

Unit

V

Note

Ao

A1

B

PRS = 0

PRS = 1

V

To

°C

Note that the two PRS value produces two adjacent ranges for VLCD. If the register and PRS bit are set to zero

13/36

STE2001

the internal voltage generator is switched off.

The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth) and of the Multiplexing

Rate. A general expression for this is:

+

1

m

----------------------------------- - V

=

V

LCD

th

1

– --------

2

1

m

For MUX Rate m = 65 the ideal V

than:

is:

LCD

V

= 6.85 · V

th

LCD(to)

–

(6.85 V

A )

i

th

= ---------------------------------------- -

V

op

0.03

Temperature Coefficient

As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there’s the need

to vary the LCD Voltage with temperature. The STE2001 provides the possibility to change the VLCD in a linear

fashion against temperature with four different Temperature Coefficient selectable through the TC0 and TC1

bits.

TC1

TC0

Value

-550

Unit

0

1

0

1

0

1

PPM/°C

-1350

-1650

-2650

Figure 14. VLCD Slopes Cross Point with Different TC

V_LCD

TEMP

D01IN1256/mod

35ºC

14/36

STE2001

Figure 15.

V_LCD

B

A₁

A₀+B

A

0

00h 01h 02h 03h 04h 05h

7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h

7Ch 7Dh 7Eh 7Fh

V_O

PRS=0 PRS=1

D01IN1257

Finally, the V

voltage at a given (T) temperature can be calculated as:

LCD

V

(T) = V

o · [1 + (T-To) · TC]

LCD

Memory Blanking Procedure

This instruction allows to fill the memory with ”blank” patterns, in order to delete patterns randomly generated

in memory when starting up the device. This instruction substitutes (128X9) single ”write” instructions. It is pos-

sible to program ”Memory Blanking Procedure” only under the following conditions:

- X address = 0

- Y address = 0

- V bit

= 0

- PD bit

- MX bit

The end of the procedure will be notified on the BSY_FLG pad going HIGH (while LOW the procedure is run-

ning). Any instruction programmed with BSY_FLG LOW will be ignored that is, no instruction can be pro-

grammed for a period equivalent to 128X9 internal write cycles (128X9X1/fclock). The start of Memory blanking

procedure will be between one and two fclock cycles from the last active edge (E rising edge for the parallel

2

interface, last SCLK rising edge for the Serial interface, last SCL rising edge for the I C interface).

Checker Board Procedure

This instruction allows to fill the memory with ”checker-board” pattern. It is mainly intended to developers, who

can now simply obtain complex module test configuration by means of a single instruction. It is possible to pro-

gram ”Checker Board Procedure” only under the following conditions:

- X address = 0

- Y address = 0

- V bit

= 0

- PD bit

- MX bit

15/36

STE2001

The end of the procedure will be notified on theBSY_FLG pad going HIGH, while LOW the procedure is running.

Any instruction programmed with BSY_FLG LOW will be ignored, that is, no instruction can be programmed for

a period equivalent to 128X9 internal write cycles (128X9X1/fclock). The start of Memory blanking procedure

will be between one and two fclock cycles from the last active edge (E rising edge for the parallel interface, last

2

SCLK rising edge for the Serial interface, last SCL rising edge for the I C interface).

Scroll

The STE2001 can scroll the graphics display in units of raster-rows. The scrolling function is achieved changing

the correspondence between the rows of the logical memory map and the output row drivers. The scroll function

doesn’t affect the data ram content. It is only related to the visualization process. The information output on the

drivers is related to the row reading sequence (the 1st row read is output on R0, the 2nd on R1 and so on).

Scrolling means reading the matrix starting from a row that is sequentially increased or decreased. After every

scrolling command the offset between the memory address and the memory scanning pointer is increased or

decreased by one. The offset range is between 0 to 63 in mux 65 mode and 0-31 in mux 33 mode. After the

64th scrolling command in mux 65 mode and after the 32th in mux 33 mode, the offset between the memory

address and the memory scanning pointer is again zero (Cyclic Scrolling). Bank8 is always accessed last in

each frame, and so isn’t scrolled.

If the DIR Bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top down. If

the DIR Bit is set to a logic one the offset register is decreased by one and the raster is scrolled from bottom-up.

Bus Interfaces

To provide the widest flexibility and ease of use the STE2001 features three different methods for interfacing

the host Controller. To select the desired interface the SEL1 and SEL2 pads need to be connected to a logic

LOW (connect to GND) or a logic HIGH (connect to VDD). All the I/O pins of the unused interfaces must be

connected to GND. If I/O pins voltage is lower than VDD interfaces could sink more current than expected.

All interfaces are working while the STE2001 is in Power Down.

SEL2

SEL1

Interface

Note

2

0

Read and Write; Fast and

High Speed Mode

I C

0

1

0

Serial

Parallel

Write only

Not Used

2

I C Interface

2

The I C interface is a fully complying I C bus specification, selectable to work in both Fast (400kHz Clock) and

High Speed Mode (3.4MHz).

This bus is intended for communication between different Ics. It consists of two lines: one bi-directional for data

signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive

supply voltage via an active or passive pull-up.

The following protocol has been defined:

- Data transfer may be initiated only when the bus is not busy.

- During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line

while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

BUS not busy: Both data and clock lines remain High.

Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, define the

START condition.

16/36

STE2001

Stop Data Transfer:

A Change in the state of the data line, from low to High, while the clock signal is High,

defines the STOP condition.

Data Valid: The state of the data line represents valid data when after a start condition, the data line is stable

for the duration of the High period of the clock signal. The data on the line may be changed during the Low period

of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data

bytes transferred between the start and the stop conditions is not limited. The information is transmitted byte-

wide and each receiver acknowledges with the ninth bit.

By definition, a device that gives out a message is called ”transmitter”, the receiving device that gets the signals

is called ”receiver”. The device that controls the message is called ”master”. The devices that are controlled by

the master are called ”slaves”

Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level

put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a

master receiver must generate an acknowledge after the reception of each byte that has been clocked out of

the slave transmitter. The device that acknowledges has to pull down the SDA_IN line during the acknowledge

clock pulse. Of course, setup and hold time must be taken into account. A master receiver must signal an end-

of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of

the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP

condition.

Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the ac-

knowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass

(COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system

SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin

Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the STE2001 will not be able

to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode

that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is nec-

essary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid

LOW level.

2

To be compliant with the I C-bus Hs-mode specification the STE2001 is able to detect the special sequence

”S00001xxx”. After this sequence no acknowledge pulse is generated.

Since no internal modification are applied to work in Hs-mode, the device is able to work in Hs-mode without

detecting the master code.

Figure 16. Bit transfer and START,STOP conditions definition

DATA LINE

STABLE

DATA VALID

CLOCK

DATA

START

CHANGE OF

STOP

CONDITION

DATA ALLOWED

CONDITION

D00IN1151

17/36

STE2001

2

Figure 17. Acknowledgment on theI C-bus

CLOCK PULSE FOR

ACKNOWLEDGEMENT

START

SCLK FROM

MASTER

1

2

8

9

DATA OUTPUT

BY TRANSMITTER

MSB

LSB

DATA OUTPUT

BY RECEIVER

D00IN1152

2

Figure 18. I C-bus timings

Sr

Sr P

t

rDA

fDA

SDAH

t

HD;DAT

t

HD;STA

t

SU;DAT

t

SU;STA

SCLH

t

fCL

t

rCL1

rCL

rCL1

(1)

t

HIGH LOW

LOW HIGH

t

RES

START

=

MCS current source pull-up

= Rp resistor pull-up

D00IN1153

Communication Protocol

2

The STE2001 is an I C slave. The access to the device is bi-directional since data write and status read are allowed.

Two are the device addresses availablefor the device. Both have in common the first 6 bits (011110). The least sig-

nificant bit of the slave address is set by connecting the SA0 input to a logic 0 or to a logic 1.

To start the communication between the bus master and the slaveLCD driver, the master must initiate a START con-

dition. Followingthis, the mastersends an 8-bit byte, shown in Fig. 18, on the SDA bus line (Most significant bit first).

This consists of the 7-bit Device selectCode, and the 1-bit Read/Write Designator (RW/ ).

2

All slaves with the corresponding address acknowledge in parallel, all the others will ignore the IC-bus transfer.

Writing Mode.

If the R/W bit is set to logic 0 the STE2001 is set to be a receiver. After the slaves acknowledge one or more

command word follows to define the status of the device.

A command word is composed by two bytes. The first is a control byte which defines the Co and D/C values,

the second is a data byte (fig 18). The Co bit is the command MSB and defines if after this command will follow

one data byte and an other command word or if will follow a stream of data (Co = 1 Command word, Co = 0

Stream of data). The D/C bit defines whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/

C = 0 Command).

If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and D/C =1, the following

data byte will be stored in the data RAM at the location specified by the data pointer.

E very byte of a command word must be acknowledged by all addressed units.

After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside the STE2001 Display

RAM starting at the address specified by the data pointer. The data pointer is automatically updated after every

byte written and in the end points to the last RAM location written.

Every byte must be acknowledged by all addressed units.

Reading Mode.

If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If the D/C bit sent

during the last write access, is set to a logic 0, the byte read is the status byte.

18/36

STE2001

Figure 19. communication protocol

WRITE MODE

STE2001 ACK

S

S 0 1 1 1 1 0 A 0 A 1 DC Control Byte A

0

DATA Byte

A 0 DC Control Byte A

DATA Byte

A P

R/W Co

SLAVE ADDRESS

Co

LAST

CONTROL BYTE

N> 0 BYTE

MSB........LSB

COMMAND WORD

READ MODE

STE2001 ACK

MASTER

P

S

S R

C D

o C

S 0 1 1 1 1 0 A 1 A

0

0 1 1 1 1 0 A /

0 W

0 0 0 0 0 0 A

R/W

STE2001

SLAVE ADDRESS

CONTROL BYTE

D01IN1247

SERIAL INTERFACE

The STE2001 serial Interface is a unidirectional link between the display driver and the application supervisor.

It consists of four lines: one for data signals (SDIN), one for clock signals (SCLK), one for the peripheral enable

(SCE) and one for mode selection (SD/C).

The serial interface is active only if the SCE line is set to a logic 0. When SCE line is high the serial peripheral

power consumption is zero.

The STE2001 is always a slave on the bus and receive the communication clock on the SCLK pin from the mas-

ter. The STE2001 is only able to receive data.

Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge.

While SCE pin is high the serial interface is kept in reset.

SD/C line status indicates whether the byte is a command (SD/C =0) or RAM data (SD/C =1);it is read on the

eighth SCLK clock pulse during every byte transfer.

If SCE stays low after the last bit of a command/data byte, the serial interface expects the MSB of the next byte

at the next SCLK positive edge.

A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM and all the internal

registers are cleared.

If SCE is low after the positive edge of RES, the serial interface is ready to receive data.

19/36

STE2001

Figure 20. Serial bus protocol - one byte transmission

SCE

D/C

SCLK

SDIN

MSB

LSB

D00IN1159

Figure 21. Serial bus protocol - several byte transmission

SCE

D/C

SCLK

SDIN

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB7

DB6

DB5

D00IN1160

Figure 22. RESET effect on the serial interface

t

PWH2

S2

H2

SCE

D/C

t

H5

t

t(

H5)

S3

H3

t

CYC

t

WH1

PWL1

t

S2

SCLK

SDIN

RES

t

H4

S4

t

START

D00IN1161

20/36

STE2001

Parallel Interface

The STE2001 parallel Interface is a unidirectional link between the display driver and the application supervisor.

It consists of ten lines: eight data lines (from DB7 to DB0) and two control lines. The control lines are: enable

(E) for data latch and PD/C for mode selection.

The data lines and the control line values are internally latched on E rising edge (fig. 23).

Figure 23. Parallel interface timing

PD/C

t

W(en)

SU(A)

t

h(A)

E

t

SU(D) HO(D)

t

CY(en)

DB0-DB7

RES

t

START

D00IN1162

Table 1. Instruction Set

Instruction

D/C R/W

Description

B7

B6 B5

B4 B3 B2 B1 B0

H=0 or H=1

NOP

0

1

0

No Operation

Function Set

MX MY PD

V

H

PowerDown Management; Entry

Mode; Extended Instruction Set

2

Read Status Byte

0

1

0

PD TRS BRS

D

E

MX MY DO

( I C interface only )

Write Data

H=0

D7

D6 D5

D4 D3 D2 D1 D0

Writes data to RAM

Memory Blank

Scroll

0

1

0

1

Starts Memory Blank Procedure

DIR Scrolls by one Row UP or DOWN

V

Range Setting

0

1

0

PRS

E

V

programmingrangeselection

LDC

LCD

Display Control

Set CP Factor

Set RAM Y

Set RAM X

H=1

0

1

D

0

Select Display Configuration

0

1

0

S1

Y1

X1

S0 Charge Pump Multiplication Factor

Y0 Set Horizontal (Y) RAM Address

1

0

Y3

X3

Y2

X2

X6

X5

X4

X0

Set Vertical (X) RAM Address

Checker Board

Multiplex Select

TC Select

0

1

0

1

Starts Checker Board Procedure

Selects MUX factor

MUX

TC1 TC0 Set TemperatureCoefficient for V

LDC

Output Address

Bias Ratios

Reserved

0

1

0

1

0

X

0

1

X

1

0

X

DO TRS BRS Set Row Order on Output Pads

BS2 BS1 BS0

Set desired Bias Ratios

Not to be used

X

Set V

OP6 OP5 OP4 OP3 OP2 OP1 OP0

V

register Write instruction

OP

21/36

STE2001

Table 2. Explanations of Table 6 symbols

RESET

STATE

BIT

0

1

DIR

H

Scroll by one down

Use basic instruction set

Device fully working

Scroll by one up

Use extended instruction set

Device in power down

0

1

0

PD

V

Horizontal addressing

Vertical addressing

MX

MY

TRS

BRS

DO

PRS

MUX

Normal X axis addressing

Image is displayed not vertically mirrored

No top rows mirroring

X axis address is mirrored.

Image is displayed vertically mirrored

Top rows mirroring (row pads 16-31 & 48-64)

Bottom rows mirroring (row pads 0-15 & 32-47)

MSB on BOTTOM

No bottom rows mirroring

MSB on TOP

V

= 2.94V

V

= 6.75V

LCD

1:65 multiplexing ratio

1:33 multiplexing ratio

Table 3.

D

E

0

1

DESCRIPTION

RESET STATE

0

1

0

1

display blank

normal mode

D=0

E=0

all display segments on

inverse video mode

Table 4.

S1

S0

0

DESCRIPTION

RESET STATE

0

1

Multiplication Factor 2X

Multiplication Factor 3X

Multiplication Factor 4X

Multiplication Factor 5X

1

0

1

Table 5.

TC1

TC0

DESCRIPTION

RESET STATE

0

1

0

1

0

1

VLCD temperature Coefficient 0

VLCD temperature Coefficient 1

VLCD temperature Coefficient 2

VLCD temperature Coefficient 3

00

22/36

STE2001

Table 6.

BS2

BS1

0

BS0

0

DESCRIPTION

Bias Ratio equal to 7

RESET STATE

0

1

0

1

Bias Ratio equal to 6

Bias Ratio equal to 5

Bias Ratio equal to 4

Bias Ratio equal to 3

Bias Ratio equal to 2

Bias Ratio equal to 1

Bias Ratio equal to 0

1

0

1

000

0

1

0

1

Figure 24. Application Schematic Using an External LCD Voltage Generator

I/O

VDD2,3

V_DD

32

128

33

VDD1

100nF

V_SS

65 x 128

DISPLAY

VSS2

VSS1

1µF

VLCDSENSE

VLCDOUT

VLCDIN

V_LCD

D00IN1157

Figure 25. Application Schematic using the Internal LCD VoltageGenerator and two separate supplies

I/O

V_DD2

VDD2,3

VDD1

32

128

33

V_DD1

100nF

V_SS

100nF

VSS2

VSS1

65 x 128

DISPLAY

1µF

VLCDSENSE

VLCDOUT

VLCDIN

D00IN1158

23/36

STE2001

Figure 26. Application Schematic using the Internal LCD Voltage Generator and a single supply

I/O

V_DD

VDD2,3

VDD1

32

128

33

100nF

V_SS

65 x 128

DISPLAY

VSS2

VSS1

1µF

VLCDSENSE

VLCDOUT

VLCDIN

D00IN1156

Figure 27. Pad Configuration with I2C interface

TEST_13

TEST_12

TEST_11

TEST_10

TEST_8

VSS2

VSS1

GND

TEST 9

SA0

VDD1/GND/VSSOUT

SCL

SDAIN

SDAOUT

RES

STE2001

µP

E

PD/C

D0

D1

D2

D3

D4

D5

D6

D7

VDD1

SCLK

SCE

SD/C

SDIN

BSY_FLG

TEST_7

TEST_6

TEST_5

TEST_4

VDD3

VDD2

VDD1

OSCIN

SEL1

SEL2

GND/VSSOUT

VSSOUT

TEST_3

TEST_2

TEST_1

TEST_0

D01IN1261

24/36

STE2001

Figure 28. Pad Configuration with Parallel interface

TEST_13

TEST_12

TEST_11

TEST_10

TEST_8

VSS2

VSS1

TEST 9

SA0

GND

VDD1/GND/VSSOUT

VDD1

SCL

SDAIN

SDAOUT

RES

E

STE2001

µP

PD/C

D0

D1

D2

D3

D4

D5

D6

D7

SCLK

SCE

VDD1

SD/C

SDIN

BSY_FLG

TEST_7

TEST_6

TEST_5

TEST_4

VDD3

VDD2

VDD1

OSC

SEL1

SEL2

GND/VSSOUT

VDD1

VSSOUT

TEST_3

TEST_2

TEST_1

TEST_0

D01IN1262

Figure 29. Pad Configuration with Serial interface

TEST_13

TEST_12

TEST_11

TEST_10

TEST_8

VSS2

VSS1

GND

TEST 9

SA0

VDD1/GND/VSSOUT

VDD1

SCL

SDAIN

SDAOUT

STE2001

µP

RES

E

PD/C

D0

D1

D2

VDD1

D3

D4

D5

D6

D7

SCLK

SCE

SD/C

SDIN

BSY_FLG

TEST_7

TEST_6

TEST_5

TEST_4

VDD3

VDD2

VDD1

OSCIN

SEL1

VDD1

SEL2

GND/VSSOUT

VSSOUT

TEST_3

TEST_2

TEST_1

TEST_0

D01IN1263

25/36

STE2001

Figure 30. Power OFF Timing Diagram

VDD2/3

t

VDD

VDD1

RES

INPUTS

D01IN1264

Figure 31. Power OFF Sequence

POWER OFF SEQUENCE

SET by Software (PD=0) or (Vop=0 & PRS=[0;0])

Force Active Input Lines Low

REMOVE VDD1

REMOVE VDD2/3

END OF POWER OFF SEQUENCE

D01IN1265

26/36

STE2001

Figure 32. Power-Up & RESET timing diagram

VDD2/3

t

VDD

VDD1

t

W(RES)

RES

INPUTS

D01IN1189

Figure 33. Power-Up & RESET timing diagram

VDD2/3

t

VHRL

t

VDD

VDD1

t

W(RES)

RES

INPUTS

D01IN1190

Figure 34. Power Up Sequence

POWER UP SEQUENCE

Set Active Input lines low

Apply VDD2/3

Apply VDD1

Apply a RESET Pulse

END OF POWER UP SEQUENCE

(STE2001 in Reset State)

D01IN1266

27/36

STE2001

Figure 35. Chip Mechanical Drawing

ALIGNEMENT MARK

ROW 0

ROW16

ROW 15

COL 0

ROW31

TEST

ALIGNEMENT MARK

VLCDIN

VLCDSENSE

VLCDOUT

VSS2

VSS1

TEST

SA0

SCL

SDAIN

SDAOUT

RES

E

PD/C

D0

D1

D2

D3

D4

D5

D6

D7

COL 63

COL 64

(0,0)

Y

X

SCLK

SCE

SD/C

SDIN

BSY_FLG

TEST

VDD2

VDD3

VDD1

OSC

SEL1

SEL2

VSSOUT

TEST

COL 127

ROW 47

ALIGNEMENT MARK

ROW64

ROW 32

ROW48

ALIGNEMENT MARK

D01IN1191

28/36

STE2001

Figure 36. Improved ALTH & PLESKO Driving Method

V_LCD

V₂

V₃

∆V₁(t)

∆V₂(t)

ROW 0

R0 (t)

V₄

V₅

V_SS

V_LCD

V₂

V₃

ROW 1

R1 (t)

V₄

V₅

V_SS

V_LCD

V₂

V₃

COL 0

C0 (t)

V₄

V₅

V_SS

V_LCD

V₂

V₃

COL 1

C1 (t)

V₄

V₅

V_SS

V_LCD- V_SS

V₃- V_SS

V

_LCD- V₂

0V

V₄- V₅

V_state1(t)

0V

V₃- V_SS

V_SS- V₅

V₄- V_LCD

V_LCD- V_SS

V₃- V_SS

V_SS- V_LCD

V_LCD- V₂

0V

V₄- V₅

0V

V_state2(t)

V₃- V_SS

V_SS- V₅

V₄- V_LCD

V_SS- V_LCD

.......

0

..... 64

1 2 3 4 5 6 7 8

9

..... 64

0 1 2 3 4 5 6 7 8 9

FRAME n

FRAME n + 1

D00IN1154

∆V₁(t) = C1(t) - R0(t)

∆V₂(t) = C1(t) - R1(t)

29/36

STE2001

Figure 37. DATA RAM to display Mapping

DISPLAY DATA RAM

bank

0

GLASS

TOP VIEW

bank

1

DISPLAY DATA RAM = ”1”

DISPLAY DATA RAM = ”0”

bank

2

LCD

bank

3

bank

7

bank

8

ICOR ROW

D00IN1155

Table 7. Test Pin Configuration

Test Numb.

TEST_0

TEST_1

TEST_2

TEST_3

GND

TEST_4

TEST_5

TEST_6

TEST_7

OPEN

T8

T9

OPEN

TEST_10

TEST_11

TEST_12

TEST_13

OPEN

30/36

STE2001

Table 8. Mechanical Dimensions

Table 9. Pad Coordinates

(continued)

NAME

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

C27

C28

C29

C30

C31

C32

C33

C34

C35

C36

C37

C38

C39

C40

C41

C42

C43

C44

C45

C46

C47

C48

C49

PAD

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

X ( m)

Y( m)

µ

Die Size

2.12mmX12.5mm

-3,681.8

-3,611.8

-3,541.8

-3,471.8

-3,401.8

-3,331.8

-3,261.8

-3,191.8

-3,121.8

-3,051.8

-2,981.8

-2,911.8

-2,841.8

-2,771.8

-2,701.8

-2,631.8

-2,561.8

-2,491.8

-2,421.8

-2,351.8

-2,281.8

-2,211.8

-2,141.8

-2,071.8

-2,001.8

-1,931.8

-1,861.8

-1,791.8

-1,721.8

-1,651.8

-1,581.8

-1,511.8

-1,441.8

-1,371.8

-1,301.8

-1,231.8

-1,161.8

-898.2

Pad Pitch

70 µm

62µm X 100 µm

50µmX88µmX17.5

500µm

Pad Size

Bump Dimensions

WFS Thickness

Table 9. Pad Coordinates

NAME

R0

PAD

1

X (µm)

Y(µm)

-898.2

-5,994

-5,924

R1

2

R2

3

-5,854

R3

4

-5,784

R4

5

-5,714

R5

6

-5,644

R6

7

-5,574

R7

8

-5,504

R8

9

-5,434

R9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

-5,364

R10

R11

R12

R13

R14

R15

C0

-5,294

-5,224

-5,154

-5,084

-5,014

-4,944

-4,591.8

-4,521.8

-4,451.8

-4,381.8

-4,311.8

-4,241.8

-4,171.8

-4,101.8

-4,031.8

-3,961.8

-3,891.8

-3,821.8

-3,751.8

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

31/36

STE2001

Table 9. Pad Coordinates

(continued)

NAME

C50

C51

C52

C53

C54

C55

C56

C57

C58

C59

C60

C61

C62

C63

C64

C65

C66

C67

C68

C69

C70

C71

C72

C73

C74

C75

C76

C77

C78

C79

C80

C81

C82

C83

C84

C85

C86

PAD

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

X ( m)

Y( m)

NAME

PAD

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

X ( m)

Y( m)

µ

-1,091.8

-1,021.8

-951.8

-898.2

C87

1,785.44

1,855.44

1,925.44

1,995.44

2,065.44

2,135.44

2,205.44

2,275.44

2,345.44

2,415.44

2,485.44

2,555.44

2,625.44

2,695.44

2,765.44

2,835.44

2,905.44

2,975.44

3,045.44

3,115.44

3,185.44

3,255.44

3,325.44

3,395.44

3,465.44

3,535.44

3,605.44

3,675.44

3,745.44

3,815.44

3,885.44

3,955.44

4,025.44

4,095.44

4,165.44

4,235.44

4,305.44

-898.2

C88

C89

-881.8

C90

C91

-811.8

-741.8

C92

C93

-671.8

-601.8

C94

-531.8

C95

-461.8

C96

-391.8

C97

C98

-321.8

-251.8

C99

C100

C101

C102

C103

C104

C105

C106

C107

C108

C109

C110

C111

C112

C113

C114

C115

C116

C117

C118

C119

C120

C121

C122

C123

-181.8

175.44

245.44

315.44

385.44

455.44

525.44

595.44

665.44

735.44

805.44

875.44

945.44

1,015.44

1,085.44

1,155.44

1,225.44

1,295.44

1,365.44

1,435.44

1,505.44

1,575.44

1,645.44

1,715.44

32/36

STE2001

Table 9. Pad Coordinates

(continued)

NAME

C124

C125

C126

C127

R47

R46

R45

R44

R43

R42

R41

R40

R39

R38

R37

R36

R35

R34

R33

R32

R48

R49

R50

R51

R52

R53

R54

R55

R56

R57

R58

R59

R60

R61

R62

R63

R64

PAD

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

X ( m)

Y( m)

NAME

TEST_3

TEST_2

TEST_1

TEST_0

VSSOUT

SEL2

PAD

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

213

214

X ( m)

Y( m)

µ

4,375.44

4,445.44

4,515.44

4,585.44

4,943.84

5,013.84

5,083.84

5,153.84

5,223.84

5,293.84

5,363.84

5,433.84

5,503.84

5,573.84

5,643.84

5,713.84

5,783.84

5,853.84

5,923.84

5,993.84

6,021.92

5,951.92

5,881.92

5,811.92

5,741.92

5,671.92

5,601.92

5,531.92

5,461.92

5,391.92

5,321.92

5,251.92

5,181.92

5,111.92

5,041.92

4,971.92

4,901.92

-898.2

898.2

4,640.52

4,500.68

4,360.84

4,221

898.2

4,151

4,011.16

3,871.32

3,731.48

3,661.48

3,591.48

3,521.48

3,451.48

3,381.48

3,311.48

3,223.08

3,153.08

3,083.08

2,994.68

2,924.68

2,854.68

2,784.68

2,714.68

2,644.68

2,574.68

2,033.84

1,894

SEL1

OSC

VDD1_1

VDD1_2

VDD1_3

VDD1_4

VDD1_5

VDD1_6

VDD3_1

VDD3_2

VDD3_3

VDD2_1

VDD2_2

VDD2_3

VDD2_4

VDD2_5

VDD2_6

VDD2_7

TEST_7

TEST_6

TEST_5

TEST_4

BSY_FLAG

SDIN

1,754.16

1,614.32

1,474.48

1,333.2

1,193.36

1,053.52

913.68

SD/C

SCE

SCLK

D7

773.84

D6

634

D5

494.16

D4

354.32

33/36

STE2001

Table 9. Pad Coordinates

(continued)

NAME

D3

PAD

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

242

243

244

245

246

247

248

249

250

251

X ( m)

Y( m)

NAME

TEST_12

TEST_13

TEST_10

TEST_11

TEST_8

R31

PAD

252

253

254

255

256

257

258

259

260

261

262

263

264

265

266

267

268

269

270

271

272

X ( m)

Y( m)

µ

214.48

898.2

-4,460.48

-4,540.48

-4,620.48

-4,700.48

-4,780.48

-4,971.92

-5,041.92

-5,111.92

-5,181.92

-5,251.92

-5,321.92

-5,391.92

-5,461.92

-5,531.92

-5,601.92

-5,671.92

-5,741.92

-5,811.92

-5,881.92

-5,951.92

-6,021.92

898.2

D2

74.64

D1

-65.2

D0

-205.04

PD/C

-344.88

E

-484.72

RES

R30

-624.56

SDA_OUT

SDA_IN

SCL

-764.4

R29

-904.24

R28

-1,044.08

-1,183.92

-1,722.04

-1,795.48

-1,865.48

-1,935.48

-2,075.88

-2,145.88

-2,215.88

-2,356.28

-2,426.28

-2,496.28

-2,636.68

-2,706.68

-2,776.68

-3,545.64

-3,615.64

-3,685.64

-3,755.64

-3,825.64

-3,895.64

-3,968.08

-4,040.48

-4,110.48

-4,180.48

-4,250.48

-4,320.48

-4,390.48

R27

SA0

R26

TEST9

R25

VSS1_1

VSS1_2

VSS1_3

VSS1_4

VSS1_5

VSS1_6

VSS2_1

VSS2_2

VSS2_3

VSS2_4

VSS2_5

VSS2_6

VLCDOUT1

VLCDOUT2

VLCDOUT3

VLCDOUT4

VLCDOUT5

VLCDOUT6

VLCSENSE

VLCDIN_1

VLCDIN_2

VLCDIN_3

VLCDIN_4

VLCDIN_5

VLCDIN_6

R24

R23

R22

R21

R20

R19

R18

R17

R16

Table 10. Alignment marks coordinates

X

Y

MARKS

mark1

mark2

mark3

mark4

4806.2

-4876.2

-6092.6

6092.6

901.8

-901.8

Figure 38. Alignment marks dimensions

34/36

STE2001

Figure 39.

DIE IDENTIFICATION

STE2001

R16

D01IN1249

Figure 40. Tray Information

0DIN1428

2 . 3 9

G m b H A R W E

F L U O R O

0 ± . 2 5 4 1 = . 4 7 3 . 1 x 9 1 3

35/36

STE2001

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights ofthird partieswhich may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

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36/36


型号：	STE2001DIE2
厂家：	ST
描述：	65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER 65 X 128单芯片LCD控制器/驱动显示驱动器驱动程序和接口接口集成电路控制器 CD
文件：	总36页 (文件大小：314K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STE2001DIE2 [STMICROELECTRONICS]

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STE2004DIE2

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STE2007

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STE2007_06